Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	162568091	23934895	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	162568091	23934895	0	59
T1	469450	229882	0	0
T2	24995	6981	0	1
T3	0	452601	0	0
T5	32116	0	0	0
T12	0	5324	0	1
T13	0	39423	0	0
T14	0	103675	0	0
T15	0	24690	0	1
T16	0	2584	0	1
T17	0	0	0	1
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T22	24749	1442	0	1
T23	2532	0	0	0
T24	652	0	0	0
T25	819	0	0	0
T27	0	929	0	1
T64	0	0	0	1
T65	0	0	0	1
T98	0	0	0	1