Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	1005579	0	0
SrcPulseCheck_M	2147483647	1002672	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	1005579
T1	3869971	8414
T2	0	380
T3	0	5138
T4	137711	50
T5	409739	170
T6	296414	390
T12	0	318
T13	0	8189
T19	8529	0
T20	35006	0
T21	19663	0
T22	384959	248
T23	43189	0
T26	10579	0
T27	0	212
T30	0	1128
T31	0	892
T51	23312	2
T53	10709	0
T54	27264	2
T55	14628	3
T100	8582	3
T101	16252	1
T102	10130	1
T103	8600	1
T104	10721	1
T105	9051	1
T106	14511	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	1002672
T1	2633223	8417
T2	0	380
T3	0	5138
T4	34468	50
T5	101267	170
T6	79060	390
T12	0	318
T13	0	7710
T19	5001	0
T20	11115	0
T21	8102	0
T22	98429	248
T23	13843	0
T26	6249	0
T27	0	212
T30	0	1128
T31	0	892
T51	138504	2
T53	56015	0
T54	11396	2
T55	26620	3
T100	22820	3
T101	6902	1
T102	8676	1
T103	14420	1
T104	18351	1
T105	3670	1
T106	6503	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	448300910	26916	0	0
SrcPulseCheck_M	163552307	26916	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	448300910	26916
T1	892055	505
T2	0	32
T3	0	266
T4	38371	10
T5	123327	34
T6	72637	14
T12	0	26
T19	1804	0
T20	8158	0
T21	4393	0
T22	95035	16
T23	9727	0
T26	2212	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	26916
T1	469450	505
T2	0	32
T3	0	266
T4	9992	10
T5	32116	34
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	448300910	33120	0	0
SrcPulseCheck_M	163552307	33130	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	448300910	33120
T1	892055	516
T2	0	32
T3	0	271
T4	38371	20
T5	123327	68
T6	72637	14
T12	0	26
T19	1804	0
T20	8158	0
T21	4393	0
T22	95035	16
T23	9727	0
T26	2212	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	33130
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	33111	0	0
SrcPulseCheck_M	448300910	33124	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	33111
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	448300910	33124
T1	892055	516
T2	0	32
T3	0	271
T4	38371	20
T5	123327	68
T6	72637	14
T12	0	26
T19	1804	0
T20	8158	0
T21	4393	0
T22	95035	16
T23	9727	0
T26	2212	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	223265656	26916	0	0
SrcPulseCheck_M	163552307	26916	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	223265656	26916
T1	445547	505
T2	0	32
T3	0	266
T4	14108	10
T5	35951	34
T6	36306	14
T12	0	26
T19	869	0
T20	4661	0
T21	2428	0
T22	47479	16
T23	5943	0
T26	1087	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	26916
T1	469450	505
T2	0	32
T3	0	266
T4	9992	10
T5	32116	34
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	223265656	33103	0	0
SrcPulseCheck_M	163552307	33139	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	223265656	33103
T1	445547	516
T2	0	32
T3	0	271
T4	14108	20
T5	35951	68
T6	36306	14
T12	0	26
T19	869	0
T20	4661	0
T21	2428	0
T22	47479	16
T23	5943	0
T26	1087	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	33139
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	33098	0	0
SrcPulseCheck_M	223265656	33106	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	33098
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	223265656	33106
T1	445547	516
T2	0	32
T3	0	271
T4	14108	20
T5	35951	68
T6	36306	14
T12	0	26
T19	869	0
T20	4661	0
T21	2428	0
T22	47479	16
T23	5943	0
T26	1087	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111632203	26916	0	0
SrcPulseCheck_M	163552307	26916	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	111632203	26916
T1	222772	505
T2	0	32
T3	0	266
T4	7053	10
T5	17974	34
T6	18153	14
T12	0	26
T19	435	0
T20	2328	0
T21	1212	0
T22	23739	16
T23	2969	0
T26	543	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	26916
T1	469450	505
T2	0	32
T3	0	266
T4	9992	10
T5	32116	34
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111632203	33004	0	0
SrcPulseCheck_M	163552307	33035	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	111632203	33004
T1	222772	516
T2	0	32
T3	0	271
T4	7053	20
T5	17974	68
T6	18153	14
T12	0	26
T19	435	0
T20	2328	0
T21	1212	0
T22	23739	16
T23	2969	0
T26	543	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	33035
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	33002	0	0
SrcPulseCheck_M	111632203	33006	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	33002
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	111632203	33006
T1	222772	516
T2	0	32
T3	0	271
T4	7053	20
T5	17974	68
T6	18153	14
T12	0	26
T19	435	0
T20	2328	0
T21	1212	0
T22	23739	16
T23	2969	0
T26	543	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	478112687	26916	0	0
SrcPulseCheck_M	163552307	26916	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	478112687	26916
T1	949053	505
T2	0	32
T3	0	266
T4	39971	10
T5	128469	34
T6	75667	14
T12	0	26
T19	1879	0
T20	8498	0
T21	4577	0
T22	98999	16
T23	10132	0
T26	2304	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	26916
T1	469450	505
T2	0	32
T3	0	266
T4	9992	10
T5	32116	34
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	478112687	33116	0	0
SrcPulseCheck_M	163552307	33138	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	478112687	33116
T1	949053	516
T2	0	32
T3	0	271
T4	39971	20
T5	128469	68
T6	75667	14
T12	0	26
T19	1879	0
T20	8498	0
T21	4577	0
T22	98999	16
T23	10132	0
T26	2304	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	33138
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	33104	0	0
SrcPulseCheck_M	478112687	33121	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	33104
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	478112687	33121
T1	949053	516
T2	0	32
T3	0	271
T4	39971	20
T5	128469	68
T6	75667	14
T12	0	26
T19	1879	0
T20	8498	0
T21	4577	0
T22	98999	16
T23	10132	0
T26	2304	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	229522013	26413	0	0
SrcPulseCheck_M	163552307	26916	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	229522013	26413
T1	456129	505
T2	0	32
T3	0	266
T4	19186	8
T5	61666	17
T6	42081	14
T12	0	26
T19	902	0
T20	4079	0
T21	2197	0
T22	47520	16
T23	4863	0
T26	1105	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	26916
T1	469450	505
T2	0	32
T3	0	266
T4	9992	10
T5	32116	34
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	229522013	32810	0	0
SrcPulseCheck_M	163552307	32982	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	229522013	32810
T1	456129	516
T2	0	32
T3	0	271
T4	19186	20
T5	61666	68
T6	42081	14
T12	0	26
T19	902	0
T20	4079	0
T21	2197	0
T22	47520	16
T23	4863	0
T26	1105	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163552307	32982
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	68
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T4,T1
1	0	Covered	T6,T4,T1
1	1	Covered	T6,T4,T1

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	32607	0	0
SrcPulseCheck_M	229522013	32842	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	32607
T1	469450	516
T2	0	32
T3	0	271
T4	9992	20
T5	32116	51
T6	21039	14
T12	0	26
T19	1804	0
T20	2039	0
T21	2197	0
T22	24749	16
T23	2532	0
T26	2259	0
T30	0	40
T31	0	36

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	229522013	32842
T1	456129	516
T2	0	32
T3	0	271
T4	19186	20
T5	61666	68
T6	42081	14
T12	0	26
T19	902	0
T20	4079	0
T21	2197	0
T22	47520	16
T23	4863	0
T26	1105	0
T30	0	40
T31	0	36

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T53,T54,T55
1	0	Covered	T53,T54,T55
1	1	Covered	T106,T107,T108

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T53,T54,T55
1	0	Covered	T106,T107,T108
1	1	Covered	T53,T54,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	40	0	0
SrcPulseCheck_M	448300910	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	40
T53	10709	1
T54	13632	1
T55	7314	1
T100	4291	2
T101	8126	1
T102	5065	2
T106	14511	3
T109	11804	1
T110	10017	1
T111	10094	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	448300910	40
T53	114236	1
T54	13490	1
T55	28087	1
T100	24236	2
T101	7801	1
T102	9724	2
T106	14511	3
T109	47217	1
T110	9913	1
T111	19775	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T56
1	0	Covered	T54,T55,T56
1	1	Covered	T57,T106,T111

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T54,T55,T56
1	0	Covered	T57,T106,T111
1	1	Covered	T54,T55,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	42	0	0
SrcPulseCheck_M	448300910	42	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	42
T54	13632	2
T55	7314	1
T56	6217	2
T57	13031	2
T100	4291	3
T101	8126	1
T102	5065	2
T106	14511	3
T109	11804	1
T110	10017	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	448300910	42
T54	13490	2
T55	28087	1
T56	5968	2
T57	13899	2
T100	24236	3
T101	7801	1
T102	9724	2
T106	14511	3
T109	47217	1
T110	9913	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T54,T55
1	0	Covered	T51,T54,T55
1	1	Covered	T55,T100,T112

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T54,T55
1	0	Covered	T55,T100,T112
1	1	Covered	T51,T54,T55

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	35	0	0
SrcPulseCheck_M	223265656	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	35
T51	11656	2
T54	13632	2
T55	7314	3
T100	4291	3
T101	8126	1
T102	5065	1
T103	4300	1
T104	10721	1
T105	9051	1
T106	14511	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	223265656	35
T51	69252	2
T54	5698	2
T55	13310	3
T100	11410	3
T101	3451	1
T102	4338	1
T103	7210	1
T104	18351	1
T105	3670	1
T106	6503	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T53,T54
1	0	Covered	T51,T53,T54
1	1	Covered	T55,T112,T113

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T53,T54
1	0	Covered	T55,T112,T113
1	1	Covered	T51,T53,T54

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	37	0	0
SrcPulseCheck_M	223265656	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	37
T51	11656	1
T53	10709	1
T54	13632	3
T55	7314	3
T100	4291	2
T101	8126	1
T102	5065	1
T103	4300	2
T114	5513	1
T115	4564	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	223265656	37
T51	69252	1
T53	56015	1
T54	5698	3
T55	13310	3
T100	11410	2
T101	3451	1
T102	4338	1
T103	7210	2
T114	2302	1
T115	2958	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T52,T53
1	0	Covered	T51,T52,T53
1	1	Covered	T51,T111,T116

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T52,T53
1	0	Covered	T51,T111,T116
1	1	Covered	T51,T52,T53

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	30	0	0
SrcPulseCheck_M	111632203	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	30
T51	11656	2
T52	15691	1
T53	10709	2
T55	7314	1
T57	13031	2
T100	4291	1
T102	5065	1
T104	10721	1
T105	9051	1
T111	10094	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	111632203	30
T51	34626	2
T52	3566	1
T53	28007	2
T55	6654	1
T57	2971	2
T100	5707	1
T102	2168	1
T104	9177	1
T105	1834	1
T111	4379	3

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T52,T53
1	0	Covered	T51,T52,T53
1	1	Covered	T51,T112,T117

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T52,T53
1	0	Covered	T51,T112,T117
1	1	Covered	T51,T52,T53

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	31	0	0
SrcPulseCheck_M	111632203	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	31
T51	11656	2
T52	15691	1
T53	10709	1
T55	7314	1
T57	13031	2
T100	4291	1
T105	9051	1
T111	10094	2
T114	5513	1
T115	4564	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	111632203	31
T51	34626	2
T52	3566	1
T53	28007	1
T55	6654	1
T57	2971	2
T100	5707	1
T105	1834	1
T111	4379	2
T114	1153	1
T115	1480	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T53,T54,T55
1	0	Covered	T53,T54,T55
1	1	Covered	T54,T55,T103

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T53,T54,T55
1	0	Covered	T54,T55,T103
1	1	Covered	T53,T54,T55

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	33	0	0
SrcPulseCheck_M	478112687	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	33
T53	10709	1
T54	13632	2
T55	7314	6
T57	13031	1
T100	4291	2
T102	5065	1
T103	4300	2
T104	10721	1
T109	11804	1
T118	5611	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	478112687	33
T53	118999	1
T54	14053	2
T55	29258	6
T57	14479	1
T100	25247	2
T102	10131	1
T103	15928	2
T104	39711	1
T109	49187	1
T118	11222	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T52,T53,T54
1	0	Covered	T52,T53,T54
1	1	Covered	T54,T55,T56

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T52,T53,T54
1	0	Covered	T54,T55,T56
1	1	Covered	T52,T53,T54

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	35	0	0
SrcPulseCheck_M	478112687	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	35
T52	15691	1
T53	10709	1
T54	13632	2
T55	7314	3
T56	6217	2
T57	13031	2
T100	4291	1
T102	5065	1
T109	11804	1
T118	5611	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	478112687	35
T52	16692	1
T53	118999	1
T54	14053	2
T55	29258	3
T56	6217	2
T57	14479	2
T100	25247	1
T102	10131	1
T109	49187	1
T118	11222	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T53,T55
1	0	Covered	T51,T53,T55
1	1	Covered	T119,T107

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T53,T55
1	0	Covered	T119,T107
1	1	Covered	T51,T53,T55

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	34	0	0
SrcPulseCheck_M	229522013	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	34
T51	11656	1
T53	10709	2
T55	7314	1
T104	10721	1
T106	14511	1
T110	10017	1
T114	5513	1
T118	5611	1
T120	8999	2
T121	15561	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	229522013	34
T51	69942	1
T53	57120	2
T55	14044	1
T104	19062	1
T106	7256	1
T110	4956	1
T114	2757	1
T118	5387	1
T120	4499	2
T121	7781	2

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T53,T54
1	0	Covered	T51,T53,T54
1	1	Covered	T55,T119,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T51,T53,T54
1	0	Covered	T55,T119,T122
1	1	Covered	T51,T53,T54

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163552307	42	0	0
SrcPulseCheck_M	229522013	42	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163552307	42
T51	11656	1
T53	10709	3
T54	13632	1
T55	7314	2
T57	13031	1
T106	14511	1
T110	10017	2
T114	5513	1
T115	4564	1
T118	5611	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	229522013	42
T51	69942	1
T53	57120	3
T54	6745	1
T55	14044	2
T57	6950	1
T106	7256	1
T110	4956	2
T114	2757	1
T115	3478	1
T118	5387	2

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	445693197	101592	0	0
SrcPulseCheck_M	14617958	100444	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	445693197	101592
T1	892055	1621
T2	0	71
T3	0	1158
T4	38371	0
T5	123327	0
T6	72637	87
T12	0	60
T13	0	1969
T19	1804	0
T20	8158	0
T21	4393	0
T22	95035	50
T23	9727	0
T26	2212	0
T27	0	53
T30	0	237
T31	0	175

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14617958	100444
T1	312095	1622
T2	0	71
T3	0	1158
T4	94	0
T5	271	0
T6	169	87
T12	0	60
T13	0	1809
T19	131	0
T20	594	0
T21	320	0
T22	363	50
T23	709	0
T26	161	0
T27	0	53
T30	0	237
T31	0	175

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	222009492	100896	0	0
SrcPulseCheck_M	14617958	99757	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	222009492	100896
T1	445547	1621
T2	0	71
T3	0	1085
T4	14108	0
T5	35951	0
T6	36306	87
T12	0	60
T13	0	1969
T19	869	0
T20	4661	0
T21	2428	0
T22	47479	50
T23	5943	0
T26	1087	0
T27	0	53
T30	0	237
T31	0	175

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14617958	99757
T1	312095	1622
T2	0	71
T3	0	1085
T4	94	0
T5	271	0
T6	169	87
T12	0	60
T13	0	1809
T19	131	0
T20	594	0
T21	320	0
T22	363	50
T23	709	0
T26	161	0
T27	0	53
T30	0	237
T31	0	175

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111004119	99574	0	0
SrcPulseCheck_M	14617958	98446	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	111004119	99574
T1	222772	1621
T2	0	71
T3	0	1045
T4	7053	0
T5	17974	0
T6	18153	87
T12	0	60
T13	0	1967
T19	435	0
T20	2328	0
T21	1212	0
T22	23739	50
T23	2969	0
T26	543	0
T27	0	53
T30	0	237
T31	0	175

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14617958	98446
T1	312095	1622
T2	0	71
T3	0	1045
T4	94	0
T5	271	0
T6	169	87
T12	0	60
T13	0	1807
T19	131	0
T20	594	0
T21	320	0
T22	363	50
T23	709	0
T26	161	0
T27	0	53
T30	0	237
T31	0	175

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	475396197	120267	0	0
SrcPulseCheck_M	14850961	120205	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	475396197	120267
T1	949053	2014
T2	0	71
T3	0	1042
T4	39971	0
T5	128469	0
T6	75667	87
T12	0	60
T13	0	2284
T19	1879	0
T20	8498	0
T21	4577	0
T22	98999	50
T23	10132	0
T26	2304	0
T27	0	53
T30	0	297
T31	0	259

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14850961	120205
T1	312491	2014
T2	0	71
T3	0	1042
T4	94	0
T5	271	0
T6	169	87
T12	0	60
T13	0	2285
T19	131	0
T20	594	0
T21	320	0
T22	363	50
T23	709	0
T26	161	0
T27	0	53
T30	0	297
T31	0	259

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Covered	T6,T1,T22
1	0	Covered	T6,T1,T22
1	1	Covered	T6,T1,T22

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T7,T8,T9

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	228218127	118739	0	0
SrcPulseCheck_M	15126529	118258	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	228218127	118739
T1	456129	2038
T2	0	71
T3	0	955
T4	19186	0
T5	61666	0
T6	42081	111
T12	0	60
T13	0	2408
T19	902	0
T20	4079	0
T21	2197	0
T22	47520	50
T23	4863	0
T26	1105	0
T27	0	53
T30	0	261
T31	0	259

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15126529	118258
T1	312515	2038
T2	0	71
T3	0	955
T4	94	0
T5	271	0
T6	193	111
T12	0	60
T13	0	2408
T19	131	0
T20	594	0
T21	320	0
T22	363	50
T23	709	0
T26	161	0
T27	0	53
T30	0	261
T31	0	259

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb