Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	163552307	5119867	0	0
clk_enables_rd_A	163552307	43599	0	0
clk_hints_rd_A	163552307	38881	0	0
extclk_ctrl_rd_A	163552307	49085	0	0
extclk_ctrl_regwen_rd_A	163552307	37151	0	0
jitter_enable_rd_A	163552307	57446	0	0
jitter_regwen_rd_A	163552307	41458	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163552307	5119867	0	0
T1	469450	222485	0	0
T2	24995	0	0	0
T3	0	73622	0	0
T5	32116	0	0	0
T13	0	141538	0	0
T14	0	125097	0	0
T18	0	22961	0	0
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T22	24749	0	0	0
T23	2532	0	0	0
T24	652	0	0	0
T25	819	0	0	0
T28	0	122845	0	0
T29	0	110937	0	0
T58	0	131124	0	0
T59	0	173423	0	0
T60	0	88879	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163552307	43599	0	0
T3	249839	2962	0	0
T12	20210	0	0	0
T15	0	13	0	0
T18	0	903	0	0
T30	65972	0	0	0
T32	1691	0	0	0
T39	8444	0	0	0
T58	0	5505	0	0
T61	2583	0	0	0
T62	1329	0	0	0
T68	0	7	0	0
T94	1206	0	0	0
T95	2280	0	0	0
T96	0	1	0	0
T99	2586	0	0	0
T123	0	2	0	0
T124	0	8	0	0
T125	0	5	0	0
T126	0	1769	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163552307	38881	0	0
T3	249839	2606	0	0
T12	20210	0	0	0
T15	0	1	0	0
T18	0	821	0	0
T30	65972	0	0	0
T32	1691	0	0	0
T39	8444	0	0	0
T58	0	4501	0	0
T61	2583	0	0	0
T62	1329	0	0	0
T68	0	2	0	0
T94	1206	0	0	0
T95	2280	0	0	0
T96	0	7	0	0
T99	2586	0	0	0
T123	0	3	0	0
T124	0	6	0	0
T127	0	7	0	0
T128	0	4	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163552307	49085	0	0
T1	469450	0	0	0
T3	0	3519	0	0
T4	9992	28	0	0
T6	21039	0	0	0
T7	2447	52	0	0
T8	1075	14	0	0
T9	666	0	0	0
T15	0	38	0	0
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T23	0	66	0	0
T26	2259	0	0	0
T63	0	56	0	0
T129	0	14	0	0
T130	0	17	0	0
T131	0	14	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163552307	37151	0	0
T1	469450	0	0	0
T3	0	2721	0	0
T4	9992	23	0	0
T5	32116	0	0	0
T18	0	852	0	0
T19	1804	0	0	0
T20	2039	0	0	0
T21	2197	0	0	0
T22	24749	0	0	0
T23	2532	0	0	0
T24	652	0	0	0
T26	2259	0	0	0
T58	0	4379	0	0
T63	0	35	0	0
T126	0	1711	0	0
T132	0	23	0	0
T133	0	16	0	0
T134	0	24	0	0
T135	0	447	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163552307	57446	0	0
T3	249839	3365	0	0
T12	20210	0	0	0
T15	0	135	0	0
T18	0	1793	0	0
T30	65972	0	0	0
T32	1691	0	0	0
T39	8444	0	0	0
T41	0	121	0	0
T58	0	6934	0	0
T61	2583	0	0	0
T62	1329	0	0	0
T94	1206	0	0	0
T95	2280	0	0	0
T96	0	133	0	0
T99	2586	0	0	0
T123	0	148	0	0
T124	0	102	0	0
T125	0	127	0	0
T127	0	92	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163552307	41458	0	0
T3	249839	2770	0	0
T12	20210	0	0	0
T18	0	909	0	0
T30	65972	0	0	0
T32	1691	0	0	0
T39	8444	0	0	0
T58	0	5469	0	0
T61	2583	0	0	0
T62	1329	0	0	0
T94	1206	0	0	0
T95	2280	0	0	0
T99	2586	0	0	0
T126	0	1882	0	0
T135	0	518	0	0
T136	0	4138	0	0
T137	0	1564	0	0
T138	0	2127	0	0
T139	0	3265	0	0
T140	0	2129	0	0