Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48770	0	0
CgEnOn_A	2147483647	39773	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48770	0	0
T1	2509427	671	0	0
T3	0	35	0	0
T4	59532	18	0	0
T6	127096	3	0	0
T7	15817	3	0	0
T8	3698	3	0	0
T9	8045	3	0	0
T13	3307332	5	0	0
T19	4987	3	0	0
T20	23645	3	0	0
T21	12610	3	0	0
T22	98999	0	0	0
T26	6146	8	0	0
T29	0	5	0	0
T35	4645	10	0	0
T36	0	15	0	0
T37	0	15	0	0
T46	54417	0	0	0
T47	8172	0	0	0
T77	5319	0	0	0
T123	20177	0	0	0
T141	0	20	0	0
T142	0	20	0	0
T143	0	25	0	0
T144	0	20	0	0
T145	0	10	0	0
T148	3340	0	0	0
T149	19886	0	0	0
T150	5687	0	0	0
T151	4875	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39773	0	0
T1	2509427	638	0	0
T2	322948	0	0	0
T3	0	301	0	0
T5	305721	0	0	0
T13	3307332	5	0	0
T19	4987	0	0	0
T20	23645	0	0	0
T21	12610	0	0	0
T22	265252	8	0	0
T23	28771	0	0	0
T24	10849	6	0	0
T25	8711	27	0	0
T26	2304	5	0	0
T29	0	4	0	0
T35	4645	16	0	0
T36	0	15	0	0
T37	0	15	0	0
T39	0	26	0	0
T41	0	4	0	0
T46	54417	0	0	0
T47	8172	0	0	0
T77	5319	0	0	0
T96	0	4	0	0
T123	20177	0	0	0
T141	0	20	0	0
T142	0	20	0	0
T143	0	25	0	0
T144	0	20	0	0
T145	0	10	0	0
T146	0	1	0	0
T148	3340	0	0	0
T149	19886	0	0	0
T150	5687	0	0	0
T151	4875	0	0	0
T153	0	36	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	222009492	134	0	0
CgEnOn_A	222009492	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222009492	134	0	0
T13	183698	1	0	0
T29	0	1	0	0
T35	1021	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	12824	0	0	0
T47	1805	0	0	0
T77	1248	0	0	0
T123	4454	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	753	0	0	0
T149	4389	0	0	0
T150	1246	0	0	0
T151	1072	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222009492	134	0	0
T13	183698	1	0	0
T29	0	1	0	0
T35	1021	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	12824	0	0	0
T47	1805	0	0	0
T77	1248	0	0	0
T123	4454	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	753	0	0	0
T149	4389	0	0	0
T150	1246	0	0	0
T151	1072	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111004119	134	0	0
CgEnOn_A	111004119	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004119	134	0	0
T13	918487	1	0	0
T29	0	1	0	0
T35	510	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	6411	0	0	0
T47	902	0	0	0
T77	623	0	0	0
T123	2227	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	375	0	0	0
T149	2195	0	0	0
T150	623	0	0	0
T151	536	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004119	134	0	0
T13	918487	1	0	0
T29	0	1	0	0
T35	510	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	6411	0	0	0
T47	902	0	0	0
T77	623	0	0	0
T123	2227	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	375	0	0	0
T149	2195	0	0	0
T150	623	0	0	0
T151	536	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445693197	134	0	0
CgEnOn_A	445693197	130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445693197	134	0	0
T13	368173	1	0	0
T29	0	1	0	0
T35	2094	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	22360	0	0	0
T47	3661	0	0	0
T77	2202	0	0	0
T123	9042	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	1462	0	0	0
T149	8912	0	0	0
T150	2572	0	0	0
T151	2195	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445693197	130	0	0
T13	368173	1	0	0
T35	2094	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	22360	0	0	0
T47	3661	0	0	0
T77	2202	0	0	0
T123	9042	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	1	0	0
T148	1462	0	0	0
T149	8912	0	0	0
T150	2572	0	0	0
T151	2195	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	475396197	134	0	0
CgEnOn_A	475396197	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	134	0	0
T13	399779	0	0	0
T28	0	1	0	0
T35	2210	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	23292	0	0	0
T47	3814	0	0	0
T77	2294	0	0	0
T123	9419	0	0	0
T141	0	3	0	0
T142	0	4	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	4	0	0
T148	1522	0	0	0
T149	9284	0	0	0
T150	2679	0	0	0
T151	2286	0	0	0
T152	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	132	0	0
T13	399779	0	0	0
T35	2210	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	23292	0	0	0
T47	3814	0	0	0
T77	2294	0	0	0
T123	9419	0	0	0
T141	0	3	0	0
T142	0	4	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	4	0	0
T146	0	2	0	0
T148	1522	0	0	0
T149	9284	0	0	0
T150	2679	0	0	0
T151	2286	0	0	0
T152	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111004119	134	0	0
CgEnOn_A	111004119	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004119	134	0	0
T13	918487	1	0	0
T29	0	1	0	0
T35	510	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	6411	0	0	0
T47	902	0	0	0
T77	623	0	0	0
T123	2227	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	375	0	0	0
T149	2195	0	0	0
T150	623	0	0	0
T151	536	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004119	134	0	0
T13	918487	1	0	0
T29	0	1	0	0
T35	510	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	6411	0	0	0
T47	902	0	0	0
T77	623	0	0	0
T123	2227	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	375	0	0	0
T149	2195	0	0	0
T150	623	0	0	0
T151	536	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	475396197	134	0	0
CgEnOn_A	475396197	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	134	0	0
T13	399779	0	0	0
T28	0	1	0	0
T35	2210	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	23292	0	0	0
T47	3814	0	0	0
T77	2294	0	0	0
T123	9419	0	0	0
T141	0	3	0	0
T142	0	4	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	4	0	0
T148	1522	0	0	0
T149	9284	0	0	0
T150	2679	0	0	0
T151	2286	0	0	0
T152	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	132	0	0
T13	399779	0	0	0
T35	2210	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	23292	0	0	0
T47	3814	0	0	0
T77	2294	0	0	0
T123	9419	0	0	0
T141	0	3	0	0
T142	0	4	0	0
T143	0	3	0	0
T144	0	2	0	0
T145	0	4	0	0
T146	0	2	0	0
T148	1522	0	0	0
T149	9284	0	0	0
T150	2679	0	0	0
T151	2286	0	0	0
T152	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111004119	134	0	0
CgEnOn_A	111004119	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004119	134	0	0
T13	918487	1	0	0
T29	0	1	0	0
T35	510	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	6411	0	0	0
T47	902	0	0	0
T77	623	0	0	0
T123	2227	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	375	0	0	0
T149	2195	0	0	0
T150	623	0	0	0
T151	536	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004119	134	0	0
T13	918487	1	0	0
T29	0	1	0	0
T35	510	2	0	0
T36	0	3	0	0
T37	0	3	0	0
T46	6411	0	0	0
T47	902	0	0	0
T77	623	0	0	0
T123	2227	0	0	0
T141	0	4	0	0
T142	0	4	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T148	375	0	0	0
T149	2195	0	0	0
T150	623	0	0	0
T151	536	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	222009492	7907	0	0
CgEnOn_A	222009492	5664	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222009492	7907	0	0
T1	445547	201	0	0
T4	14108	6	0	0
T6	36306	1	0	0
T7	4954	1	0	0
T8	1089	1	0	0
T9	2315	1	0	0
T19	869	1	0	0
T20	4661	1	0	0
T21	2428	1	0	0
T26	1087	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222009492	5664	0	0
T1	445547	190	0	0
T2	92252	0	0	0
T3	0	86	0	0
T5	35951	0	0	0
T19	869	0	0	0
T20	4661	0	0	0
T21	2428	0	0	0
T22	47479	3	0	0
T23	5943	0	0	0
T24	1899	2	0	0
T25	1521	8	0	0
T35	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T96	0	1	0	0
T153	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	111004119	7833	0	0
CgEnOn_A	111004119	5590	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004119	7833	0	0
T1	222772	200	0	0
T4	7053	6	0	0
T6	18153	1	0	0
T7	2475	1	0	0
T8	543	1	0	0
T9	1157	1	0	0
T19	435	1	0	0
T20	2328	1	0	0
T21	1212	1	0	0
T26	543	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111004119	5590	0	0
T1	222772	189	0	0
T2	46126	0	0	0
T3	0	88	0	0
T5	17974	0	0	0
T19	435	0	0	0
T20	2328	0	0	0
T21	1212	0	0	0
T22	23739	3	0	0
T23	2969	0	0	0
T24	950	2	0	0
T25	761	9	0	0
T35	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T96	0	1	0	0
T153	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	445693197	7910	0	0
CgEnOn_A	445693197	5663	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445693197	7910	0	0
T1	892055	204	0	0
T4	38371	6	0	0
T6	72637	1	0	0
T7	8388	1	0	0
T8	2066	1	0	0
T9	4573	1	0	0
T19	1804	1	0	0
T20	8158	1	0	0
T21	4393	1	0	0
T26	2212	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	445693197	5663	0	0
T1	892055	193	0	0
T2	184570	0	0	0
T3	0	92	0	0
T5	123327	0	0	0
T19	1804	0	0	0
T20	8158	0	0	0
T21	4393	0	0	0
T22	95035	2	0	0
T23	9727	0	0	0
T24	3919	2	0	0
T25	3149	10	0	0
T35	0	2	0	0
T39	0	2	0	0
T41	0	1	0	0
T96	0	1	0	0
T153	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	228218127	7862	0	0
CgEnOn_A	228218127	5614	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228218127	7862	0	0
T1	456129	196	0	0
T4	19186	6	0	0
T6	42081	1	0	0
T7	4194	1	0	0
T8	1033	1	0	0
T9	2286	1	0	0
T19	902	1	0	0
T20	4079	1	0	0
T21	2197	1	0	0
T26	1105	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228218127	5614	0	0
T1	456129	185	0	0
T2	92289	0	0	0
T3	0	89	0	0
T5	61666	0	0	0
T19	902	0	0	0
T20	4079	0	0	0
T21	2197	0	0	0
T22	47520	3	0	0
T23	4863	0	0	0
T24	1959	2	0	0
T25	1574	8	0	0
T35	0	4	0	0
T39	0	1	0	0
T41	0	1	0	0
T96	0	1	0	0
T153	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T26,T1,T3
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	475396197	4070	0	0
CgEnOn_A	475396197	4068	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	4070	0	0
T1	949053	66	0	0
T3	0	35	0	0
T5	128469	0	0	0
T19	1879	0	0	0
T20	8498	0	0	0
T21	4577	0	0	0
T22	98999	0	0	0
T23	10132	0	0	0
T24	4081	0	0	0
T25	3280	0	0	0
T26	2304	5	0	0
T39	0	21	0	0
T41	0	1	0	0
T44	0	4	0	0
T61	0	7	0	0
T95	0	9	0	0
T96	0	1	0	0
T97	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	4068	0	0
T1	949053	66	0	0
T3	0	35	0	0
T5	128469	0	0	0
T19	1879	0	0	0
T20	8498	0	0	0
T21	4577	0	0	0
T22	98999	0	0	0
T23	10132	0	0	0
T24	4081	0	0	0
T25	3280	0	0	0
T26	2304	5	0	0
T39	0	21	0	0
T41	0	1	0	0
T44	0	4	0	0
T61	0	7	0	0
T95	0	9	0	0
T96	0	1	0	0
T97	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T26,T1,T3
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	475396197	4050	0	0
CgEnOn_A	475396197	4048	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	4050	0	0
T1	949053	73	0	0
T3	0	36	0	0
T5	128469	0	0	0
T19	1879	0	0	0
T20	8498	0	0	0
T21	4577	0	0	0
T22	98999	0	0	0
T23	10132	0	0	0
T24	4081	0	0	0
T25	3280	0	0	0
T26	2304	5	0	0
T39	0	16	0	0
T41	0	1	0	0
T44	0	9	0	0
T61	0	8	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	4048	0	0
T1	949053	73	0	0
T3	0	36	0	0
T5	128469	0	0	0
T19	1879	0	0	0
T20	8498	0	0	0
T21	4577	0	0	0
T22	98999	0	0	0
T23	10132	0	0	0
T24	4081	0	0	0
T25	3280	0	0	0
T26	2304	5	0	0
T39	0	16	0	0
T41	0	1	0	0
T44	0	9	0	0
T61	0	8	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T26,T1,T3
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	475396197	4027	0	0
CgEnOn_A	475396197	4025	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	4027	0	0
T1	949053	77	0	0
T3	0	32	0	0
T5	128469	0	0	0
T19	1879	0	0	0
T20	8498	0	0	0
T21	4577	0	0	0
T22	98999	0	0	0
T23	10132	0	0	0
T24	4081	0	0	0
T25	3280	0	0	0
T26	2304	4	0	0
T39	0	18	0	0
T41	0	1	0	0
T44	0	9	0	0
T61	0	7	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	4025	0	0
T1	949053	77	0	0
T3	0	32	0	0
T5	128469	0	0	0
T19	1879	0	0	0
T20	8498	0	0	0
T21	4577	0	0	0
T22	98999	0	0	0
T23	10132	0	0	0
T24	4081	0	0	0
T25	3280	0	0	0
T26	2304	4	0	0
T39	0	18	0	0
T41	0	1	0	0
T44	0	9	0	0
T61	0	7	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T22
1	0	Covered	T26,T1,T3
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	475396197	4173	0	0
CgEnOn_A	475396197	4171	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	4173	0	0
T1	949053	75	0	0
T3	0	31	0	0
T5	128469	0	0	0
T19	1879	0	0	0
T20	8498	0	0	0
T21	4577	0	0	0
T22	98999	0	0	0
T23	10132	0	0	0
T24	4081	0	0	0
T25	3280	0	0	0
T26	2304	5	0	0
T39	0	16	0	0
T41	0	1	0	0
T44	0	6	0	0
T61	0	8	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475396197	4171	0	0
T1	949053	75	0	0
T3	0	31	0	0
T5	128469	0	0	0
T19	1879	0	0	0
T20	8498	0	0	0
T21	4577	0	0	0
T22	98999	0	0	0
T23	10132	0	0	0
T24	4081	0	0	0
T25	3280	0	0	0
T26	2304	5	0	0
T39	0	16	0	0
T41	0	1	0	0
T44	0	6	0	0
T61	0	8	0	0
T95	0	6	0	0
T96	0	1	0	0
T97	0	3	0	0