Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.79	100.00	100.00	98.81	97.01	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1003	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2312357884			Apr 28 12:51:52 PM PDT 24	Apr 28 12:51:56 PM PDT 24	41604845 ps
T93	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3558205292			Apr 28 12:51:42 PM PDT 24	Apr 28 12:51:47 PM PDT 24	579457639 ps
T1004	/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.370307197			Apr 28 12:51:30 PM PDT 24	Apr 28 12:51:34 PM PDT 24	189793417 ps
T1005	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.104251791			Apr 28 12:51:18 PM PDT 24	Apr 28 12:51:20 PM PDT 24	220333861 ps
T117	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3991696622			Apr 28 12:51:16 PM PDT 24	Apr 28 12:51:19 PM PDT 24	131377753 ps
T1006	/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3422819478			Apr 28 12:51:48 PM PDT 24	Apr 28 12:51:51 PM PDT 24	102485274 ps
T1007	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1209419948			Apr 28 12:51:15 PM PDT 24	Apr 28 12:51:18 PM PDT 24	84913015 ps
T1008	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2914025066			Apr 28 12:51:27 PM PDT 24	Apr 28 12:51:30 PM PDT 24	184479621 ps
T1009	/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3438046755			Apr 28 12:51:22 PM PDT 24	Apr 28 12:51:24 PM PDT 24	102831643 ps
T1010	/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.55818082			Apr 28 12:51:51 PM PDT 24	Apr 28 12:51:52 PM PDT 24	23691822 ps

Test location	/workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.3955024888
Short name	T1
Test name
Test status
Simulation time	95805418538 ps
CPU time	1023.82 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 01:13:53 PM PDT 24
Peak memory	209664 kb
Host	smart-ca5c8b1a-696e-4159-bcef-6fd31c49ea74
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3955024888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.3955024888
Directory	/workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.clkmgr_regwen.45766279
Short name	T5
Test name
Test status
Simulation time	1284716637 ps
CPU time	4.78 seconds
Started	Apr 28 12:56:32 PM PDT 24
Finished	Apr 28 12:56:37 PM PDT 24
Peak memory	201152 kb
Host	smart-80f31cd8-ff30-4253-8e1d-e5dc4e1beca3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45766279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.45766279
Directory	/workspace/17.clkmgr_regwen/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2495238119
Short name	T55
Test name
Test status
Simulation time	292612483 ps
CPU time	2.26 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	209256 kb
Host	smart-f95c3693-231c-43a3-bf27-a8174fa9121f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495238119 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.clkmgr_shadow_reg_errors.2495238119
Directory	/workspace/17.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/2.clkmgr_sec_cm.3006973215
Short name	T38
Test name
Test status
Simulation time	154725441 ps
CPU time	1.96 seconds
Started	Apr 28 12:55:57 PM PDT 24
Finished	Apr 28 12:56:00 PM PDT 24
Peak memory	220184 kb
Host	smart-594f29f8-b85f-409f-8e95-521a3e3a0ca2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006973215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg r_sec_cm.3006973215
Directory	/workspace/2.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_status.696289512
Short name	T36
Test name
Test status
Simulation time	14896083 ps
CPU time	0.71 seconds
Started	Apr 28 12:56:32 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	200872 kb
Host	smart-814455c7-5c3b-46ce-9fcf-12b636535309
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696289512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.696289512
Directory	/workspace/15.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/49.clkmgr_idle_intersig_mubi.3417180899
Short name	T26
Test name
Test status
Simulation time	23068298 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	201028 kb
Host	smart-4d8398b4-57a9-4eb4-81a8-0a77b72e02e5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417180899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.3417180899
Directory	/workspace/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all.2968182654
Short name	T39
Test name
Test status
Simulation time	88899969 ps
CPU time	1.64 seconds
Started	Apr 28 12:56:18 PM PDT 24
Finished	Apr 28 12:56:20 PM PDT 24
Peak memory	201232 kb
Host	smart-945bf698-5046-4f08-8ee5-96ade20ce6ad
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968182654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.2968182654
Directory	/workspace/13.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1632239668
Short name	T85
Test name
Test status
Simulation time	97624717 ps
CPU time	2.33 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	200628 kb
Host	smart-8d20beb2-b3c6-4c16-aa73-5524fc9988ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632239668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 19.clkmgr_tl_intg_err.1632239668
Directory	/workspace/19.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all.1393587771
Short name	T15
Test name
Test status
Simulation time	2447995365 ps
CPU time	17.63 seconds
Started	Apr 28 12:57:48 PM PDT 24
Finished	Apr 28 12:58:06 PM PDT 24
Peak memory	201400 kb
Host	smart-88cea69e-6548-40eb-8ce4-e1973e5e276c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393587771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.1393587771
Directory	/workspace/48.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.7684127
Short name	T51
Test name
Test status
Simulation time	1457132163 ps
CPU time	5.82 seconds
Started	Apr 28 12:51:34 PM PDT 24
Finished	Apr 28 12:51:40 PM PDT 24
Peak memory	209340 kb
Host	smart-036b0031-9f58-4db6-93cc-fdcf92e6c299
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7684127 -assert nopostproc +UVM_TESTNAME=c lkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.7684127
Directory	/workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1477474068
Short name	T18
Test name
Test status
Simulation time	33410806051 ps
CPU time	191.64 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:59:52 PM PDT 24
Peak memory	216340 kb
Host	smart-209fa205-6293-4bfb-bbfa-0ebb97e15e54
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1477474068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1477474068
Directory	/workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.clkmgr_alert_test.432577898
Short name	T166
Test name
Test status
Simulation time	36732770 ps
CPU time	0.84 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	200892 kb
Host	smart-1d30db1b-e9eb-4744-86ac-6b897655e20e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432577898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg r_alert_test.432577898
Directory	/workspace/0.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.1036418528
Short name	T28
Test name
Test status
Simulation time	100337438531 ps
CPU time	690.4 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 01:08:27 PM PDT 24
Peak memory	213848 kb
Host	smart-5301cf7b-cb54-43bc-a7b3-96beea2e193c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1036418528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.1036418528
Directory	/workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3076646252
Short name	T7
Test name
Test status
Simulation time	87406906 ps
CPU time	1.11 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	200948 kb
Host	smart-8e4e6cad-0e04-4bbd-8987-665fac56ca21
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076646252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.3076646252
Directory	/workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_regwen.3607808938
Short name	T11
Test name
Test status
Simulation time	950192118 ps
CPU time	5.5 seconds
Started	Apr 28 12:56:22 PM PDT 24
Finished	Apr 28 12:56:28 PM PDT 24
Peak memory	200984 kb
Host	smart-9d34a6eb-cc38-459f-b308-34a6fb56aadc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607808938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3607808938
Directory	/workspace/12.clkmgr_regwen/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.507094654
Short name	T107
Test name
Test status
Simulation time	607530825 ps
CPU time	3.26 seconds
Started	Apr 28 12:51:35 PM PDT 24
Finished	Apr 28 12:51:38 PM PDT 24
Peak memory	209200 kb
Host	smart-f2cb3f6c-a7d0-411c-8f59-3775a3d9f276
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507094654 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 8.clkmgr_shadow_reg_errors.507094654
Directory	/workspace/8.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1381759427
Short name	T979
Test name
Test status
Simulation time	233390757 ps
CPU time	2.1 seconds
Started	Apr 28 12:51:41 PM PDT 24
Finished	Apr 28 12:51:44 PM PDT 24
Peak memory	200732 kb
Host	smart-1bc93697-6d8c-4573-8254-812fadd3f88d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381759427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 13.clkmgr_tl_intg_err.1381759427
Directory	/workspace/13.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.clkmgr_idle_intersig_mubi.1055513624
Short name	T206
Test name
Test status
Simulation time	18881363 ps
CPU time	0.81 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	200868 kb
Host	smart-58ef1e18-5118-4493-8645-8c99924078da
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055513624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.1055513624
Directory	/workspace/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_regwen.3994152421
Short name	T350
Test name
Test status
Simulation time	396781062 ps
CPU time	2.67 seconds
Started	Apr 28 12:55:55 PM PDT 24
Finished	Apr 28 12:55:59 PM PDT 24
Peak memory	200952 kb
Host	smart-4426bb05-f689-4602-9d21-585f0f75f2c9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994152421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3994152421
Directory	/workspace/0.clkmgr_regwen/latest

Test location	/workspace/coverage/default/12.clkmgr_extclk.3638695559
Short name	T192
Test name
Test status
Simulation time	44948222 ps
CPU time	0.88 seconds
Started	Apr 28 12:56:15 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	201012 kb
Host	smart-ee5ab307-b964-4d00-b80a-2e20ca960ce5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638695559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.3638695559
Directory	/workspace/12.clkmgr_extclk/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3253717765
Short name	T100
Test name
Test status
Simulation time	252494073 ps
CPU time	1.92 seconds
Started	Apr 28 12:51:16 PM PDT 24
Finished	Apr 28 12:51:19 PM PDT 24
Peak memory	201052 kb
Host	smart-7947024f-46e4-42bf-8235-f452608a35bb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253717765 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.clkmgr_shadow_reg_errors.3253717765
Directory	/workspace/1.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2117297865
Short name	T89
Test name
Test status
Simulation time	264876013 ps
CPU time	2.6 seconds
Started	Apr 28 12:51:29 PM PDT 24
Finished	Apr 28 12:51:32 PM PDT 24
Peak memory	200572 kb
Host	smart-a51116b5-0d8a-4171-a284-119898f496d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117297865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 5.clkmgr_tl_intg_err.2117297865
Directory	/workspace/5.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.990426670
Short name	T984
Test name
Test status
Simulation time	76552228 ps
CPU time	1.57 seconds
Started	Apr 28 12:51:18 PM PDT 24
Finished	Apr 28 12:51:21 PM PDT 24
Peak memory	200664 kb
Host	smart-406ccbe7-f314-4fc3-b755-676b1fd4eae0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990426670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.clkmgr_csr_aliasing.990426670
Directory	/workspace/0.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.4271049468
Short name	T895
Test name
Test status
Simulation time	738682180 ps
CPU time	8.37 seconds
Started	Apr 28 12:51:17 PM PDT 24
Finished	Apr 28 12:51:26 PM PDT 24
Peak memory	200548 kb
Host	smart-6c3b64fe-5782-4bab-aa6a-13b180425841
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271049468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_bit_bash.4271049468
Directory	/workspace/0.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2225688645
Short name	T914
Test name
Test status
Simulation time	15968434 ps
CPU time	0.77 seconds
Started	Apr 28 12:51:17 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	200324 kb
Host	smart-21b5b24a-5b71-435b-bb8c-44e8b62266c1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225688645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_hw_reset.2225688645
Directory	/workspace/0.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.213511378
Short name	T928
Test name
Test status
Simulation time	45462503 ps
CPU time	1.08 seconds
Started	Apr 28 12:51:19 PM PDT 24
Finished	Apr 28 12:51:20 PM PDT 24
Peak memory	200488 kb
Host	smart-69621efa-bed7-4c86-bd18-0bf75bf957d7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213511378 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.213511378
Directory	/workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1480835214
Short name	T859
Test name
Test status
Simulation time	18976173 ps
CPU time	0.85 seconds
Started	Apr 28 12:51:18 PM PDT 24
Finished	Apr 28 12:51:20 PM PDT 24
Peak memory	200456 kb
Host	smart-6d8ddfd5-d1d3-4184-8a9f-7385dee39f8d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480835214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. clkmgr_csr_rw.1480835214
Directory	/workspace/0.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3890837570
Short name	T891
Test name
Test status
Simulation time	27111315 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:17 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	198816 kb
Host	smart-d797abe2-ab75-43a0-b795-0c59ad36dec9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890837570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_intr_test.3890837570
Directory	/workspace/0.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3758170514
Short name	T990
Test name
Test status
Simulation time	28717623 ps
CPU time	0.97 seconds
Started	Apr 28 12:51:16 PM PDT 24
Finished	Apr 28 12:51:17 PM PDT 24
Peak memory	200464 kb
Host	smart-d0ffa6f0-495c-47b2-b893-7e683817094f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758170514 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.clkmgr_same_csr_outstanding.3758170514
Directory	/workspace/0.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3267705796
Short name	T122
Test name
Test status
Simulation time	306523314 ps
CPU time	2.49 seconds
Started	Apr 28 12:51:19 PM PDT 24
Finished	Apr 28 12:51:22 PM PDT 24
Peak memory	201000 kb
Host	smart-703ebbfa-4128-404a-9bf7-8212aaefcbf4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267705796 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.clkmgr_shadow_reg_errors.3267705796
Directory	/workspace/0.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3991696622
Short name	T117
Test name
Test status
Simulation time	131377753 ps
CPU time	2.34 seconds
Started	Apr 28 12:51:16 PM PDT 24
Finished	Apr 28 12:51:19 PM PDT 24
Peak memory	209288 kb
Host	smart-a9d2915b-b4ac-4636-a8f8-0e2cc78a7962
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991696622 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3991696622
Directory	/workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.105290050
Short name	T930
Test name
Test status
Simulation time	180146692 ps
CPU time	1.83 seconds
Started	Apr 28 12:51:20 PM PDT 24
Finished	Apr 28 12:51:22 PM PDT 24
Peak memory	200752 kb
Host	smart-0e1e0004-1fcd-4722-add4-05e5bc68d595
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105290050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm gr_tl_errors.105290050
Directory	/workspace/0.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1752475946
Short name	T877
Test name
Test status
Simulation time	328979893 ps
CPU time	3.09 seconds
Started	Apr 28 12:51:17 PM PDT 24
Finished	Apr 28 12:51:21 PM PDT 24
Peak memory	200520 kb
Host	smart-bf3ac95c-9fef-4446-868c-c42b993b793d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752475946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 0.clkmgr_tl_intg_err.1752475946
Directory	/workspace/0.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2250850101
Short name	T971
Test name
Test status
Simulation time	237386098 ps
CPU time	1.73 seconds
Started	Apr 28 12:51:15 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	200440 kb
Host	smart-06aaee04-cdd1-4b15-bde1-5bf1f0531347
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250850101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_aliasing.2250850101
Directory	/workspace/1.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3781339047
Short name	T87
Test name
Test status
Simulation time	264986761 ps
CPU time	7.3 seconds
Started	Apr 28 12:51:19 PM PDT 24
Finished	Apr 28 12:51:27 PM PDT 24
Peak memory	200632 kb
Host	smart-51388a43-79b8-4391-a4a9-d0808f2bd1e6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781339047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_bit_bash.3781339047
Directory	/workspace/1.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2898956361
Short name	T933
Test name
Test status
Simulation time	19121864 ps
CPU time	0.77 seconds
Started	Apr 28 12:51:17 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	200092 kb
Host	smart-582f0996-7348-466c-8e8e-98ef0e5161a6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898956361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_hw_reset.2898956361
Directory	/workspace/1.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.308501479
Short name	T898
Test name
Test status
Simulation time	25535437 ps
CPU time	1.39 seconds
Started	Apr 28 12:51:19 PM PDT 24
Finished	Apr 28 12:51:21 PM PDT 24
Peak memory	200680 kb
Host	smart-e8ae1f4b-5c91-481e-a0fa-9da60c73b53d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308501479 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.308501479
Directory	/workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.4093210542
Short name	T899
Test name
Test status
Simulation time	62693064 ps
CPU time	0.85 seconds
Started	Apr 28 12:51:18 PM PDT 24
Finished	Apr 28 12:51:19 PM PDT 24
Peak memory	200308 kb
Host	smart-948eb38d-81dc-4eda-b095-58c3a0a6423f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093210542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. clkmgr_csr_rw.4093210542
Directory	/workspace/1.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1012871548
Short name	T937
Test name
Test status
Simulation time	25431968 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:16 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	198832 kb
Host	smart-2edfa8f8-aba2-4abf-87f9-3a9b55bb4366
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012871548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_intr_test.1012871548
Directory	/workspace/1.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2178959106
Short name	T995
Test name
Test status
Simulation time	38901917 ps
CPU time	1.22 seconds
Started	Apr 28 12:51:19 PM PDT 24
Finished	Apr 28 12:51:21 PM PDT 24
Peak memory	200404 kb
Host	smart-fa6cdbc4-c71d-4fda-bdb9-9df5360bba03
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178959106 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.clkmgr_same_csr_outstanding.2178959106
Directory	/workspace/1.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.104251791
Short name	T1005
Test name
Test status
Simulation time	220333861 ps
CPU time	2.08 seconds
Started	Apr 28 12:51:18 PM PDT 24
Finished	Apr 28 12:51:20 PM PDT 24
Peak memory	209360 kb
Host	smart-04a1011e-a74f-470f-a6d4-906cb5aaaf5b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104251791 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.104251791
Directory	/workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1209419948
Short name	T1007
Test name
Test status
Simulation time	84913015 ps
CPU time	2.02 seconds
Started	Apr 28 12:51:15 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	200740 kb
Host	smart-4914541b-8b61-4fae-bc31-94f7363280ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209419948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_tl_errors.1209419948
Directory	/workspace/1.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.197129367
Short name	T91
Test name
Test status
Simulation time	72208020 ps
CPU time	1.69 seconds
Started	Apr 28 12:51:20 PM PDT 24
Finished	Apr 28 12:51:22 PM PDT 24
Peak memory	200708 kb
Host	smart-fb869aed-8c94-4a50-973d-4d2a4d1b6c4b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197129367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.clkmgr_tl_intg_err.197129367
Directory	/workspace/1.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.895802269
Short name	T866
Test name
Test status
Simulation time	204400854 ps
CPU time	1.92 seconds
Started	Apr 28 12:51:37 PM PDT 24
Finished	Apr 28 12:51:40 PM PDT 24
Peak memory	200760 kb
Host	smart-5c0bfac0-bcc9-4972-9262-c2e33f808581
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895802269 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.895802269
Directory	/workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.298346267
Short name	T70
Test name
Test status
Simulation time	16224551 ps
CPU time	0.74 seconds
Started	Apr 28 12:51:39 PM PDT 24
Finished	Apr 28 12:51:40 PM PDT 24
Peak memory	200364 kb
Host	smart-9f25646d-3d7e-4a89-a830-41e8f22d0b49
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298346267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. clkmgr_csr_rw.298346267
Directory	/workspace/10.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2376240226
Short name	T874
Test name
Test status
Simulation time	11614213 ps
CPU time	0.67 seconds
Started	Apr 28 12:51:38 PM PDT 24
Finished	Apr 28 12:51:39 PM PDT 24
Peak memory	198940 kb
Host	smart-eacea574-3ab3-41c0-92d5-4b2afeb42adf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376240226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_intr_test.2376240226
Directory	/workspace/10.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1074351909
Short name	T982
Test name
Test status
Simulation time	24261914 ps
CPU time	0.97 seconds
Started	Apr 28 12:51:37 PM PDT 24
Finished	Apr 28 12:51:38 PM PDT 24
Peak memory	200368 kb
Host	smart-40cf338e-bfc3-4bb8-98f7-dcb4a64d1ef1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074351909 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 10.clkmgr_same_csr_outstanding.1074351909
Directory	/workspace/10.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3475466506
Short name	T54
Test name
Test status
Simulation time	140557095 ps
CPU time	2.06 seconds
Started	Apr 28 12:51:32 PM PDT 24
Finished	Apr 28 12:51:35 PM PDT 24
Peak memory	201168 kb
Host	smart-d30d7151-c59c-4deb-85fa-9d720523c76a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475466506 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.clkmgr_shadow_reg_errors.3475466506
Directory	/workspace/10.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3672391379
Short name	T120
Test name
Test status
Simulation time	93768221 ps
CPU time	1.89 seconds
Started	Apr 28 12:51:31 PM PDT 24
Finished	Apr 28 12:51:33 PM PDT 24
Peak memory	217364 kb
Host	smart-6cae4ba8-d8df-40d5-b393-47ad86d5c570
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672391379 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3672391379
Directory	/workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2505742726
Short name	T908
Test name
Test status
Simulation time	302954494 ps
CPU time	2.72 seconds
Started	Apr 28 12:51:31 PM PDT 24
Finished	Apr 28 12:51:34 PM PDT 24
Peak memory	200652 kb
Host	smart-c1ddb4a8-7bb3-47c7-ad0f-3e0e25bf5e73
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505742726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_tl_errors.2505742726
Directory	/workspace/10.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3355428063
Short name	T939
Test name
Test status
Simulation time	574463945 ps
CPU time	3.76 seconds
Started	Apr 28 12:51:35 PM PDT 24
Finished	Apr 28 12:51:39 PM PDT 24
Peak memory	200636 kb
Host	smart-11f3fe10-c75a-4ddc-a1ad-7061eab977ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355428063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.clkmgr_tl_intg_err.3355428063
Directory	/workspace/10.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2550934973
Short name	T858
Test name
Test status
Simulation time	32817697 ps
CPU time	1.58 seconds
Started	Apr 28 12:51:37 PM PDT 24
Finished	Apr 28 12:51:39 PM PDT 24
Peak memory	200764 kb
Host	smart-558af88f-924b-479d-a041-244864b64cbe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550934973 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.2550934973
Directory	/workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3362515685
Short name	T985
Test name
Test status
Simulation time	29939337 ps
CPU time	0.75 seconds
Started	Apr 28 12:51:37 PM PDT 24
Finished	Apr 28 12:51:39 PM PDT 24
Peak memory	200444 kb
Host	smart-8ace6425-b80d-4c4f-969e-a05a3ce36c1f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362515685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .clkmgr_csr_rw.3362515685
Directory	/workspace/11.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2004946359
Short name	T950
Test name
Test status
Simulation time	26928078 ps
CPU time	0.71 seconds
Started	Apr 28 12:51:41 PM PDT 24
Finished	Apr 28 12:51:42 PM PDT 24
Peak memory	198960 kb
Host	smart-00c15847-b4c9-4be5-9375-a39dda27f76f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004946359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_intr_test.2004946359
Directory	/workspace/11.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3948876905
Short name	T69
Test name
Test status
Simulation time	127263369 ps
CPU time	1.39 seconds
Started	Apr 28 12:51:38 PM PDT 24
Finished	Apr 28 12:51:40 PM PDT 24
Peak memory	200400 kb
Host	smart-e8c84418-c61d-463c-834a-5338556d5f39
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948876905 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.clkmgr_same_csr_outstanding.3948876905
Directory	/workspace/11.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.3279214157
Short name	T103
Test name
Test status
Simulation time	159305441 ps
CPU time	1.56 seconds
Started	Apr 28 12:51:38 PM PDT 24
Finished	Apr 28 12:51:41 PM PDT 24
Peak memory	200828 kb
Host	smart-b9c91173-b795-4905-8173-ab5154849568
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279214157 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.clkmgr_shadow_reg_errors.3279214157
Directory	/workspace/11.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.4190253789
Short name	T104
Test name
Test status
Simulation time	397133080 ps
CPU time	3.44 seconds
Started	Apr 28 12:51:37 PM PDT 24
Finished	Apr 28 12:51:42 PM PDT 24
Peak memory	209236 kb
Host	smart-b6d5f973-07ec-4a0e-b47f-c6a50f3b10f9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190253789 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.4190253789
Directory	/workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1171587156
Short name	T931
Test name
Test status
Simulation time	150816487 ps
CPU time	2.54 seconds
Started	Apr 28 12:51:36 PM PDT 24
Finished	Apr 28 12:51:40 PM PDT 24
Peak memory	200684 kb
Host	smart-22a693d0-7af9-45c4-83a7-77043cc19745
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171587156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_tl_errors.1171587156
Directory	/workspace/11.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3055438628
Short name	T86
Test name
Test status
Simulation time	79885725 ps
CPU time	1.73 seconds
Started	Apr 28 12:51:38 PM PDT 24
Finished	Apr 28 12:51:40 PM PDT 24
Peak memory	200616 kb
Host	smart-4dd95276-5562-4327-8906-4d3424303dce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055438628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 11.clkmgr_tl_intg_err.3055438628
Directory	/workspace/11.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2771851490
Short name	T905
Test name
Test status
Simulation time	75005945 ps
CPU time	1.45 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:46 PM PDT 24
Peak memory	200396 kb
Host	smart-d9640abe-b6f3-4808-a0c0-14f449d2a338
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771851490 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.2771851490
Directory	/workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.752677217
Short name	T934
Test name
Test status
Simulation time	20678691 ps
CPU time	0.85 seconds
Started	Apr 28 12:51:46 PM PDT 24
Finished	Apr 28 12:51:47 PM PDT 24
Peak memory	200416 kb
Host	smart-bf4d32a7-fb78-47ee-94a6-b4753f756054
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752677217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. clkmgr_csr_rw.752677217
Directory	/workspace/12.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3480817897
Short name	T945
Test name
Test status
Simulation time	12818579 ps
CPU time	0.7 seconds
Started	Apr 28 12:51:42 PM PDT 24
Finished	Apr 28 12:51:44 PM PDT 24
Peak memory	198856 kb
Host	smart-5a60b538-ed99-47e2-bb5c-536c8f93b2db
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480817897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_intr_test.3480817897
Directory	/workspace/12.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2433747221
Short name	T999
Test name
Test status
Simulation time	97646599 ps
CPU time	1.12 seconds
Started	Apr 28 12:51:45 PM PDT 24
Finished	Apr 28 12:51:47 PM PDT 24
Peak memory	200328 kb
Host	smart-ed5aa9c8-df96-4222-b7d3-d2aeb98a7b52
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433747221 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.clkmgr_same_csr_outstanding.2433747221
Directory	/workspace/12.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1314462641
Short name	T114
Test name
Test status
Simulation time	57462890 ps
CPU time	1.33 seconds
Started	Apr 28 12:51:38 PM PDT 24
Finished	Apr 28 12:51:40 PM PDT 24
Peak memory	200920 kb
Host	smart-1a4cc3f2-9592-4156-b92c-9e20e42a3985
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314462641 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 12.clkmgr_shadow_reg_errors.1314462641
Directory	/workspace/12.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1509737086
Short name	T110
Test name
Test status
Simulation time	103292056 ps
CPU time	2.49 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:46 PM PDT 24
Peak memory	217368 kb
Host	smart-1b22f63e-428f-4d03-81fa-55ec4b61d14f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509737086 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1509737086
Directory	/workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1360424106
Short name	T867
Test name
Test status
Simulation time	42719800 ps
CPU time	2.45 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:47 PM PDT 24
Peak memory	200672 kb
Host	smart-ea10df33-fd46-4578-9fc9-68ed52683ce0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360424106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_tl_errors.1360424106
Directory	/workspace/12.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2785743579
Short name	T88
Test name
Test status
Simulation time	214488216 ps
CPU time	1.86 seconds
Started	Apr 28 12:51:41 PM PDT 24
Finished	Apr 28 12:51:44 PM PDT 24
Peak memory	200624 kb
Host	smart-363c3391-421f-4778-9a5b-db73baf85384
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785743579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.clkmgr_tl_intg_err.2785743579
Directory	/workspace/12.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2957687535
Short name	T884
Test name
Test status
Simulation time	38425544 ps
CPU time	1.79 seconds
Started	Apr 28 12:51:42 PM PDT 24
Finished	Apr 28 12:51:45 PM PDT 24
Peak memory	208936 kb
Host	smart-fe26e457-a9cc-4423-bb02-60b3bc30e0e2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957687535 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.2957687535
Directory	/workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.933413631
Short name	T901
Test name
Test status
Simulation time	13823462 ps
CPU time	0.73 seconds
Started	Apr 28 12:51:41 PM PDT 24
Finished	Apr 28 12:51:42 PM PDT 24
Peak memory	200392 kb
Host	smart-186de103-0081-4d7b-88f0-30416faa71f7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933413631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. clkmgr_csr_rw.933413631
Directory	/workspace/13.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.4271994553
Short name	T936
Test name
Test status
Simulation time	16428000 ps
CPU time	0.71 seconds
Started	Apr 28 12:51:46 PM PDT 24
Finished	Apr 28 12:51:47 PM PDT 24
Peak memory	198960 kb
Host	smart-7fe35197-a008-4f35-95f8-a5b24fd63260
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271994553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_intr_test.4271994553
Directory	/workspace/13.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2804369327
Short name	T996
Test name
Test status
Simulation time	88684713 ps
CPU time	1.39 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:45 PM PDT 24
Peak memory	200660 kb
Host	smart-9435d315-6076-40fe-8904-332d35dfa261
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804369327 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.clkmgr_same_csr_outstanding.2804369327
Directory	/workspace/13.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2047231377
Short name	T116
Test name
Test status
Simulation time	272302285 ps
CPU time	2.12 seconds
Started	Apr 28 12:51:42 PM PDT 24
Finished	Apr 28 12:51:45 PM PDT 24
Peak memory	201164 kb
Host	smart-0d27d9a7-719f-4ca9-8f1f-eef631cdfaa7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047231377 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.clkmgr_shadow_reg_errors.2047231377
Directory	/workspace/13.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.594326516
Short name	T113
Test name
Test status
Simulation time	376630540 ps
CPU time	3.03 seconds
Started	Apr 28 12:51:44 PM PDT 24
Finished	Apr 28 12:51:48 PM PDT 24
Peak memory	217468 kb
Host	smart-8d6a1378-ff51-4eff-b8ed-726cdbf71980
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594326516 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.594326516
Directory	/workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.1309786826
Short name	T865
Test name
Test status
Simulation time	112013574 ps
CPU time	3.24 seconds
Started	Apr 28 12:51:41 PM PDT 24
Finished	Apr 28 12:51:44 PM PDT 24
Peak memory	200756 kb
Host	smart-6a285446-d972-4149-9b8c-e2b6b813433b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309786826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_tl_errors.1309786826
Directory	/workspace/13.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2943132672
Short name	T965
Test name
Test status
Simulation time	23619093 ps
CPU time	0.94 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:45 PM PDT 24
Peak memory	200404 kb
Host	smart-78ab2300-f825-48d5-b17c-3fa7c9633f84
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943132672 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.2943132672
Directory	/workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2297924993
Short name	T897
Test name
Test status
Simulation time	39598398 ps
CPU time	0.82 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:45 PM PDT 24
Peak memory	200320 kb
Host	smart-f105f180-b05f-42cf-b890-5ae3a22fe681
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297924993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .clkmgr_csr_rw.2297924993
Directory	/workspace/14.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.762729617
Short name	T957
Test name
Test status
Simulation time	13959841 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:45 PM PDT 24
Peak memory	198924 kb
Host	smart-2a2a3925-47b6-46bd-9d43-cb0d7a1ed23c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762729617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk mgr_intr_test.762729617
Directory	/workspace/14.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.771390056
Short name	T963
Test name
Test status
Simulation time	34251982 ps
CPU time	1.02 seconds
Started	Apr 28 12:51:40 PM PDT 24
Finished	Apr 28 12:51:42 PM PDT 24
Peak memory	200332 kb
Host	smart-5a06010d-a085-4a59-a64c-598b0b3fd2b2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771390056 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 14.clkmgr_same_csr_outstanding.771390056
Directory	/workspace/14.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.645006155
Short name	T967
Test name
Test status
Simulation time	58541575 ps
CPU time	1.25 seconds
Started	Apr 28 12:51:44 PM PDT 24
Finished	Apr 28 12:51:46 PM PDT 24
Peak memory	200824 kb
Host	smart-6562134e-329b-47f5-bad5-dd1a96beaf06
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645006155 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 14.clkmgr_shadow_reg_errors.645006155
Directory	/workspace/14.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.253659110
Short name	T106
Test name
Test status
Simulation time	151195707 ps
CPU time	2.7 seconds
Started	Apr 28 12:51:40 PM PDT 24
Finished	Apr 28 12:51:43 PM PDT 24
Peak memory	209316 kb
Host	smart-831eef4c-0841-45e9-8663-6de100544f18
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253659110 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.253659110
Directory	/workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2970413942
Short name	T940
Test name
Test status
Simulation time	27231341 ps
CPU time	1.67 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:46 PM PDT 24
Peak memory	200764 kb
Host	smart-11dc37c9-67e4-43eb-8fdd-70e646065573
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970413942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_tl_errors.2970413942
Directory	/workspace/14.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3558205292
Short name	T93
Test name
Test status
Simulation time	579457639 ps
CPU time	3.68 seconds
Started	Apr 28 12:51:42 PM PDT 24
Finished	Apr 28 12:51:47 PM PDT 24
Peak memory	200720 kb
Host	smart-29010de1-a69d-4cd8-8028-f2a6116754eb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558205292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.clkmgr_tl_intg_err.3558205292
Directory	/workspace/14.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.227530435
Short name	T862
Test name
Test status
Simulation time	51514518 ps
CPU time	1.26 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:50 PM PDT 24
Peak memory	200516 kb
Host	smart-10e3f1c4-b6ab-459a-ac40-f438695fe5e7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227530435 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.227530435
Directory	/workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.704249950
Short name	T961
Test name
Test status
Simulation time	13852149 ps
CPU time	0.74 seconds
Started	Apr 28 12:51:44 PM PDT 24
Finished	Apr 28 12:51:45 PM PDT 24
Peak memory	200408 kb
Host	smart-1d636d70-076c-45b7-9996-f9864fe98aa4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704249950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. clkmgr_csr_rw.704249950
Directory	/workspace/15.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3979520340
Short name	T970
Test name
Test status
Simulation time	29005103 ps
CPU time	0.72 seconds
Started	Apr 28 12:51:46 PM PDT 24
Finished	Apr 28 12:51:47 PM PDT 24
Peak memory	198928 kb
Host	smart-4498be60-2b44-449e-ad35-52f1e9d63371
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979520340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_intr_test.3979520340
Directory	/workspace/15.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.514904977
Short name	T941
Test name
Test status
Simulation time	59751431 ps
CPU time	1.33 seconds
Started	Apr 28 12:51:40 PM PDT 24
Finished	Apr 28 12:51:42 PM PDT 24
Peak memory	200600 kb
Host	smart-89fa599a-8493-462e-a175-1b1172ebf5fe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514904977 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 15.clkmgr_same_csr_outstanding.514904977
Directory	/workspace/15.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3569380619
Short name	T56
Test name
Test status
Simulation time	62199748 ps
CPU time	1.34 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:46 PM PDT 24
Peak memory	200848 kb
Host	smart-c20d7abd-7c8c-42c3-8ffd-80f8fea82d03
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569380619 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.clkmgr_shadow_reg_errors.3569380619
Directory	/workspace/15.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.814648969
Short name	T109
Test name
Test status
Simulation time	491894009 ps
CPU time	3.6 seconds
Started	Apr 28 12:51:45 PM PDT 24
Finished	Apr 28 12:51:49 PM PDT 24
Peak memory	217276 kb
Host	smart-d05efd93-e29c-44dc-9968-49b36b8f46cf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814648969 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.814648969
Directory	/workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1483299862
Short name	T988
Test name
Test status
Simulation time	89492790 ps
CPU time	2.74 seconds
Started	Apr 28 12:51:43 PM PDT 24
Finished	Apr 28 12:51:47 PM PDT 24
Peak memory	200612 kb
Host	smart-3da2dab3-21b6-4e34-82d4-8b6800c482f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483299862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_tl_errors.1483299862
Directory	/workspace/15.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2566956454
Short name	T84
Test name
Test status
Simulation time	475577952 ps
CPU time	3.16 seconds
Started	Apr 28 12:51:40 PM PDT 24
Finished	Apr 28 12:51:44 PM PDT 24
Peak memory	200680 kb
Host	smart-af96a2b2-ba4a-4a39-87a6-722988e9c505
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566956454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 15.clkmgr_tl_intg_err.2566956454
Directory	/workspace/15.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1773803233
Short name	T919
Test name
Test status
Simulation time	44525418 ps
CPU time	1.31 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:52 PM PDT 24
Peak memory	200408 kb
Host	smart-bed2e1c8-c726-4021-9b61-cac96664f7fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773803233 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.1773803233
Directory	/workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.2881072233
Short name	T878
Test name
Test status
Simulation time	27533366 ps
CPU time	0.79 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:51 PM PDT 24
Peak memory	200420 kb
Host	smart-a7d0e89a-94ba-402a-8c7e-f79b64c35cba
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881072233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .clkmgr_csr_rw.2881072233
Directory	/workspace/16.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3538190839
Short name	T890
Test name
Test status
Simulation time	14717154 ps
CPU time	0.69 seconds
Started	Apr 28 12:51:51 PM PDT 24
Finished	Apr 28 12:51:52 PM PDT 24
Peak memory	198964 kb
Host	smart-c1def775-b92b-4fff-a7db-b86d1659db8f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538190839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_intr_test.3538190839
Directory	/workspace/16.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3333518456
Short name	T75
Test name
Test status
Simulation time	343395468 ps
CPU time	2.1 seconds
Started	Apr 28 12:51:49 PM PDT 24
Finished	Apr 28 12:51:52 PM PDT 24
Peak memory	200684 kb
Host	smart-38403811-1669-4df8-855b-34e424d3329b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333518456 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.clkmgr_same_csr_outstanding.3333518456
Directory	/workspace/16.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2175959540
Short name	T57
Test name
Test status
Simulation time	144814298 ps
CPU time	2.15 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:51 PM PDT 24
Peak memory	201084 kb
Host	smart-0d2d4e44-ee27-4314-adb3-428cadfc289c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175959540 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.clkmgr_shadow_reg_errors.2175959540
Directory	/workspace/16.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.37378133
Short name	T118
Test name
Test status
Simulation time	112244022 ps
CPU time	1.83 seconds
Started	Apr 28 12:51:51 PM PDT 24
Finished	Apr 28 12:51:54 PM PDT 24
Peak memory	201200 kb
Host	smart-8f195479-49e1-44fc-a58b-502d0a430cd4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37378133 -assert nopostproc +UVM_TESTNAME= clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.37378133
Directory	/workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3323861181
Short name	T871
Test name
Test status
Simulation time	38857285 ps
CPU time	2.09 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	200716 kb
Host	smart-e7b6fd1f-761e-46ba-89ec-f349e6a2c071
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323861181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl kmgr_tl_errors.3323861181
Directory	/workspace/16.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1294076614
Short name	T156
Test name
Test status
Simulation time	102064817 ps
CPU time	2.44 seconds
Started	Apr 28 12:51:58 PM PDT 24
Finished	Apr 28 12:52:01 PM PDT 24
Peak memory	200764 kb
Host	smart-9cd25d4b-afbc-429d-9167-9f0d83106b6f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294076614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 16.clkmgr_tl_intg_err.1294076614
Directory	/workspace/16.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3677102184
Short name	T948
Test name
Test status
Simulation time	44121052 ps
CPU time	1.02 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:54 PM PDT 24
Peak memory	200452 kb
Host	smart-494122f2-ab06-41d7-b987-694c5a0fe7de
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677102184 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3677102184
Directory	/workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1247731173
Short name	T956
Test name
Test status
Simulation time	62614822 ps
CPU time	0.93 seconds
Started	Apr 28 12:52:06 PM PDT 24
Finished	Apr 28 12:52:08 PM PDT 24
Peak memory	200452 kb
Host	smart-f9bae5ed-2d8d-4a16-a154-af7296341a02
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247731173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .clkmgr_csr_rw.1247731173
Directory	/workspace/17.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3364322648
Short name	T1000
Test name
Test status
Simulation time	24421868 ps
CPU time	0.69 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	198888 kb
Host	smart-2090e79c-1996-49c8-8dcc-15435e27aa0d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364322648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_intr_test.3364322648
Directory	/workspace/17.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1644499740
Short name	T72
Test name
Test status
Simulation time	18852183 ps
CPU time	0.94 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:50 PM PDT 24
Peak memory	200348 kb
Host	smart-f6871580-bf38-4a4b-bd59-a97f8247aa37
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644499740 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.clkmgr_same_csr_outstanding.1644499740
Directory	/workspace/17.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.776746779
Short name	T955
Test name
Test status
Simulation time	519407433 ps
CPU time	2.78 seconds
Started	Apr 28 12:51:47 PM PDT 24
Finished	Apr 28 12:51:50 PM PDT 24
Peak memory	201264 kb
Host	smart-c943c881-3208-4124-887e-f2b603075735
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776746779 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.776746779
Directory	/workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2312357884
Short name	T1003
Test name
Test status
Simulation time	41604845 ps
CPU time	2.51 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:56 PM PDT 24
Peak memory	200676 kb
Host	smart-e17146ef-265f-48c6-976c-23e9f109b262
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312357884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl kmgr_tl_errors.2312357884
Directory	/workspace/17.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2017597503
Short name	T916
Test name
Test status
Simulation time	65556307 ps
CPU time	1.71 seconds
Started	Apr 28 12:51:46 PM PDT 24
Finished	Apr 28 12:51:49 PM PDT 24
Peak memory	200692 kb
Host	smart-78132a51-7297-4338-8224-34fa1f25f018
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017597503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 17.clkmgr_tl_intg_err.2017597503
Directory	/workspace/17.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.898952535
Short name	T989
Test name
Test status
Simulation time	17886210 ps
CPU time	0.9 seconds
Started	Apr 28 12:51:47 PM PDT 24
Finished	Apr 28 12:51:48 PM PDT 24
Peak memory	200552 kb
Host	smart-04f55b2b-b483-412e-a2ac-848789176380
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898952535 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.898952535
Directory	/workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.628146505
Short name	T71
Test name
Test status
Simulation time	91495701 ps
CPU time	1.06 seconds
Started	Apr 28 12:51:46 PM PDT 24
Finished	Apr 28 12:51:48 PM PDT 24
Peak memory	200292 kb
Host	smart-1661930b-adde-4c46-94aa-1e9a6eb71712
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628146505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. clkmgr_csr_rw.628146505
Directory	/workspace/18.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1323735264
Short name	T857
Test name
Test status
Simulation time	12131092 ps
CPU time	0.67 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:51 PM PDT 24
Peak memory	199008 kb
Host	smart-1fb06b13-97ef-425d-8b11-10ee76d613c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323735264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_intr_test.1323735264
Directory	/workspace/18.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1436146507
Short name	T991
Test name
Test status
Simulation time	105822221 ps
CPU time	1.59 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:50 PM PDT 24
Peak memory	200684 kb
Host	smart-b2f980d1-dc23-47db-adf7-3d2a223e50f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436146507 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.clkmgr_same_csr_outstanding.1436146507
Directory	/workspace/18.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.4249770374
Short name	T111
Test name
Test status
Simulation time	206025426 ps
CPU time	2.25 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	201128 kb
Host	smart-20b9a624-c679-4dd3-8de7-210f3356a263
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249770374 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.clkmgr_shadow_reg_errors.4249770374
Directory	/workspace/18.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1245982283
Short name	T947
Test name
Test status
Simulation time	217296244 ps
CPU time	2.53 seconds
Started	Apr 28 12:51:57 PM PDT 24
Finished	Apr 28 12:52:01 PM PDT 24
Peak memory	201320 kb
Host	smart-dce07899-3578-49d4-9044-86d23d487cad
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245982283 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.1245982283
Directory	/workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.405070151
Short name	T946
Test name
Test status
Simulation time	219835202 ps
CPU time	3.55 seconds
Started	Apr 28 12:51:49 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	200748 kb
Host	smart-c3dd618a-78d2-44e1-a2b9-a90b129c449f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405070151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk mgr_tl_errors.405070151
Directory	/workspace/18.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.268645817
Short name	T902
Test name
Test status
Simulation time	173689995 ps
CPU time	1.85 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:51 PM PDT 24
Peak memory	200680 kb
Host	smart-ed1ad1f8-2be9-4c76-a1bd-6d94a6d0bf9a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268645817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.clkmgr_tl_intg_err.268645817
Directory	/workspace/18.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.2898195353
Short name	T920
Test name
Test status
Simulation time	31346195 ps
CPU time	1.03 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:49 PM PDT 24
Peak memory	200500 kb
Host	smart-e3ad1b96-e580-4cc1-b21d-4c77d88a4c8b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898195353 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.2898195353
Directory	/workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.4269528368
Short name	T986
Test name
Test status
Simulation time	73724127 ps
CPU time	1.04 seconds
Started	Apr 28 12:51:58 PM PDT 24
Finished	Apr 28 12:52:00 PM PDT 24
Peak memory	200504 kb
Host	smart-c7ccea37-877b-40d1-971f-185cc2ef462e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269528368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .clkmgr_csr_rw.4269528368
Directory	/workspace/19.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3198109002
Short name	T873
Test name
Test status
Simulation time	36776237 ps
CPU time	0.69 seconds
Started	Apr 28 12:51:49 PM PDT 24
Finished	Apr 28 12:51:50 PM PDT 24
Peak memory	198980 kb
Host	smart-12633cfd-4863-40d6-ba12-e7d61244d845
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198109002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_intr_test.3198109002
Directory	/workspace/19.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3422819478
Short name	T1006
Test name
Test status
Simulation time	102485274 ps
CPU time	1.34 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:51 PM PDT 24
Peak memory	200688 kb
Host	smart-a65fc8bb-1e43-45fc-91b0-5288f03f3c92
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422819478 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.clkmgr_same_csr_outstanding.3422819478
Directory	/workspace/19.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.847691776
Short name	T959
Test name
Test status
Simulation time	171505694 ps
CPU time	1.96 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:54 PM PDT 24
Peak memory	201000 kb
Host	smart-b2fb003b-81dc-4699-a96b-0fc50aff24ee
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847691776 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 19.clkmgr_shadow_reg_errors.847691776
Directory	/workspace/19.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1497710586
Short name	T108
Test name
Test status
Simulation time	134107715 ps
CPU time	2.8 seconds
Started	Apr 28 12:51:58 PM PDT 24
Finished	Apr 28 12:52:02 PM PDT 24
Peak memory	217476 kb
Host	smart-e38ac283-e166-4dd8-b7e6-4b9511e87f51
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497710586 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.1497710586
Directory	/workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1126450540
Short name	T909
Test name
Test status
Simulation time	216725668 ps
CPU time	3.46 seconds
Started	Apr 28 12:51:49 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	200680 kb
Host	smart-f5c82511-ec4c-4b80-a148-52076c3e4cb5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126450540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_tl_errors.1126450540
Directory	/workspace/19.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2448901570
Short name	T894
Test name
Test status
Simulation time	126924731 ps
CPU time	1.45 seconds
Started	Apr 28 12:51:20 PM PDT 24
Finished	Apr 28 12:51:22 PM PDT 24
Peak memory	200464 kb
Host	smart-51b85a1b-f6f8-4d03-8cd8-91a1a38e760b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448901570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_aliasing.2448901570
Directory	/workspace/2.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.652507141
Short name	T896
Test name
Test status
Simulation time	280388184 ps
CPU time	4.89 seconds
Started	Apr 28 12:51:22 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200696 kb
Host	smart-42b3eb46-e51c-428a-aef8-dc3b0bc135db
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652507141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 2.clkmgr_csr_bit_bash.652507141
Directory	/workspace/2.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1290562468
Short name	T917
Test name
Test status
Simulation time	37649631 ps
CPU time	0.92 seconds
Started	Apr 28 12:51:23 PM PDT 24
Finished	Apr 28 12:51:25 PM PDT 24
Peak memory	200320 kb
Host	smart-5f71618d-c702-4ce6-ad68-69794a01bcba
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290562468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_hw_reset.1290562468
Directory	/workspace/2.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2282057748
Short name	T860
Test name
Test status
Simulation time	70567842 ps
CPU time	1.4 seconds
Started	Apr 28 12:51:23 PM PDT 24
Finished	Apr 28 12:51:25 PM PDT 24
Peak memory	200552 kb
Host	smart-c9af0076-b651-4eba-875c-7effa8b7ace5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282057748 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.2282057748
Directory	/workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.4070077971
Short name	T904
Test name
Test status
Simulation time	17781681 ps
CPU time	0.84 seconds
Started	Apr 28 12:51:24 PM PDT 24
Finished	Apr 28 12:51:26 PM PDT 24
Peak memory	200464 kb
Host	smart-7e5d9a20-cf5c-4c86-a902-eac8d82191a0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070077971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. clkmgr_csr_rw.4070077971
Directory	/workspace/2.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.1679308614
Short name	T869
Test name
Test status
Simulation time	30042509 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:17 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	198964 kb
Host	smart-c1217be6-7f51-475c-800e-451ab76a5f34
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679308614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_intr_test.1679308614
Directory	/workspace/2.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.577045865
Short name	T976
Test name
Test status
Simulation time	558040168 ps
CPU time	2.71 seconds
Started	Apr 28 12:51:23 PM PDT 24
Finished	Apr 28 12:51:26 PM PDT 24
Peak memory	200548 kb
Host	smart-3b4543e2-ea72-4447-910c-3e16528d9f08
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577045865 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.clkmgr_same_csr_outstanding.577045865
Directory	/workspace/2.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.351142980
Short name	T119
Test name
Test status
Simulation time	96754856 ps
CPU time	1.21 seconds
Started	Apr 28 12:51:16 PM PDT 24
Finished	Apr 28 12:51:18 PM PDT 24
Peak memory	200924 kb
Host	smart-d48eea16-b677-4b30-83f4-ebe29efe45c4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351142980 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.clkmgr_shadow_reg_errors.351142980
Directory	/workspace/2.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.507227557
Short name	T121
Test name
Test status
Simulation time	162132771 ps
CPU time	2.84 seconds
Started	Apr 28 12:51:19 PM PDT 24
Finished	Apr 28 12:51:23 PM PDT 24
Peak memory	209204 kb
Host	smart-95639cb6-ff8b-4cdd-b4dc-91773123267e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507227557 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.507227557
Directory	/workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3425484310
Short name	T969
Test name
Test status
Simulation time	52272364 ps
CPU time	1.67 seconds
Started	Apr 28 12:51:14 PM PDT 24
Finished	Apr 28 12:51:17 PM PDT 24
Peak memory	200668 kb
Host	smart-5159d931-ddc4-4e19-8a72-69447fa3b8f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425484310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_tl_errors.3425484310
Directory	/workspace/2.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.2341812546
Short name	T155
Test name
Test status
Simulation time	355810436 ps
CPU time	3.1 seconds
Started	Apr 28 12:51:20 PM PDT 24
Finished	Apr 28 12:51:24 PM PDT 24
Peak memory	200648 kb
Host	smart-8970916f-989f-4a25-bff2-420a7f4fbbf5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341812546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 2.clkmgr_tl_intg_err.2341812546
Directory	/workspace/2.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2890902263
Short name	T861
Test name
Test status
Simulation time	27301253 ps
CPU time	0.65 seconds
Started	Apr 28 12:51:45 PM PDT 24
Finished	Apr 28 12:51:46 PM PDT 24
Peak memory	199060 kb
Host	smart-0f8e0249-b0eb-4137-adb8-76d844139c66
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890902263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl kmgr_intr_test.2890902263
Directory	/workspace/20.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3706008203
Short name	T882
Test name
Test status
Simulation time	34809478 ps
CPU time	0.77 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:52 PM PDT 24
Peak memory	198828 kb
Host	smart-24e6020b-6d6a-4982-acea-1f4731c91b7f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706008203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl kmgr_intr_test.3706008203
Directory	/workspace/21.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1338867706
Short name	T883
Test name
Test status
Simulation time	39362660 ps
CPU time	0.72 seconds
Started	Apr 28 12:51:57 PM PDT 24
Finished	Apr 28 12:51:59 PM PDT 24
Peak memory	199076 kb
Host	smart-663ed597-5eb3-4cb8-95ba-ccb24f793021
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338867706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl kmgr_intr_test.1338867706
Directory	/workspace/22.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3126359420
Short name	T938
Test name
Test status
Simulation time	27949650 ps
CPU time	0.7 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:54 PM PDT 24
Peak memory	198888 kb
Host	smart-d3a0e789-9ac5-42d1-bdaf-090da10d4f6b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126359420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl kmgr_intr_test.3126359420
Directory	/workspace/23.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2885750562
Short name	T954
Test name
Test status
Simulation time	126156475 ps
CPU time	0.92 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:52 PM PDT 24
Peak memory	198864 kb
Host	smart-582a40df-2613-48c2-80a7-b035a966cbda
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885750562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl kmgr_intr_test.2885750562
Directory	/workspace/24.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.401274801
Short name	T879
Test name
Test status
Simulation time	26145348 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:49 PM PDT 24
Finished	Apr 28 12:51:50 PM PDT 24
Peak memory	198952 kb
Host	smart-b5c7e071-4a8a-43a9-a1a7-3329b811e898
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401274801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk mgr_intr_test.401274801
Directory	/workspace/25.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.353252695
Short name	T993
Test name
Test status
Simulation time	28887293 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:49 PM PDT 24
Peak memory	198872 kb
Host	smart-68f19423-3bad-45f0-8537-bb73eb2b8f82
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353252695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clk mgr_intr_test.353252695
Directory	/workspace/26.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3856298980
Short name	T870
Test name
Test status
Simulation time	22738512 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:50 PM PDT 24
Peak memory	199008 kb
Host	smart-1e2bc02d-382c-4846-8b39-e7aa7be30a90
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856298980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl kmgr_intr_test.3856298980
Directory	/workspace/27.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.840630733
Short name	T987
Test name
Test status
Simulation time	33043537 ps
CPU time	0.7 seconds
Started	Apr 28 12:51:48 PM PDT 24
Finished	Apr 28 12:51:49 PM PDT 24
Peak memory	198924 kb
Host	smart-d4ebc721-542a-464e-b4b4-34090c549bf3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840630733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk mgr_intr_test.840630733
Directory	/workspace/28.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3115137925
Short name	T868
Test name
Test status
Simulation time	44579161 ps
CPU time	0.78 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:52 PM PDT 24
Peak memory	198996 kb
Host	smart-d5af5fcf-1dab-4ecf-b91b-be5c4f9ce86d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115137925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl kmgr_intr_test.3115137925
Directory	/workspace/29.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3442280626
Short name	T952
Test name
Test status
Simulation time	28247185 ps
CPU time	1.5 seconds
Started	Apr 28 12:51:21 PM PDT 24
Finished	Apr 28 12:51:23 PM PDT 24
Peak memory	200648 kb
Host	smart-9bda46ac-0c30-47e4-b263-8c3a3237e4cb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442280626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_aliasing.3442280626
Directory	/workspace/3.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1533742408
Short name	T923
Test name
Test status
Simulation time	971965906 ps
CPU time	6.43 seconds
Started	Apr 28 12:51:22 PM PDT 24
Finished	Apr 28 12:51:29 PM PDT 24
Peak memory	200716 kb
Host	smart-4e69fe12-cc6c-494f-be81-55792130139e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533742408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_bit_bash.1533742408
Directory	/workspace/3.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2851671405
Short name	T872
Test name
Test status
Simulation time	39014631 ps
CPU time	0.81 seconds
Started	Apr 28 12:51:22 PM PDT 24
Finished	Apr 28 12:51:23 PM PDT 24
Peak memory	200416 kb
Host	smart-31ebed1d-ddab-48ea-9409-3d1ef8aaed08
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851671405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_hw_reset.2851671405
Directory	/workspace/3.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1252203390
Short name	T962
Test name
Test status
Simulation time	111953598 ps
CPU time	1.31 seconds
Started	Apr 28 12:51:19 PM PDT 24
Finished	Apr 28 12:51:21 PM PDT 24
Peak memory	200448 kb
Host	smart-93e26f1a-f7ff-4ffd-ac6d-3cde457060f5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252203390 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.1252203390
Directory	/workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.3015040276
Short name	T953
Test name
Test status
Simulation time	44776652 ps
CPU time	0.86 seconds
Started	Apr 28 12:51:23 PM PDT 24
Finished	Apr 28 12:51:24 PM PDT 24
Peak memory	200228 kb
Host	smart-529f03ef-f699-47a6-9a02-fe135bdc68ec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015040276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. clkmgr_csr_rw.3015040276
Directory	/workspace/3.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.159484592
Short name	T889
Test name
Test status
Simulation time	23060420 ps
CPU time	0.74 seconds
Started	Apr 28 12:51:21 PM PDT 24
Finished	Apr 28 12:51:23 PM PDT 24
Peak memory	198936 kb
Host	smart-98ab5149-3819-4bea-b6da-1cb70d082695
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159484592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm gr_intr_test.159484592
Directory	/workspace/3.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2397615357
Short name	T972
Test name
Test status
Simulation time	108462286 ps
CPU time	1.34 seconds
Started	Apr 28 12:51:21 PM PDT 24
Finished	Apr 28 12:51:22 PM PDT 24
Peak memory	200404 kb
Host	smart-e0257190-bf43-4b8a-a006-afecf7568d36
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397615357 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.clkmgr_same_csr_outstanding.2397615357
Directory	/workspace/3.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3985440385
Short name	T978
Test name
Test status
Simulation time	97252841 ps
CPU time	1.88 seconds
Started	Apr 28 12:51:22 PM PDT 24
Finished	Apr 28 12:51:25 PM PDT 24
Peak memory	201080 kb
Host	smart-11f2f818-ddad-40d0-ab12-4db5d3bc0323
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985440385 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.clkmgr_shadow_reg_errors.3985440385
Directory	/workspace/3.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4211382221
Short name	T52
Test name
Test status
Simulation time	166938744 ps
CPU time	2.78 seconds
Started	Apr 28 12:51:22 PM PDT 24
Finished	Apr 28 12:51:25 PM PDT 24
Peak memory	209328 kb
Host	smart-931de001-60a9-4806-907d-7268e8e13780
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211382221 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.4211382221
Directory	/workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1609619373
Short name	T915
Test name
Test status
Simulation time	152035340 ps
CPU time	2.58 seconds
Started	Apr 28 12:51:23 PM PDT 24
Finished	Apr 28 12:51:26 PM PDT 24
Peak memory	200620 kb
Host	smart-e1d73d4f-3c98-429f-8713-52320dd6fa0e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609619373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_tl_errors.1609619373
Directory	/workspace/3.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3632678054
Short name	T154
Test name
Test status
Simulation time	64471788 ps
CPU time	1.67 seconds
Started	Apr 28 12:51:23 PM PDT 24
Finished	Apr 28 12:51:25 PM PDT 24
Peak memory	200488 kb
Host	smart-381a53a0-56e8-4d68-bbaa-825783d0e232
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632678054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 3.clkmgr_tl_intg_err.3632678054
Directory	/workspace/3.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.747984489
Short name	T926
Test name
Test status
Simulation time	37565203 ps
CPU time	0.72 seconds
Started	Apr 28 12:51:47 PM PDT 24
Finished	Apr 28 12:51:49 PM PDT 24
Peak memory	198880 kb
Host	smart-e5e4b835-e3c2-4dfe-8c2f-6df6e9e8c803
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747984489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clk mgr_intr_test.747984489
Directory	/workspace/30.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3716783023
Short name	T927
Test name
Test status
Simulation time	15471075 ps
CPU time	0.67 seconds
Started	Apr 28 12:51:50 PM PDT 24
Finished	Apr 28 12:51:52 PM PDT 24
Peak memory	198928 kb
Host	smart-d2575888-38e0-4c50-a8ab-138a86bf24a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716783023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl kmgr_intr_test.3716783023
Directory	/workspace/31.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.465401290
Short name	T998
Test name
Test status
Simulation time	77302753 ps
CPU time	0.79 seconds
Started	Apr 28 12:51:58 PM PDT 24
Finished	Apr 28 12:51:59 PM PDT 24
Peak memory	199012 kb
Host	smart-01663963-a0f5-4872-a7d1-1959c7c5611f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465401290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clk mgr_intr_test.465401290
Directory	/workspace/32.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.3367111554
Short name	T911
Test name
Test status
Simulation time	16563163 ps
CPU time	0.67 seconds
Started	Apr 28 12:51:49 PM PDT 24
Finished	Apr 28 12:51:50 PM PDT 24
Peak memory	198872 kb
Host	smart-b6b99bb2-6312-432b-99d9-8676c127c344
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367111554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl kmgr_intr_test.3367111554
Directory	/workspace/33.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.853350348
Short name	T900
Test name
Test status
Simulation time	34800080 ps
CPU time	0.69 seconds
Started	Apr 28 12:51:56 PM PDT 24
Finished	Apr 28 12:51:58 PM PDT 24
Peak memory	198884 kb
Host	smart-7dd6027f-204f-4ee0-9195-95fffdcd639b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853350348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk mgr_intr_test.853350348
Directory	/workspace/34.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.771453096
Short name	T892
Test name
Test status
Simulation time	23604700 ps
CPU time	0.72 seconds
Started	Apr 28 12:51:58 PM PDT 24
Finished	Apr 28 12:52:00 PM PDT 24
Peak memory	199092 kb
Host	smart-43665f56-b41e-4dd4-b0e0-e5ee01c866ab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771453096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk mgr_intr_test.771453096
Directory	/workspace/35.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.3089795169
Short name	T925
Test name
Test status
Simulation time	14527834 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:54 PM PDT 24
Peak memory	198996 kb
Host	smart-510b0154-c854-4bf6-a988-c50e2d7b97f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089795169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl kmgr_intr_test.3089795169
Directory	/workspace/36.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.408640901
Short name	T949
Test name
Test status
Simulation time	12592842 ps
CPU time	0.67 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	199036 kb
Host	smart-84cde618-f8ca-4ee5-ad4c-efecec84b4df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408640901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clk mgr_intr_test.408640901
Directory	/workspace/37.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1995481427
Short name	T863
Test name
Test status
Simulation time	13433009 ps
CPU time	0.67 seconds
Started	Apr 28 12:51:53 PM PDT 24
Finished	Apr 28 12:51:55 PM PDT 24
Peak memory	198984 kb
Host	smart-dd61ae2a-d6d6-4c14-b1e0-a776fb9f1b4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995481427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl kmgr_intr_test.1995481427
Directory	/workspace/38.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2182702985
Short name	T924
Test name
Test status
Simulation time	27917912 ps
CPU time	0.69 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:51:56 PM PDT 24
Peak memory	199008 kb
Host	smart-7b0efb52-5512-4d27-8d9a-8f564860f097
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182702985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl kmgr_intr_test.2182702985
Directory	/workspace/39.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2831047112
Short name	T907
Test name
Test status
Simulation time	107472736 ps
CPU time	1.75 seconds
Started	Apr 28 12:51:24 PM PDT 24
Finished	Apr 28 12:51:27 PM PDT 24
Peak memory	200688 kb
Host	smart-0cef5315-e1aa-4168-aa64-15409d844d0b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831047112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_aliasing.2831047112
Directory	/workspace/4.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2482117801
Short name	T964
Test name
Test status
Simulation time	1020128053 ps
CPU time	9.41 seconds
Started	Apr 28 12:51:23 PM PDT 24
Finished	Apr 28 12:51:33 PM PDT 24
Peak memory	200700 kb
Host	smart-0bd7a3c3-ee20-412f-b4d8-76f62905bc11
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482117801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_bit_bash.2482117801
Directory	/workspace/4.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3549043120
Short name	T912
Test name
Test status
Simulation time	24707630 ps
CPU time	0.87 seconds
Started	Apr 28 12:51:20 PM PDT 24
Finished	Apr 28 12:51:22 PM PDT 24
Peak memory	200392 kb
Host	smart-a0618866-adcc-4e6f-abd4-03244147fca7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549043120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_hw_reset.3549043120
Directory	/workspace/4.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2446622088
Short name	T958
Test name
Test status
Simulation time	23591107 ps
CPU time	1.21 seconds
Started	Apr 28 12:51:28 PM PDT 24
Finished	Apr 28 12:51:30 PM PDT 24
Peak memory	200484 kb
Host	smart-a3a518ac-616d-4f17-9fd5-0099af87f0c8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446622088 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.2446622088
Directory	/workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3438046755
Short name	T1009
Test name
Test status
Simulation time	102831643 ps
CPU time	1.06 seconds
Started	Apr 28 12:51:22 PM PDT 24
Finished	Apr 28 12:51:24 PM PDT 24
Peak memory	200456 kb
Host	smart-e3f3bcc7-3d54-4625-b156-0bd0cc339f27
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438046755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. clkmgr_csr_rw.3438046755
Directory	/workspace/4.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1346003972
Short name	T888
Test name
Test status
Simulation time	82577085 ps
CPU time	0.79 seconds
Started	Apr 28 12:51:24 PM PDT 24
Finished	Apr 28 12:51:25 PM PDT 24
Peak memory	198908 kb
Host	smart-7a3e65d9-50eb-4c23-a818-9a3a38018e3b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346003972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_intr_test.1346003972
Directory	/workspace/4.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.680573343
Short name	T960
Test name
Test status
Simulation time	256656022 ps
CPU time	1.84 seconds
Started	Apr 28 12:51:27 PM PDT 24
Finished	Apr 28 12:51:29 PM PDT 24
Peak memory	200724 kb
Host	smart-2fafcfdc-0f85-4f18-8ae8-802764cac766
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680573343 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.clkmgr_same_csr_outstanding.680573343
Directory	/workspace/4.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3201079234
Short name	T102
Test name
Test status
Simulation time	101327547 ps
CPU time	1.36 seconds
Started	Apr 28 12:51:22 PM PDT 24
Finished	Apr 28 12:51:24 PM PDT 24
Peak memory	200904 kb
Host	smart-55285fbb-620e-4b1c-b578-e8f695834a8d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201079234 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.clkmgr_shadow_reg_errors.3201079234
Directory	/workspace/4.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3388248884
Short name	T101
Test name
Test status
Simulation time	81289285 ps
CPU time	1.8 seconds
Started	Apr 28 12:51:23 PM PDT 24
Finished	Apr 28 12:51:25 PM PDT 24
Peak memory	217532 kb
Host	smart-c641ed73-166c-4da2-a685-2527f40c8509
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388248884 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.3388248884
Directory	/workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2536505123
Short name	T876
Test name
Test status
Simulation time	337233378 ps
CPU time	3.34 seconds
Started	Apr 28 12:51:24 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200692 kb
Host	smart-e65fd900-3615-4a81-b461-9e7883cd2933
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536505123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_tl_errors.2536505123
Directory	/workspace/4.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3481386455
Short name	T90
Test name
Test status
Simulation time	63391522 ps
CPU time	1.63 seconds
Started	Apr 28 12:51:21 PM PDT 24
Finished	Apr 28 12:51:23 PM PDT 24
Peak memory	200528 kb
Host	smart-75ec8238-c786-4578-a370-5624678703c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481386455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.clkmgr_tl_intg_err.3481386455
Directory	/workspace/4.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.320615993
Short name	T943
Test name
Test status
Simulation time	41909043 ps
CPU time	0.71 seconds
Started	Apr 28 12:51:55 PM PDT 24
Finished	Apr 28 12:51:57 PM PDT 24
Peak memory	198868 kb
Host	smart-a4c1319d-6187-4c83-aab0-2f823b50745b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320615993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clk mgr_intr_test.320615993
Directory	/workspace/40.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.463693658
Short name	T921
Test name
Test status
Simulation time	11819634 ps
CPU time	0.63 seconds
Started	Apr 28 12:51:56 PM PDT 24
Finished	Apr 28 12:51:58 PM PDT 24
Peak memory	198884 kb
Host	smart-4a35963f-30e3-4350-a113-9706b92da479
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463693658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk mgr_intr_test.463693658
Directory	/workspace/41.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1438845455
Short name	T981
Test name
Test status
Simulation time	35395871 ps
CPU time	0.73 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:51:56 PM PDT 24
Peak memory	198976 kb
Host	smart-86d9ff52-3f0e-439a-a9ec-842164a2b70d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438845455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl kmgr_intr_test.1438845455
Directory	/workspace/42.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.994731105
Short name	T881
Test name
Test status
Simulation time	15132722 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:51:56 PM PDT 24
Peak memory	199004 kb
Host	smart-b59bae14-19e1-49dd-95e3-12b0a3182422
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994731105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clk mgr_intr_test.994731105
Directory	/workspace/43.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.177937438
Short name	T1002
Test name
Test status
Simulation time	25422175 ps
CPU time	0.66 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:53 PM PDT 24
Peak memory	198880 kb
Host	smart-da8b1c36-6541-4fa3-8e19-f373435fc246
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177937438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clk mgr_intr_test.177937438
Directory	/workspace/44.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3384332274
Short name	T929
Test name
Test status
Simulation time	21069174 ps
CPU time	0.67 seconds
Started	Apr 28 12:51:52 PM PDT 24
Finished	Apr 28 12:51:54 PM PDT 24
Peak memory	198968 kb
Host	smart-5a297004-f5d9-47c6-9004-9cde1dff954e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384332274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl kmgr_intr_test.3384332274
Directory	/workspace/45.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.493907608
Short name	T880
Test name
Test status
Simulation time	21818210 ps
CPU time	0.66 seconds
Started	Apr 28 12:51:56 PM PDT 24
Finished	Apr 28 12:51:57 PM PDT 24
Peak memory	198936 kb
Host	smart-d31c7067-2b58-4698-a67f-d23ce816163b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493907608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clk mgr_intr_test.493907608
Directory	/workspace/46.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2785076158
Short name	T968
Test name
Test status
Simulation time	41131362 ps
CPU time	0.72 seconds
Started	Apr 28 12:51:54 PM PDT 24
Finished	Apr 28 12:51:56 PM PDT 24
Peak memory	198904 kb
Host	smart-ec2c9d3f-85d8-4bba-8f93-2e73a31e7321
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785076158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl kmgr_intr_test.2785076158
Directory	/workspace/47.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2358212935
Short name	T977
Test name
Test status
Simulation time	37206721 ps
CPU time	0.71 seconds
Started	Apr 28 12:51:56 PM PDT 24
Finished	Apr 28 12:51:58 PM PDT 24
Peak memory	198884 kb
Host	smart-ef42fff2-6dfe-41df-b40b-697199f598f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358212935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl kmgr_intr_test.2358212935
Directory	/workspace/48.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.55818082
Short name	T1010
Test name
Test status
Simulation time	23691822 ps
CPU time	0.67 seconds
Started	Apr 28 12:51:51 PM PDT 24
Finished	Apr 28 12:51:52 PM PDT 24
Peak memory	199040 kb
Host	smart-3e2bcde1-81b4-426f-9fe4-f35a81dc1945
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55818082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkm gr_intr_test.55818082
Directory	/workspace/49.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1543336357
Short name	T887
Test name
Test status
Simulation time	81937225 ps
CPU time	1.28 seconds
Started	Apr 28 12:51:26 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200548 kb
Host	smart-8383ab9e-6f40-4472-92c2-4be355381885
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543336357 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1543336357
Directory	/workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2242088835
Short name	T918
Test name
Test status
Simulation time	16440618 ps
CPU time	0.81 seconds
Started	Apr 28 12:51:27 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200428 kb
Host	smart-02b9a123-14d3-472d-8906-8ba54b20c410
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242088835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. clkmgr_csr_rw.2242088835
Directory	/workspace/5.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.708285032
Short name	T932
Test name
Test status
Simulation time	36644510 ps
CPU time	0.72 seconds
Started	Apr 28 12:51:28 PM PDT 24
Finished	Apr 28 12:51:29 PM PDT 24
Peak memory	198964 kb
Host	smart-5ed7db4c-eee3-43f7-870c-d7dc35f16378
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708285032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm gr_intr_test.708285032
Directory	/workspace/5.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3030021055
Short name	T910
Test name
Test status
Simulation time	104041374 ps
CPU time	1.46 seconds
Started	Apr 28 12:51:26 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200704 kb
Host	smart-5113c8b4-fb8d-4d56-aba4-a826348b8315
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030021055 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.clkmgr_same_csr_outstanding.3030021055
Directory	/workspace/5.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3430929228
Short name	T974
Test name
Test status
Simulation time	181049116 ps
CPU time	2.2 seconds
Started	Apr 28 12:51:28 PM PDT 24
Finished	Apr 28 12:51:31 PM PDT 24
Peak memory	201140 kb
Host	smart-aae28efb-3d75-4173-b32f-3c61fc11f3c7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430929228 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.clkmgr_shadow_reg_errors.3430929228
Directory	/workspace/5.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2914025066
Short name	T1008
Test name
Test status
Simulation time	184479621 ps
CPU time	2.33 seconds
Started	Apr 28 12:51:27 PM PDT 24
Finished	Apr 28 12:51:30 PM PDT 24
Peak memory	216900 kb
Host	smart-a2ffb380-a37d-466c-9d6b-213c9a177b64
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914025066 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.2914025066
Directory	/workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1316276737
Short name	T875
Test name
Test status
Simulation time	22839782 ps
CPU time	1.41 seconds
Started	Apr 28 12:51:26 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200756 kb
Host	smart-4fff3450-2658-4e5c-80f1-4df095bb23cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316276737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_tl_errors.1316276737
Directory	/workspace/5.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2895978545
Short name	T951
Test name
Test status
Simulation time	87066883 ps
CPU time	1.24 seconds
Started	Apr 28 12:51:27 PM PDT 24
Finished	Apr 28 12:51:29 PM PDT 24
Peak memory	200564 kb
Host	smart-3aab0740-135a-4429-9bff-f2863cf1510c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895978545 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2895978545
Directory	/workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1438332995
Short name	T74
Test name
Test status
Simulation time	43047036 ps
CPU time	0.81 seconds
Started	Apr 28 12:51:26 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200468 kb
Host	smart-81e75122-e6b3-4781-9ceb-09a79776f140
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438332995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. clkmgr_csr_rw.1438332995
Directory	/workspace/6.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1437475707
Short name	T922
Test name
Test status
Simulation time	35177209 ps
CPU time	0.71 seconds
Started	Apr 28 12:51:28 PM PDT 24
Finished	Apr 28 12:51:29 PM PDT 24
Peak memory	198860 kb
Host	smart-1c3cc73f-ec42-4b95-a40f-11045821a691
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437475707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_intr_test.1437475707
Directory	/workspace/6.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.343553288
Short name	T942
Test name
Test status
Simulation time	89047179 ps
CPU time	1.09 seconds
Started	Apr 28 12:51:30 PM PDT 24
Finished	Apr 28 12:51:31 PM PDT 24
Peak memory	200316 kb
Host	smart-bf322b39-dd71-493c-9e49-8347541c64df
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343553288 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.clkmgr_same_csr_outstanding.343553288
Directory	/workspace/6.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1954930990
Short name	T115
Test name
Test status
Simulation time	72472665 ps
CPU time	1.29 seconds
Started	Apr 28 12:51:28 PM PDT 24
Finished	Apr 28 12:51:30 PM PDT 24
Peak memory	200908 kb
Host	smart-78b460f5-6341-46ec-9b6c-ff2ba9fc786a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954930990 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.clkmgr_shadow_reg_errors.1954930990
Directory	/workspace/6.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2928944043
Short name	T105
Test name
Test status
Simulation time	90537668 ps
CPU time	1.95 seconds
Started	Apr 28 12:51:29 PM PDT 24
Finished	Apr 28 12:51:31 PM PDT 24
Peak memory	209152 kb
Host	smart-228caee6-e4d9-4597-a142-9b73f43e3aff
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928944043 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.2928944043
Directory	/workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4104673790
Short name	T885
Test name
Test status
Simulation time	99072017 ps
CPU time	2.09 seconds
Started	Apr 28 12:51:28 PM PDT 24
Finished	Apr 28 12:51:31 PM PDT 24
Peak memory	200652 kb
Host	smart-e667dd23-9aad-4e2a-9cc8-3183696737db
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104673790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_tl_errors.4104673790
Directory	/workspace/6.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1678454230
Short name	T92
Test name
Test status
Simulation time	123476407 ps
CPU time	2.63 seconds
Started	Apr 28 12:51:25 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200632 kb
Host	smart-72c3075d-4f15-48a6-8581-903b680b993f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678454230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.clkmgr_tl_intg_err.1678454230
Directory	/workspace/6.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.208744159
Short name	T983
Test name
Test status
Simulation time	62176026 ps
CPU time	1.24 seconds
Started	Apr 28 12:51:35 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	200532 kb
Host	smart-490caa6b-4b17-454b-a73c-d7088956f010
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208744159 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.208744159
Directory	/workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.933822863
Short name	T893
Test name
Test status
Simulation time	58310059 ps
CPU time	0.92 seconds
Started	Apr 28 12:51:35 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	200368 kb
Host	smart-577b8376-d12d-4521-b108-d420096eca48
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933822863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.c lkmgr_csr_rw.933822863
Directory	/workspace/7.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2266307486
Short name	T935
Test name
Test status
Simulation time	14734673 ps
CPU time	0.68 seconds
Started	Apr 28 12:51:36 PM PDT 24
Finished	Apr 28 12:51:38 PM PDT 24
Peak memory	198884 kb
Host	smart-ab81cdb4-6395-4ccc-87b4-b33c36c13b39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266307486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_intr_test.2266307486
Directory	/workspace/7.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1299519061
Short name	T73
Test name
Test status
Simulation time	32919568 ps
CPU time	1.08 seconds
Started	Apr 28 12:51:35 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	200388 kb
Host	smart-58604986-f104-4b5b-ba7d-36212db8a6cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299519061 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.clkmgr_same_csr_outstanding.1299519061
Directory	/workspace/7.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.914249980
Short name	T112
Test name
Test status
Simulation time	110017244 ps
CPU time	1.36 seconds
Started	Apr 28 12:51:27 PM PDT 24
Finished	Apr 28 12:51:28 PM PDT 24
Peak memory	200836 kb
Host	smart-eed4fe0a-fc27-46cf-a82c-b19df925bd25
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914249980 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 7.clkmgr_shadow_reg_errors.914249980
Directory	/workspace/7.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2817576064
Short name	T53
Test name
Test status
Simulation time	1190021600 ps
CPU time	5.85 seconds
Started	Apr 28 12:51:32 PM PDT 24
Finished	Apr 28 12:51:39 PM PDT 24
Peak memory	209272 kb
Host	smart-a6572eae-a61b-4a7d-b9fa-6e41d5a61f20
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817576064 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2817576064
Directory	/workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.3764174773
Short name	T944
Test name
Test status
Simulation time	114361780 ps
CPU time	3.27 seconds
Started	Apr 28 12:51:33 PM PDT 24
Finished	Apr 28 12:51:37 PM PDT 24
Peak memory	200676 kb
Host	smart-3840dfa4-bdbb-41d7-a815-291ac4f6c11f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764174773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_tl_errors.3764174773
Directory	/workspace/7.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4046763628
Short name	T83
Test name
Test status
Simulation time	135173517 ps
CPU time	1.98 seconds
Started	Apr 28 12:51:34 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	200688 kb
Host	smart-62756710-ffaf-4d93-be65-6fde5459a0e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046763628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.clkmgr_tl_intg_err.4046763628
Directory	/workspace/7.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.860758493
Short name	T864
Test name
Test status
Simulation time	137809562 ps
CPU time	1.42 seconds
Started	Apr 28 12:51:32 PM PDT 24
Finished	Apr 28 12:51:34 PM PDT 24
Peak memory	200444 kb
Host	smart-ce97b462-0414-4a15-83bf-056a4a0ee31d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860758493 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.860758493
Directory	/workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3858687752
Short name	T903
Test name
Test status
Simulation time	19832692 ps
CPU time	0.79 seconds
Started	Apr 28 12:51:32 PM PDT 24
Finished	Apr 28 12:51:33 PM PDT 24
Peak memory	200432 kb
Host	smart-e45d4199-ab32-4781-a57c-d37b4a6e00dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858687752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. clkmgr_csr_rw.3858687752
Directory	/workspace/8.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1916090016
Short name	T980
Test name
Test status
Simulation time	35078661 ps
CPU time	0.73 seconds
Started	Apr 28 12:51:32 PM PDT 24
Finished	Apr 28 12:51:33 PM PDT 24
Peak memory	198936 kb
Host	smart-43b799e7-e9ae-4b77-878a-9de672d34240
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916090016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_intr_test.1916090016
Directory	/workspace/8.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.82363597
Short name	T913
Test name
Test status
Simulation time	28123841 ps
CPU time	1.04 seconds
Started	Apr 28 12:51:34 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	200368 kb
Host	smart-a163f536-187a-41dd-8dfe-974e6b1d457c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82363597 -assert nopostproc +UVM_TESTNAME=clkmgr_ba se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.clkmgr_same_csr_outstanding.82363597
Directory	/workspace/8.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1139615340
Short name	T975
Test name
Test status
Simulation time	126704765 ps
CPU time	1.8 seconds
Started	Apr 28 12:51:31 PM PDT 24
Finished	Apr 28 12:51:33 PM PDT 24
Peak memory	209324 kb
Host	smart-09ee6cf7-e1dd-4713-a487-33b8bbdae25b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139615340 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.1139615340
Directory	/workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1249210306
Short name	T886
Test name
Test status
Simulation time	794403156 ps
CPU time	4.03 seconds
Started	Apr 28 12:51:32 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	200684 kb
Host	smart-c9b1546d-07b9-40f5-ae4f-bbc8a2ddc631
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249210306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_tl_errors.1249210306
Directory	/workspace/8.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.365909703
Short name	T997
Test name
Test status
Simulation time	85222720 ps
CPU time	1.56 seconds
Started	Apr 28 12:51:33 PM PDT 24
Finished	Apr 28 12:51:35 PM PDT 24
Peak memory	200540 kb
Host	smart-f6e3017b-e9fa-44f5-aeac-d5702f9fbfc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365909703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.clkmgr_tl_intg_err.365909703
Directory	/workspace/8.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.286317239
Short name	T973
Test name
Test status
Simulation time	27210745 ps
CPU time	1.01 seconds
Started	Apr 28 12:51:34 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	200464 kb
Host	smart-0658595f-839b-4a82-885d-134201d3c80e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286317239 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.286317239
Directory	/workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.981389809
Short name	T966
Test name
Test status
Simulation time	43809683 ps
CPU time	0.84 seconds
Started	Apr 28 12:51:36 PM PDT 24
Finished	Apr 28 12:51:38 PM PDT 24
Peak memory	200452 kb
Host	smart-67f20d35-3c03-4aad-aeeb-e0dd123152b7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981389809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.c lkmgr_csr_rw.981389809
Directory	/workspace/9.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1258968996
Short name	T994
Test name
Test status
Simulation time	34046107 ps
CPU time	0.71 seconds
Started	Apr 28 12:51:32 PM PDT 24
Finished	Apr 28 12:51:33 PM PDT 24
Peak memory	198804 kb
Host	smart-755e6c3e-9253-484c-8364-9f186fcd02b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258968996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_intr_test.1258968996
Directory	/workspace/9.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1430992024
Short name	T1001
Test name
Test status
Simulation time	22693293 ps
CPU time	0.96 seconds
Started	Apr 28 12:51:35 PM PDT 24
Finished	Apr 28 12:51:37 PM PDT 24
Peak memory	200416 kb
Host	smart-449ef892-16b7-46e1-9275-c60dcab9d979
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430992024 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.clkmgr_same_csr_outstanding.1430992024
Directory	/workspace/9.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.4082226499
Short name	T992
Test name
Test status
Simulation time	159819650 ps
CPU time	2.13 seconds
Started	Apr 28 12:51:33 PM PDT 24
Finished	Apr 28 12:51:36 PM PDT 24
Peak memory	200936 kb
Host	smart-2e37e415-e8da-41a8-811f-c031f3fac8cf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082226499 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.clkmgr_shadow_reg_errors.4082226499
Directory	/workspace/9.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2284910188
Short name	T906
Test name
Test status
Simulation time	36183325 ps
CPU time	2.22 seconds
Started	Apr 28 12:51:35 PM PDT 24
Finished	Apr 28 12:51:38 PM PDT 24
Peak memory	200548 kb
Host	smart-1fb78b14-051d-4d94-b729-d8a9f0b47033
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284910188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_tl_errors.2284910188
Directory	/workspace/9.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.370307197
Short name	T1004
Test name
Test status
Simulation time	189793417 ps
CPU time	2.75 seconds
Started	Apr 28 12:51:30 PM PDT 24
Finished	Apr 28 12:51:34 PM PDT 24
Peak memory	200696 kb
Host	smart-97006310-54df-499d-bee4-7cdd5649812a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370307197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.clkmgr_tl_intg_err.370307197
Directory	/workspace/9.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.2187594226
Short name	T76
Test name
Test status
Simulation time	35434348 ps
CPU time	0.83 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:50 PM PDT 24
Peak memory	200968 kb
Host	smart-efe11ab3-cc37-4b21-87a1-028fb6eac0c7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187594226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.2187594226
Directory	/workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_status.3206129396
Short name	T146
Test name
Test status
Simulation time	46384424 ps
CPU time	0.77 seconds
Started	Apr 28 12:55:51 PM PDT 24
Finished	Apr 28 12:55:53 PM PDT 24
Peak memory	200020 kb
Host	smart-4de148f3-3ddf-45d4-8072-7ddc7804febc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206129396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.3206129396
Directory	/workspace/0.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_div_intersig_mubi.3136033533
Short name	T820
Test name
Test status
Simulation time	99432236 ps
CPU time	1.12 seconds
Started	Apr 28 12:55:55 PM PDT 24
Finished	Apr 28 12:55:57 PM PDT 24
Peak memory	200972 kb
Host	smart-6fb745a6-80cc-4628-aed1-46ec05352729
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136033533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.3136033533
Directory	/workspace/0.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_extclk.2761180150
Short name	T557
Test name
Test status
Simulation time	48818687 ps
CPU time	0.86 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:53 PM PDT 24
Peak memory	200996 kb
Host	smart-3ffda5b2-ffb1-4794-a758-7fd7cbc4a307
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761180150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2761180150
Directory	/workspace/0.clkmgr_extclk/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency.3097269306
Short name	T265
Test name
Test status
Simulation time	804200128 ps
CPU time	6.58 seconds
Started	Apr 28 12:55:51 PM PDT 24
Finished	Apr 28 12:55:59 PM PDT 24
Peak memory	200912 kb
Host	smart-ea7d15a5-7102-49d5-9e81-35af391356bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097269306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3097269306
Directory	/workspace/0.clkmgr_frequency/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency_timeout.1095678784
Short name	T516
Test name
Test status
Simulation time	1005391213 ps
CPU time	4.39 seconds
Started	Apr 28 12:55:48 PM PDT 24
Finished	Apr 28 12:55:53 PM PDT 24
Peak memory	201064 kb
Host	smart-413c08fc-ab5b-4dfe-b593-9244a3a3a49c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095678784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti meout.1095678784
Directory	/workspace/0.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.4006014065
Short name	T658
Test name
Test status
Simulation time	40131757 ps
CPU time	0.9 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	201008 kb
Host	smart-0029c06b-0f92-4c5c-bae4-435d0c6c3202
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006014065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_clk_byp_req_intersig_mubi.4006014065
Directory	/workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.1096746568
Short name	T225
Test name
Test status
Simulation time	295037156 ps
CPU time	1.61 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:53 PM PDT 24
Peak memory	200988 kb
Host	smart-f348c298-9828-4fe5-85b2-0a501ef63c08
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096746568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_ctrl_intersig_mubi.1096746568
Directory	/workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_peri.3162467345
Short name	T325
Test name
Test status
Simulation time	30559747 ps
CPU time	0.75 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:50 PM PDT 24
Peak memory	200996 kb
Host	smart-9a3f0bb6-09e2-4db7-a2a3-a15767a47422
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162467345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.3162467345
Directory	/workspace/0.clkmgr_peri/latest

Test location	/workspace/coverage/default/0.clkmgr_sec_cm.2084835788
Short name	T40
Test name
Test status
Simulation time	219340887 ps
CPU time	1.97 seconds
Started	Apr 28 12:55:50 PM PDT 24
Finished	Apr 28 12:55:53 PM PDT 24
Peak memory	216160 kb
Host	smart-e3860865-5f62-429a-a294-3ec2e635a91b
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084835788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg r_sec_cm.2084835788
Directory	/workspace/0.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/0.clkmgr_smoke.3451773610
Short name	T272
Test name
Test status
Simulation time	23698469 ps
CPU time	0.89 seconds
Started	Apr 28 12:55:51 PM PDT 24
Finished	Apr 28 12:55:53 PM PDT 24
Peak memory	201028 kb
Host	smart-471657b3-741f-4ac3-8599-a4a28c4f33e9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451773610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3451773610
Directory	/workspace/0.clkmgr_smoke/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all.3981704625
Short name	T22
Test name
Test status
Simulation time	990011790 ps
CPU time	4.81 seconds
Started	Apr 28 12:55:51 PM PDT 24
Finished	Apr 28 12:55:57 PM PDT 24
Peak memory	200936 kb
Host	smart-1eee6716-860a-484a-ad5c-51132034c46b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981704625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.3981704625
Directory	/workspace/0.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.1311357887
Short name	T628
Test name
Test status
Simulation time	133472872048 ps
CPU time	736.73 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 01:08:07 PM PDT 24
Peak memory	217864 kb
Host	smart-16293bdc-9f28-47bb-a32d-8a24069efad6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1311357887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.1311357887
Directory	/workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.clkmgr_trans.3716576510
Short name	T800
Test name
Test status
Simulation time	40439982 ps
CPU time	0.96 seconds
Started	Apr 28 12:55:52 PM PDT 24
Finished	Apr 28 12:55:54 PM PDT 24
Peak memory	200892 kb
Host	smart-a772ef7e-453c-4fa3-8ad0-5bb5f1c02808
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716576510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.3716576510
Directory	/workspace/0.clkmgr_trans/latest

Test location	/workspace/coverage/default/1.clkmgr_alert_test.2924333899
Short name	T33
Test name
Test status
Simulation time	15071375 ps
CPU time	0.76 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:57 PM PDT 24
Peak memory	200960 kb
Host	smart-4b4302e0-0cf9-4376-ac0b-90e41b485295
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924333899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm gr_alert_test.2924333899
Directory	/workspace/1.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.477476216
Short name	T79
Test name
Test status
Simulation time	27761561 ps
CPU time	0.92 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:58 PM PDT 24
Peak memory	200968 kb
Host	smart-699e713c-bbce-42e3-a8ea-e1ca6d4cf040
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477476216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.477476216
Directory	/workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_status.3886352147
Short name	T783
Test name
Test status
Simulation time	17434158 ps
CPU time	0.69 seconds
Started	Apr 28 12:55:57 PM PDT 24
Finished	Apr 28 12:55:59 PM PDT 24
Peak memory	200884 kb
Host	smart-a591fd98-c8e2-431d-a0ac-66cefb655941
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886352147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3886352147
Directory	/workspace/1.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/1.clkmgr_div_intersig_mubi.4224400558
Short name	T9
Test name
Test status
Simulation time	47654613 ps
CPU time	0.77 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:57 PM PDT 24
Peak memory	200880 kb
Host	smart-c30279ac-c50a-4ee1-b8a3-78dd0bfdc032
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224400558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.4224400558
Directory	/workspace/1.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_extclk.3853484245
Short name	T171
Test name
Test status
Simulation time	51019626 ps
CPU time	0.97 seconds
Started	Apr 28 12:55:49 PM PDT 24
Finished	Apr 28 12:55:52 PM PDT 24
Peak memory	201008 kb
Host	smart-87638f2b-cbad-4508-9f7d-aaa078718e2d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853484245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3853484245
Directory	/workspace/1.clkmgr_extclk/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency.2698737974
Short name	T467
Test name
Test status
Simulation time	796467192 ps
CPU time	6.34 seconds
Started	Apr 28 12:55:57 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	201012 kb
Host	smart-a6cdae55-10cc-4b46-a417-81db9d74865f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698737974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.2698737974
Directory	/workspace/1.clkmgr_frequency/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency_timeout.3806433235
Short name	T288
Test name
Test status
Simulation time	1828398190 ps
CPU time	8.94 seconds
Started	Apr 28 12:55:57 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	201008 kb
Host	smart-1811801d-0608-4c8e-84ca-87f7f98666d2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806433235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti meout.3806433235
Directory	/workspace/1.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/1.clkmgr_idle_intersig_mubi.2907187311
Short name	T568
Test name
Test status
Simulation time	107710829 ps
CPU time	1.08 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:58 PM PDT 24
Peak memory	200960 kb
Host	smart-1f88bcc7-f0bd-4319-b705-801d9e3b155b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907187311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.2907187311
Directory	/workspace/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3721337461
Short name	T333
Test name
Test status
Simulation time	17532962 ps
CPU time	0.79 seconds
Started	Apr 28 12:55:53 PM PDT 24
Finished	Apr 28 12:55:54 PM PDT 24
Peak memory	200892 kb
Host	smart-07ee1a74-a5ff-4f9f-b11a-e4608771febb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721337461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_clk_byp_req_intersig_mubi.3721337461
Directory	/workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2138250740
Short name	T615
Test name
Test status
Simulation time	72186479 ps
CPU time	1.04 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:58 PM PDT 24
Peak memory	200896 kb
Host	smart-7d0632fe-29f2-4fe8-afa3-a4a41225ade8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138250740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_ctrl_intersig_mubi.2138250740
Directory	/workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_peri.245804668
Short name	T456
Test name
Test status
Simulation time	16441969 ps
CPU time	0.78 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:58 PM PDT 24
Peak memory	200876 kb
Host	smart-0936fe36-7828-43a0-a313-7b6cf6dc1375
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245804668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.245804668
Directory	/workspace/1.clkmgr_peri/latest

Test location	/workspace/coverage/default/1.clkmgr_regwen.3409765168
Short name	T678
Test name
Test status
Simulation time	812844671 ps
CPU time	3.18 seconds
Started	Apr 28 12:55:55 PM PDT 24
Finished	Apr 28 12:55:59 PM PDT 24
Peak memory	201052 kb
Host	smart-89db6571-55bb-4ce9-b725-3292faa4f55c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409765168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3409765168
Directory	/workspace/1.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_sec_cm.2975853376
Short name	T48
Test name
Test status
Simulation time	489944956 ps
CPU time	3.17 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:02 PM PDT 24
Peak memory	216260 kb
Host	smart-bf07ac15-e137-410b-9747-e1e8d12e893c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975853376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg r_sec_cm.2975853376
Directory	/workspace/1.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/1.clkmgr_smoke.4132180715
Short name	T260
Test name
Test status
Simulation time	28991694 ps
CPU time	0.83 seconds
Started	Apr 28 12:55:48 PM PDT 24
Finished	Apr 28 12:55:50 PM PDT 24
Peak memory	200912 kb
Host	smart-eb568162-4f92-4b68-bcd7-af9666a86aad
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132180715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.4132180715
Directory	/workspace/1.clkmgr_smoke/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all.3192277344
Short name	T622
Test name
Test status
Simulation time	3589678537 ps
CPU time	14.34 seconds
Started	Apr 28 12:55:57 PM PDT 24
Finished	Apr 28 12:56:12 PM PDT 24
Peak memory	201272 kb
Host	smart-2ea4073d-f993-4875-85e7-a2fba12960da
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192277344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.3192277344
Directory	/workspace/1.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.1528494634
Short name	T357
Test name
Test status
Simulation time	176355737882 ps
CPU time	1046.89 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 01:13:24 PM PDT 24
Peak memory	217876 kb
Host	smart-18327f2a-1708-48ea-9c51-ca42b0e247cd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1528494634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.1528494634
Directory	/workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.clkmgr_trans.3677494266
Short name	T607
Test name
Test status
Simulation time	101195667 ps
CPU time	1.14 seconds
Started	Apr 28 12:55:55 PM PDT 24
Finished	Apr 28 12:55:56 PM PDT 24
Peak memory	200984 kb
Host	smart-b78856e4-cc27-45f9-9aa2-6eee8164d1d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677494266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3677494266
Directory	/workspace/1.clkmgr_trans/latest

Test location	/workspace/coverage/default/10.clkmgr_alert_test.1364393092
Short name	T517
Test name
Test status
Simulation time	44042504 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	201068 kb
Host	smart-35f65036-3ff4-497b-a10c-392b10af187e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364393092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk mgr_alert_test.1364393092
Directory	/workspace/10.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2083676885
Short name	T761
Test name
Test status
Simulation time	79406696 ps
CPU time	0.99 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	200968 kb
Host	smart-f00e46b8-8f28-41b6-aeb3-ae2a32ad1176
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083676885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.2083676885
Directory	/workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_status.3637251056
Short name	T691
Test name
Test status
Simulation time	32343109 ps
CPU time	0.73 seconds
Started	Apr 28 12:56:09 PM PDT 24
Finished	Apr 28 12:56:11 PM PDT 24
Peak memory	199820 kb
Host	smart-b8e591a5-4f0e-4cb7-94a1-c56fcdaa5574
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637251056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3637251056
Directory	/workspace/10.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/10.clkmgr_div_intersig_mubi.745773211
Short name	T803
Test name
Test status
Simulation time	190436828 ps
CPU time	1.35 seconds
Started	Apr 28 12:56:11 PM PDT 24
Finished	Apr 28 12:56:13 PM PDT 24
Peak memory	200904 kb
Host	smart-7a87ec4a-de00-44d5-88a8-890f711d25e1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745773211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.clkmgr_div_intersig_mubi.745773211
Directory	/workspace/10.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_extclk.1098655169
Short name	T483
Test name
Test status
Simulation time	27498498 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:14 PM PDT 24
Peak memory	200880 kb
Host	smart-638dc76c-f556-4216-8a09-bc053184b2c5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098655169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1098655169
Directory	/workspace/10.clkmgr_extclk/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency.4203582515
Short name	T436
Test name
Test status
Simulation time	928351536 ps
CPU time	5.52 seconds
Started	Apr 28 12:56:12 PM PDT 24
Finished	Apr 28 12:56:19 PM PDT 24
Peak memory	201068 kb
Host	smart-79153822-f02a-4ae3-affd-69777843d565
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203582515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.4203582515
Directory	/workspace/10.clkmgr_frequency/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency_timeout.1845158680
Short name	T300
Test name
Test status
Simulation time	1817907341 ps
CPU time	12.33 seconds
Started	Apr 28 12:56:12 PM PDT 24
Finished	Apr 28 12:56:25 PM PDT 24
Peak memory	201112 kb
Host	smart-7f5b7d43-0471-46be-9ad5-171e8e80ee0e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845158680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t imeout.1845158680
Directory	/workspace/10.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/10.clkmgr_idle_intersig_mubi.3410929717
Short name	T695
Test name
Test status
Simulation time	28749674 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:15 PM PDT 24
Peak memory	200876 kb
Host	smart-2fd95319-7a8e-4164-b7a7-c4fb60199142
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410929717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.3410929717
Directory	/workspace/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1201615124
Short name	T631
Test name
Test status
Simulation time	217168248 ps
CPU time	1.34 seconds
Started	Apr 28 12:56:11 PM PDT 24
Finished	Apr 28 12:56:13 PM PDT 24
Peak memory	200872 kb
Host	smart-97060dde-5b84-4a77-b04e-a6a669ca4623
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201615124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_clk_byp_req_intersig_mubi.1201615124
Directory	/workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.3601774056
Short name	T463
Test name
Test status
Simulation time	38107694 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:09 PM PDT 24
Finished	Apr 28 12:56:11 PM PDT 24
Peak memory	201008 kb
Host	smart-6ba97f14-274e-425e-b508-0d38c6376e73
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601774056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_ctrl_intersig_mubi.3601774056
Directory	/workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_peri.408658626
Short name	T174
Test name
Test status
Simulation time	16796424 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:09 PM PDT 24
Finished	Apr 28 12:56:11 PM PDT 24
Peak memory	200956 kb
Host	smart-52797579-b912-49ec-bc72-030db21125ed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408658626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.408658626
Directory	/workspace/10.clkmgr_peri/latest

Test location	/workspace/coverage/default/10.clkmgr_regwen.2973786697
Short name	T132
Test name
Test status
Simulation time	387257884 ps
CPU time	2.65 seconds
Started	Apr 28 12:56:09 PM PDT 24
Finished	Apr 28 12:56:12 PM PDT 24
Peak memory	200876 kb
Host	smart-62bd2c72-aecc-4b09-9dca-90434479fb55
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973786697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2973786697
Directory	/workspace/10.clkmgr_regwen/latest

Test location	/workspace/coverage/default/10.clkmgr_smoke.750736880
Short name	T299
Test name
Test status
Simulation time	19654537 ps
CPU time	0.88 seconds
Started	Apr 28 12:56:11 PM PDT 24
Finished	Apr 28 12:56:12 PM PDT 24
Peak memory	200956 kb
Host	smart-a03a2862-b2bd-4e22-956b-d83d39d9ed1a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750736880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.750736880
Directory	/workspace/10.clkmgr_smoke/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all.3469293334
Short name	T847
Test name
Test status
Simulation time	2856364245 ps
CPU time	21.8 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:37 PM PDT 24
Peak memory	201480 kb
Host	smart-65df1cb9-52f3-4324-a3a9-3a6dabc0ec05
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469293334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.3469293334
Directory	/workspace/10.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.4184185661
Short name	T374
Test name
Test status
Simulation time	30956942952 ps
CPU time	202.95 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 12:59:32 PM PDT 24
Peak memory	209720 kb
Host	smart-64b2e3ac-1533-4194-a117-73d60ae581e5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4184185661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.4184185661
Directory	/workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.clkmgr_trans.2110885635
Short name	T358
Test name
Test status
Simulation time	51673630 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:09 PM PDT 24
Finished	Apr 28 12:56:11 PM PDT 24
Peak memory	200996 kb
Host	smart-365926c9-ba27-45a9-b2c8-682316bffcb0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110885635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2110885635
Directory	/workspace/10.clkmgr_trans/latest

Test location	/workspace/coverage/default/11.clkmgr_alert_test.2927168748
Short name	T624
Test name
Test status
Simulation time	14842481 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:22 PM PDT 24
Finished	Apr 28 12:56:23 PM PDT 24
Peak memory	201036 kb
Host	smart-03fa2c23-7b69-4432-9cb0-c233f883a958
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927168748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk mgr_alert_test.2927168748
Directory	/workspace/11.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_status.786926752
Short name	T814
Test name
Test status
Simulation time	19738657 ps
CPU time	0.69 seconds
Started	Apr 28 12:56:18 PM PDT 24
Finished	Apr 28 12:56:19 PM PDT 24
Peak memory	199896 kb
Host	smart-111b34c9-e12e-482e-b297-2e8280cbefd3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786926752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.786926752
Directory	/workspace/11.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/11.clkmgr_div_intersig_mubi.3948577891
Short name	T387
Test name
Test status
Simulation time	57097840 ps
CPU time	0.96 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	200840 kb
Host	smart-3d27e82e-0a5d-4f9e-8b52-cd0788434227
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948577891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.3948577891
Directory	/workspace/11.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_extclk.1588301471
Short name	T130
Test name
Test status
Simulation time	59442426 ps
CPU time	0.93 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	201040 kb
Host	smart-54edbad8-534e-4ca3-abae-118f8defcc5f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588301471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.1588301471
Directory	/workspace/11.clkmgr_extclk/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency.2612046465
Short name	T244
Test name
Test status
Simulation time	2152468860 ps
CPU time	9.79 seconds
Started	Apr 28 12:56:15 PM PDT 24
Finished	Apr 28 12:56:26 PM PDT 24
Peak memory	201244 kb
Host	smart-1fdf8dbb-db17-42f5-ae62-68f202f00259
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612046465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.2612046465
Directory	/workspace/11.clkmgr_frequency/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency_timeout.992255139
Short name	T455
Test name
Test status
Simulation time	1580737689 ps
CPU time	11.41 seconds
Started	Apr 28 12:56:22 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	201116 kb
Host	smart-25b80c8e-0f3f-4a52-ba4e-fe24a821fcc4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992255139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_ti meout.992255139
Directory	/workspace/11.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/11.clkmgr_idle_intersig_mubi.3430500849
Short name	T479
Test name
Test status
Simulation time	219100814 ps
CPU time	1.36 seconds
Started	Apr 28 12:56:16 PM PDT 24
Finished	Apr 28 12:56:18 PM PDT 24
Peak memory	200800 kb
Host	smart-3e8a5716-0cfa-4bdf-afa0-e7fb9faef44d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430500849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.3430500849
Directory	/workspace/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.4067497291
Short name	T287
Test name
Test status
Simulation time	28464380 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:15 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	200988 kb
Host	smart-8096e0d5-6c63-44bf-b8d4-0aa18f7e682d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067497291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_clk_byp_req_intersig_mubi.4067497291
Directory	/workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.629294398
Short name	T804
Test name
Test status
Simulation time	82402470 ps
CPU time	1.02 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:15 PM PDT 24
Peak memory	201012 kb
Host	smart-4d3083c0-5033-4e15-bfa5-8889cfbd88b5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629294398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.clkmgr_lc_ctrl_intersig_mubi.629294398
Directory	/workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_peri.1882839010
Short name	T390
Test name
Test status
Simulation time	52023904 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:15 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	200988 kb
Host	smart-bb88a134-5e2d-4357-8deb-bc7941b1de1d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882839010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.1882839010
Directory	/workspace/11.clkmgr_peri/latest

Test location	/workspace/coverage/default/11.clkmgr_regwen.1452734312
Short name	T133
Test name
Test status
Simulation time	526309432 ps
CPU time	3.36 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:18 PM PDT 24
Peak memory	200888 kb
Host	smart-d318f7fc-9afc-4bbb-8517-fda2bf4273cc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452734312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1452734312
Directory	/workspace/11.clkmgr_regwen/latest

Test location	/workspace/coverage/default/11.clkmgr_smoke.3648867614
Short name	T506
Test name
Test status
Simulation time	19850232 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	201076 kb
Host	smart-cc6b766a-0585-4477-a7f8-95669c1d8011
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648867614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.3648867614
Directory	/workspace/11.clkmgr_smoke/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all.469404246
Short name	T521
Test name
Test status
Simulation time	2182653606 ps
CPU time	8.69 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:24 PM PDT 24
Peak memory	201416 kb
Host	smart-8863ef20-daa9-4ed2-a556-3f510adb56ff
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469404246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.469404246
Directory	/workspace/11.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.3380502650
Short name	T34
Test name
Test status
Simulation time	79700053481 ps
CPU time	708.67 seconds
Started	Apr 28 12:56:17 PM PDT 24
Finished	Apr 28 01:08:06 PM PDT 24
Peak memory	212892 kb
Host	smart-8cb440c5-4490-4c6c-9f9f-3432ea92cd92
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3380502650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3380502650
Directory	/workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.clkmgr_trans.525029599
Short name	T496
Test name
Test status
Simulation time	41960285 ps
CPU time	1.07 seconds
Started	Apr 28 12:56:16 PM PDT 24
Finished	Apr 28 12:56:18 PM PDT 24
Peak memory	200992 kb
Host	smart-266331f2-70ce-4ad9-81ed-f3b507bd7a6c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525029599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.525029599
Directory	/workspace/11.clkmgr_trans/latest

Test location	/workspace/coverage/default/12.clkmgr_alert_test.3667008139
Short name	T828
Test name
Test status
Simulation time	18666951 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:18 PM PDT 24
Finished	Apr 28 12:56:20 PM PDT 24
Peak memory	201056 kb
Host	smart-748d36a5-dd14-48a3-9630-b15b10169acf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667008139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk mgr_alert_test.3667008139
Directory	/workspace/12.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3768566510
Short name	T850
Test name
Test status
Simulation time	17204452 ps
CPU time	0.81 seconds
Started	Apr 28 12:56:19 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	200972 kb
Host	smart-8ef97bf9-6757-4a9c-81ed-bb7149c8d6ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768566510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.3768566510
Directory	/workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_status.668081285
Short name	T494
Test name
Test status
Simulation time	33851075 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	200020 kb
Host	smart-57d98501-3aa1-488d-8e0a-0d3b1bf07737
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668081285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.668081285
Directory	/workspace/12.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/12.clkmgr_div_intersig_mubi.899241968
Short name	T559
Test name
Test status
Simulation time	41725715 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:20 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	200896 kb
Host	smart-caea5ed1-c229-4a6f-9dee-5e6be62af83e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899241968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.clkmgr_div_intersig_mubi.899241968
Directory	/workspace/12.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency.3863122415
Short name	T12
Test name
Test status
Simulation time	1554660476 ps
CPU time	6.07 seconds
Started	Apr 28 12:56:15 PM PDT 24
Finished	Apr 28 12:56:22 PM PDT 24
Peak memory	201024 kb
Host	smart-1c95e543-be59-4122-8bc4-e91b36cae44f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863122415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3863122415
Directory	/workspace/12.clkmgr_frequency/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency_timeout.3286544834
Short name	T619
Test name
Test status
Simulation time	1945569940 ps
CPU time	10.02 seconds
Started	Apr 28 12:56:16 PM PDT 24
Finished	Apr 28 12:56:27 PM PDT 24
Peak memory	201112 kb
Host	smart-6b1758c7-4060-46e4-854f-4c38a0b3b3c4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286544834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t imeout.3286544834
Directory	/workspace/12.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/12.clkmgr_idle_intersig_mubi.4003831695
Short name	T380
Test name
Test status
Simulation time	40225321 ps
CPU time	0.88 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	200828 kb
Host	smart-d45e1e83-c35a-4e83-9b5e-2c7ba2f34d6f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003831695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.4003831695
Directory	/workspace/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.3158362024
Short name	T344
Test name
Test status
Simulation time	59917797 ps
CPU time	0.85 seconds
Started	Apr 28 12:56:16 PM PDT 24
Finished	Apr 28 12:56:18 PM PDT 24
Peak memory	200952 kb
Host	smart-b7141568-d74a-4545-bf7b-919fcbd5922e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158362024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_clk_byp_req_intersig_mubi.3158362024
Directory	/workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1036407542
Short name	T825
Test name
Test status
Simulation time	19023618 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	200920 kb
Host	smart-eab88e50-719f-4b25-99a6-c0c2ec509157
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036407542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_ctrl_intersig_mubi.1036407542
Directory	/workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_peri.2734285569
Short name	T439
Test name
Test status
Simulation time	25356096 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:16 PM PDT 24
Finished	Apr 28 12:56:18 PM PDT 24
Peak memory	200820 kb
Host	smart-5fe53f56-7b8b-4265-ab76-8cc486179c14
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734285569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2734285569
Directory	/workspace/12.clkmgr_peri/latest

Test location	/workspace/coverage/default/12.clkmgr_smoke.2472809192
Short name	T338
Test name
Test status
Simulation time	77644542 ps
CPU time	1.01 seconds
Started	Apr 28 12:56:15 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	201056 kb
Host	smart-2c4f03b2-8af5-4f5f-9084-44622cd2abc7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472809192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2472809192
Directory	/workspace/12.clkmgr_smoke/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all.2392606153
Short name	T457
Test name
Test status
Simulation time	7982345041 ps
CPU time	24.72 seconds
Started	Apr 28 12:56:23 PM PDT 24
Finished	Apr 28 12:56:48 PM PDT 24
Peak memory	201292 kb
Host	smart-55200b8d-e3c8-4c02-b7a8-cc395e6dd834
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392606153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.2392606153
Directory	/workspace/12.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.1449409546
Short name	T157
Test name
Test status
Simulation time	68885730573 ps
CPU time	446.9 seconds
Started	Apr 28 12:56:24 PM PDT 24
Finished	Apr 28 01:03:53 PM PDT 24
Peak memory	211056 kb
Host	smart-f2ecd175-0340-4166-a1a2-fb13eccc2cf3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1449409546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.1449409546
Directory	/workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.clkmgr_trans.2694811747
Short name	T389
Test name
Test status
Simulation time	114474481 ps
CPU time	1.12 seconds
Started	Apr 28 12:56:22 PM PDT 24
Finished	Apr 28 12:56:24 PM PDT 24
Peak memory	200984 kb
Host	smart-c6cb48c9-9f32-426d-b691-f0f1853a995f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694811747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2694811747
Directory	/workspace/12.clkmgr_trans/latest

Test location	/workspace/coverage/default/13.clkmgr_alert_test.3290858375
Short name	T781
Test name
Test status
Simulation time	16645448 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:20 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	201064 kb
Host	smart-13e4bfbe-394d-4f47-9b6b-394968aaea6b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290858375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk mgr_alert_test.3290858375
Directory	/workspace/13.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2159057654
Short name	T440
Test name
Test status
Simulation time	17900577 ps
CPU time	0.81 seconds
Started	Apr 28 12:56:19 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	200884 kb
Host	smart-6b88bc41-6154-4a00-8a26-d74152ebf50d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159057654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.2159057654
Directory	/workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_status.1393764172
Short name	T710
Test name
Test status
Simulation time	85739689 ps
CPU time	0.86 seconds
Started	Apr 28 12:56:25 PM PDT 24
Finished	Apr 28 12:56:28 PM PDT 24
Peak memory	199900 kb
Host	smart-459f743c-6fce-4d15-ae54-4d54edb3cf9a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393764172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.1393764172
Directory	/workspace/13.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/13.clkmgr_div_intersig_mubi.16552867
Short name	T849
Test name
Test status
Simulation time	49419787 ps
CPU time	0.98 seconds
Started	Apr 28 12:56:22 PM PDT 24
Finished	Apr 28 12:56:24 PM PDT 24
Peak memory	200992 kb
Host	smart-f049936e-44a0-49f5-af99-351a9955f31e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16552867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13 .clkmgr_div_intersig_mubi.16552867
Directory	/workspace/13.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_extclk.4112680633
Short name	T489
Test name
Test status
Simulation time	32499108 ps
CPU time	0.81 seconds
Started	Apr 28 12:56:19 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	200996 kb
Host	smart-79757812-f01b-4b45-850e-ade38f7d5e80
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112680633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.4112680633
Directory	/workspace/13.clkmgr_extclk/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency.1680034603
Short name	T460
Test name
Test status
Simulation time	940425682 ps
CPU time	4.43 seconds
Started	Apr 28 12:56:19 PM PDT 24
Finished	Apr 28 12:56:25 PM PDT 24
Peak memory	200964 kb
Host	smart-1194ab15-4a6f-4f5f-b0aa-3768a9735a7c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680034603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.1680034603
Directory	/workspace/13.clkmgr_frequency/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency_timeout.2120513908
Short name	T852
Test name
Test status
Simulation time	408410461 ps
CPU time	2.03 seconds
Started	Apr 28 12:56:29 PM PDT 24
Finished	Apr 28 12:56:33 PM PDT 24
Peak memory	200996 kb
Host	smart-b90c0cb8-6d75-4ac4-bb3e-b652851f0cf1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120513908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t imeout.2120513908
Directory	/workspace/13.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.489963623
Short name	T201
Test name
Test status
Simulation time	322048965 ps
CPU time	1.73 seconds
Started	Apr 28 12:56:19 PM PDT 24
Finished	Apr 28 12:56:22 PM PDT 24
Peak memory	200840 kb
Host	smart-9045d37b-714b-4b5a-b281-66fdc2608ec6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489963623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.clkmgr_idle_intersig_mubi.489963623
Directory	/workspace/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2654265257
Short name	T367
Test name
Test status
Simulation time	80394905 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:17 PM PDT 24
Finished	Apr 28 12:56:18 PM PDT 24
Peak memory	200932 kb
Host	smart-534753fd-d0fe-4a59-8752-a8553541be3f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654265257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_clk_byp_req_intersig_mubi.2654265257
Directory	/workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1788968177
Short name	T343
Test name
Test status
Simulation time	88617038 ps
CPU time	0.98 seconds
Started	Apr 28 12:56:23 PM PDT 24
Finished	Apr 28 12:56:24 PM PDT 24
Peak memory	200868 kb
Host	smart-928205a8-d4ed-4064-9a18-eb98a675bbbc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788968177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_ctrl_intersig_mubi.1788968177
Directory	/workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_peri.496599628
Short name	T401
Test name
Test status
Simulation time	15962186 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:19 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	200960 kb
Host	smart-735095f1-76a9-4bee-bd80-a49ebd29ab26
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496599628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.496599628
Directory	/workspace/13.clkmgr_peri/latest

Test location	/workspace/coverage/default/13.clkmgr_regwen.1669719157
Short name	T575
Test name
Test status
Simulation time	1151954176 ps
CPU time	6.69 seconds
Started	Apr 28 12:56:20 PM PDT 24
Finished	Apr 28 12:56:28 PM PDT 24
Peak memory	200996 kb
Host	smart-8c1ecbfb-fcfe-4fa4-a21f-18496ce48bca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669719157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1669719157
Directory	/workspace/13.clkmgr_regwen/latest

Test location	/workspace/coverage/default/13.clkmgr_smoke.2972699680
Short name	T303
Test name
Test status
Simulation time	45027552 ps
CPU time	0.9 seconds
Started	Apr 28 12:56:24 PM PDT 24
Finished	Apr 28 12:56:27 PM PDT 24
Peak memory	200960 kb
Host	smart-01f992ab-c0d4-4546-8e06-553738cca09d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972699680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2972699680
Directory	/workspace/13.clkmgr_smoke/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.2623340067
Short name	T14
Test name
Test status
Simulation time	50658287122 ps
CPU time	541.4 seconds
Started	Apr 28 12:56:25 PM PDT 24
Finished	Apr 28 01:05:28 PM PDT 24
Peak memory	217876 kb
Host	smart-99a3ed51-468e-4d99-b2d6-a0a4b210f539
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2623340067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.2623340067
Directory	/workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.clkmgr_trans.2320162490
Short name	T264
Test name
Test status
Simulation time	69017898 ps
CPU time	1.1 seconds
Started	Apr 28 12:56:30 PM PDT 24
Finished	Apr 28 12:56:32 PM PDT 24
Peak memory	200896 kb
Host	smart-35bdc4dd-4073-4ceb-a9b8-55ef9b0a894f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320162490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2320162490
Directory	/workspace/13.clkmgr_trans/latest

Test location	/workspace/coverage/default/14.clkmgr_alert_test.64234453
Short name	T807
Test name
Test status
Simulation time	134045328 ps
CPU time	1.12 seconds
Started	Apr 28 12:56:29 PM PDT 24
Finished	Apr 28 12:56:32 PM PDT 24
Peak memory	201076 kb
Host	smart-adb6200f-6c6d-4c70-a241-47743297dc48
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64234453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmg r_alert_test.64234453
Directory	/workspace/14.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3549572371
Short name	T224
Test name
Test status
Simulation time	28501679 ps
CPU time	0.88 seconds
Started	Apr 28 12:56:18 PM PDT 24
Finished	Apr 28 12:56:19 PM PDT 24
Peak memory	200984 kb
Host	smart-9bc113aa-11b3-4829-ad54-3ad06e4943f6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549572371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.3549572371
Directory	/workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_status.114936572
Short name	T717
Test name
Test status
Simulation time	17249858 ps
CPU time	0.7 seconds
Started	Apr 28 12:56:20 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	199892 kb
Host	smart-44b72d9e-158a-4c1f-9b9b-191edd06402a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114936572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.114936572
Directory	/workspace/14.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/14.clkmgr_div_intersig_mubi.3391428887
Short name	T722
Test name
Test status
Simulation time	213802322 ps
CPU time	1.42 seconds
Started	Apr 28 12:56:25 PM PDT 24
Finished	Apr 28 12:56:28 PM PDT 24
Peak memory	200844 kb
Host	smart-98dfe1b6-8526-4814-a9ac-6b682b9e41e0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391428887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.3391428887
Directory	/workspace/14.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_extclk.3323973481
Short name	T241
Test name
Test status
Simulation time	32314472 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:27 PM PDT 24
Finished	Apr 28 12:56:29 PM PDT 24
Peak memory	200896 kb
Host	smart-897c3676-54e4-4f18-b182-73012bcd641d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323973481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3323973481
Directory	/workspace/14.clkmgr_extclk/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency.575908427
Short name	T562
Test name
Test status
Simulation time	2472407700 ps
CPU time	10.29 seconds
Started	Apr 28 12:56:29 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	201144 kb
Host	smart-a851cfd2-83e5-4d85-af29-564dd0e8a66c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575908427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.575908427
Directory	/workspace/14.clkmgr_frequency/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency_timeout.1094012182
Short name	T6
Test name
Test status
Simulation time	876697412 ps
CPU time	3.86 seconds
Started	Apr 28 12:56:19 PM PDT 24
Finished	Apr 28 12:56:24 PM PDT 24
Peak memory	200936 kb
Host	smart-973084cc-9cb9-42a6-a0ca-663a462a2f21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094012182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t imeout.1094012182
Directory	/workspace/14.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/14.clkmgr_idle_intersig_mubi.1351436645
Short name	T495
Test name
Test status
Simulation time	71946377 ps
CPU time	0.99 seconds
Started	Apr 28 12:56:22 PM PDT 24
Finished	Apr 28 12:56:23 PM PDT 24
Peak memory	200984 kb
Host	smart-352c8584-dcbd-4e47-addb-4cd37faff585
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351436645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.1351436645
Directory	/workspace/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.47671874
Short name	T630
Test name
Test status
Simulation time	17578063 ps
CPU time	0.73 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:31 PM PDT 24
Peak memory	200884 kb
Host	smart-1664954f-7e2f-483c-920e-591682503d16
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47671874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.47671874
Directory	/workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.1611903816
Short name	T312
Test name
Test status
Simulation time	27253628 ps
CPU time	0.89 seconds
Started	Apr 28 12:56:18 PM PDT 24
Finished	Apr 28 12:56:20 PM PDT 24
Peak memory	200820 kb
Host	smart-c69e2f8e-3061-4cd8-88fe-47abeb840679
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611903816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_ctrl_intersig_mubi.1611903816
Directory	/workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_peri.2602116426
Short name	T366
Test name
Test status
Simulation time	40752391 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:22 PM PDT 24
Finished	Apr 28 12:56:24 PM PDT 24
Peak memory	200976 kb
Host	smart-14455735-68cc-487f-9e6a-ffada9e1b3e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602116426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2602116426
Directory	/workspace/14.clkmgr_peri/latest

Test location	/workspace/coverage/default/14.clkmgr_regwen.2985059111
Short name	T159
Test name
Test status
Simulation time	811982943 ps
CPU time	3.26 seconds
Started	Apr 28 12:56:29 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	201040 kb
Host	smart-7291e109-0288-4f48-ad32-950974b90745
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985059111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2985059111
Directory	/workspace/14.clkmgr_regwen/latest

Test location	/workspace/coverage/default/14.clkmgr_smoke.3470993307
Short name	T826
Test name
Test status
Simulation time	110960135 ps
CPU time	1.07 seconds
Started	Apr 28 12:56:19 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	200912 kb
Host	smart-b774057a-3ad6-4008-9656-cb41b8d50923
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470993307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.3470993307
Directory	/workspace/14.clkmgr_smoke/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all.2269995523
Short name	T67
Test name
Test status
Simulation time	1732180587 ps
CPU time	6.91 seconds
Started	Apr 28 12:56:26 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	201352 kb
Host	smart-664366d3-f116-4182-bdc6-222cdfc5f7bf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269995523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.2269995523
Directory	/workspace/14.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.391198861
Short name	T140
Test name
Test status
Simulation time	79152629207 ps
CPU time	672.16 seconds
Started	Apr 28 12:56:30 PM PDT 24
Finished	Apr 28 01:07:43 PM PDT 24
Peak memory	209564 kb
Host	smart-22a7615e-3d00-43f4-bd7c-df512d561a7e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=391198861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.391198861
Directory	/workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.clkmgr_trans.3862624465
Short name	T654
Test name
Test status
Simulation time	33555906 ps
CPU time	0.84 seconds
Started	Apr 28 12:56:23 PM PDT 24
Finished	Apr 28 12:56:25 PM PDT 24
Peak memory	200952 kb
Host	smart-65a4fc42-ab9f-4085-a97d-022af19de335
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862624465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3862624465
Directory	/workspace/14.clkmgr_trans/latest

Test location	/workspace/coverage/default/15.clkmgr_alert_test.3405371760
Short name	T665
Test name
Test status
Simulation time	17200627 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:32 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	200960 kb
Host	smart-e52b5b21-c987-4e0c-9add-05e12663c17f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405371760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk mgr_alert_test.3405371760
Directory	/workspace/15.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.3615235893
Short name	T324
Test name
Test status
Simulation time	17240646 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:27 PM PDT 24
Finished	Apr 28 12:56:29 PM PDT 24
Peak memory	200888 kb
Host	smart-b4fa0110-7c1e-4030-90b7-0fd815bd3c1e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615235893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.3615235893
Directory	/workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_div_intersig_mubi.178965303
Short name	T432
Test name
Test status
Simulation time	18378529 ps
CPU time	0.76 seconds
Started	Apr 28 12:56:27 PM PDT 24
Finished	Apr 28 12:56:29 PM PDT 24
Peak memory	201008 kb
Host	smart-84a32fe5-fc01-40fc-aae8-f9debdb95d78
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178965303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.clkmgr_div_intersig_mubi.178965303
Directory	/workspace/15.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_extclk.1408816575
Short name	T833
Test name
Test status
Simulation time	21438604 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:29 PM PDT 24
Finished	Apr 28 12:56:31 PM PDT 24
Peak memory	200880 kb
Host	smart-f2092d89-0792-4eef-a2a2-81a7137e31b4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408816575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.1408816575
Directory	/workspace/15.clkmgr_extclk/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency.3241012524
Short name	T700
Test name
Test status
Simulation time	1161005421 ps
CPU time	6.74 seconds
Started	Apr 28 12:56:31 PM PDT 24
Finished	Apr 28 12:56:38 PM PDT 24
Peak memory	201024 kb
Host	smart-1939725d-9a19-4737-a255-ca0be9d145a0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241012524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.3241012524
Directory	/workspace/15.clkmgr_frequency/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency_timeout.1019786068
Short name	T376
Test name
Test status
Simulation time	2088004778 ps
CPU time	8.39 seconds
Started	Apr 28 12:56:26 PM PDT 24
Finished	Apr 28 12:56:36 PM PDT 24
Peak memory	201252 kb
Host	smart-c66c9bb9-ebae-4c7f-885c-e094f1fccd80
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019786068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t imeout.1019786068
Directory	/workspace/15.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1225403821
Short name	T617
Test name
Test status
Simulation time	14662494 ps
CPU time	0.73 seconds
Started	Apr 28 12:56:27 PM PDT 24
Finished	Apr 28 12:56:30 PM PDT 24
Peak memory	200804 kb
Host	smart-5b30c245-97e0-4d2b-9c03-237499f0d265
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225403821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.1225403821
Directory	/workspace/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3124452624
Short name	T480
Test name
Test status
Simulation time	18616220 ps
CPU time	0.86 seconds
Started	Apr 28 12:56:29 PM PDT 24
Finished	Apr 28 12:56:32 PM PDT 24
Peak memory	201004 kb
Host	smart-57535441-8562-4604-ac89-17b072ff5eb4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124452624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_clk_byp_req_intersig_mubi.3124452624
Directory	/workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.2080910117
Short name	T278
Test name
Test status
Simulation time	40582274 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:32 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	200896 kb
Host	smart-8d2dfbb4-7455-4e66-90d8-4dc4d17f90fb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080910117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_ctrl_intersig_mubi.2080910117
Directory	/workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_peri.653587322
Short name	T724
Test name
Test status
Simulation time	47681778 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:25 PM PDT 24
Finished	Apr 28 12:56:27 PM PDT 24
Peak memory	200856 kb
Host	smart-153aaf69-e65f-4fa9-b78f-b7f3a8dd04d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653587322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.653587322
Directory	/workspace/15.clkmgr_peri/latest

Test location	/workspace/coverage/default/15.clkmgr_regwen.142550435
Short name	T361
Test name
Test status
Simulation time	1221741504 ps
CPU time	5.3 seconds
Started	Apr 28 12:56:31 PM PDT 24
Finished	Apr 28 12:56:37 PM PDT 24
Peak memory	201052 kb
Host	smart-c99569bd-0c66-4bdf-93f3-ee03f3deaf08
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142550435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.142550435
Directory	/workspace/15.clkmgr_regwen/latest

Test location	/workspace/coverage/default/15.clkmgr_smoke.685189412
Short name	T795
Test name
Test status
Simulation time	44470674 ps
CPU time	0.93 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:31 PM PDT 24
Peak memory	201012 kb
Host	smart-3339c613-ac69-4578-9f2a-69fdc6123581
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685189412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.685189412
Directory	/workspace/15.clkmgr_smoke/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all.464408235
Short name	T430
Test name
Test status
Simulation time	10549210108 ps
CPU time	40.92 seconds
Started	Apr 28 12:56:26 PM PDT 24
Finished	Apr 28 12:57:09 PM PDT 24
Peak memory	201444 kb
Host	smart-88cadecb-baee-4678-853d-7370ab9f12b2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464408235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.464408235
Directory	/workspace/15.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.1087909272
Short name	T846
Test name
Test status
Simulation time	168525079884 ps
CPU time	930.53 seconds
Started	Apr 28 12:56:24 PM PDT 24
Finished	Apr 28 01:11:55 PM PDT 24
Peak memory	209572 kb
Host	smart-fe8e292c-769a-48b8-9af4-0be62bfaece5
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1087909272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.1087909272
Directory	/workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.clkmgr_trans.1504618441
Short name	T254
Test name
Test status
Simulation time	319323933 ps
CPU time	1.56 seconds
Started	Apr 28 12:56:26 PM PDT 24
Finished	Apr 28 12:56:29 PM PDT 24
Peak memory	200804 kb
Host	smart-99955f9b-2e21-41a9-90ba-ad7936851967
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504618441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.1504618441
Directory	/workspace/15.clkmgr_trans/latest

Test location	/workspace/coverage/default/16.clkmgr_alert_test.2866687062
Short name	T667
Test name
Test status
Simulation time	43409304 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:30 PM PDT 24
Finished	Apr 28 12:56:32 PM PDT 24
Peak memory	200880 kb
Host	smart-b485150a-5c8b-470c-8ae5-357f55426b29
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866687062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk mgr_alert_test.2866687062
Directory	/workspace/16.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3279538670
Short name	T740
Test name
Test status
Simulation time	36109649 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:33 PM PDT 24
Finished	Apr 28 12:56:35 PM PDT 24
Peak memory	200868 kb
Host	smart-db713dc4-9e3d-425b-8bd7-e9a86601ad20
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279538670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.3279538670
Directory	/workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_status.593487982
Short name	T145
Test name
Test status
Simulation time	39870797 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:31 PM PDT 24
Peak memory	200020 kb
Host	smart-c7e38f00-3803-4d83-b9a1-319db791b170
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593487982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.593487982
Directory	/workspace/16.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/16.clkmgr_div_intersig_mubi.3740480663
Short name	T163
Test name
Test status
Simulation time	155113911 ps
CPU time	1.25 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:31 PM PDT 24
Peak memory	200844 kb
Host	smart-a3e7cbb2-e8f3-4a96-b338-af10a8d866b2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740480663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.3740480663
Directory	/workspace/16.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_extclk.2526257490
Short name	T20
Test name
Test status
Simulation time	85008373 ps
CPU time	1.05 seconds
Started	Apr 28 12:56:27 PM PDT 24
Finished	Apr 28 12:56:30 PM PDT 24
Peak memory	200836 kb
Host	smart-689ea507-d0e4-401f-ad4b-f867fb8c9976
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526257490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2526257490
Directory	/workspace/16.clkmgr_extclk/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency.3549733295
Short name	T539
Test name
Test status
Simulation time	1641490886 ps
CPU time	12.9 seconds
Started	Apr 28 12:56:25 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	200932 kb
Host	smart-110bbc99-bfed-4d37-9a3d-12414ce57aae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549733295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.3549733295
Directory	/workspace/16.clkmgr_frequency/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency_timeout.1973587561
Short name	T655
Test name
Test status
Simulation time	1591417572 ps
CPU time	6.65 seconds
Started	Apr 28 12:56:24 PM PDT 24
Finished	Apr 28 12:56:32 PM PDT 24
Peak memory	201092 kb
Host	smart-68aa0036-a0b6-460b-8e64-c8a2cd002f05
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973587561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t imeout.1973587561
Directory	/workspace/16.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2417218757
Short name	T690
Test name
Test status
Simulation time	64180515 ps
CPU time	1 seconds
Started	Apr 28 12:56:30 PM PDT 24
Finished	Apr 28 12:56:32 PM PDT 24
Peak memory	200904 kb
Host	smart-fa12f81d-8996-4b3a-86c5-03d8156a0f78
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417218757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.2417218757
Directory	/workspace/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.3200485497
Short name	T302
Test name
Test status
Simulation time	16773706 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:31 PM PDT 24
Finished	Apr 28 12:56:33 PM PDT 24
Peak memory	200896 kb
Host	smart-fbeaec85-8149-4abc-959f-fffcbdcf0707
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200485497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_clk_byp_req_intersig_mubi.3200485497
Directory	/workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.2410610810
Short name	T816
Test name
Test status
Simulation time	16609432 ps
CPU time	0.75 seconds
Started	Apr 28 12:56:26 PM PDT 24
Finished	Apr 28 12:56:28 PM PDT 24
Peak memory	200884 kb
Host	smart-7358754d-5eb7-4365-901e-94c90c6dd0e3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410610810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_ctrl_intersig_mubi.2410610810
Directory	/workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_peri.2244582487
Short name	T257
Test name
Test status
Simulation time	23431685 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:25 PM PDT 24
Finished	Apr 28 12:56:27 PM PDT 24
Peak memory	200916 kb
Host	smart-c1d8d2b4-fa46-468a-9542-9555713e66c9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244582487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.2244582487
Directory	/workspace/16.clkmgr_peri/latest

Test location	/workspace/coverage/default/16.clkmgr_regwen.1349181863
Short name	T276
Test name
Test status
Simulation time	1235043256 ps
CPU time	4.49 seconds
Started	Apr 28 12:56:35 PM PDT 24
Finished	Apr 28 12:56:40 PM PDT 24
Peak memory	201100 kb
Host	smart-43bfcabc-375f-4edd-bec9-73175d01ae9b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349181863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1349181863
Directory	/workspace/16.clkmgr_regwen/latest

Test location	/workspace/coverage/default/16.clkmgr_smoke.3755970825
Short name	T767
Test name
Test status
Simulation time	15446264 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:31 PM PDT 24
Finished	Apr 28 12:56:33 PM PDT 24
Peak memory	201072 kb
Host	smart-72bbccaf-1bbe-4a6e-9d8b-c4bffd73a17b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755970825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3755970825
Directory	/workspace/16.clkmgr_smoke/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all.32551491
Short name	T776
Test name
Test status
Simulation time	12609990836 ps
CPU time	47.19 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	201400 kb
Host	smart-01761d03-956b-4f33-910e-383c89ad8dc1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32551491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.clkmgr_stress_all.32551491
Directory	/workspace/16.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2779774087
Short name	T59
Test name
Test status
Simulation time	48790834999 ps
CPU time	758.77 seconds
Started	Apr 28 12:56:35 PM PDT 24
Finished	Apr 28 01:09:15 PM PDT 24
Peak memory	209724 kb
Host	smart-67f3ac82-651c-43ea-8903-0eb29e5149e8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2779774087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2779774087
Directory	/workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.clkmgr_trans.3750374452
Short name	T764
Test name
Test status
Simulation time	95548772 ps
CPU time	1.15 seconds
Started	Apr 28 12:56:27 PM PDT 24
Finished	Apr 28 12:56:30 PM PDT 24
Peak memory	201004 kb
Host	smart-86a130c3-2803-4761-8dad-da29c223dad9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750374452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3750374452
Directory	/workspace/16.clkmgr_trans/latest

Test location	/workspace/coverage/default/17.clkmgr_alert_test.1164713581
Short name	T706
Test name
Test status
Simulation time	20104318 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:32 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	200932 kb
Host	smart-f431096e-74fb-4384-8d1e-5d66413f6b75
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164713581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk mgr_alert_test.1164713581
Directory	/workspace/17.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2841136737
Short name	T832
Test name
Test status
Simulation time	39187533 ps
CPU time	0.89 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 12:56:40 PM PDT 24
Peak memory	200864 kb
Host	smart-c28c30a5-ef09-4afa-9301-df666c28f25c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841136737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.2841136737
Directory	/workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_status.488685272
Short name	T793
Test name
Test status
Simulation time	16980795 ps
CPU time	0.69 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:30 PM PDT 24
Peak memory	199984 kb
Host	smart-551055e3-0b47-4cba-b168-d0d975f6e418
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488685272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.488685272
Directory	/workspace/17.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/17.clkmgr_div_intersig_mubi.2907945418
Short name	T578
Test name
Test status
Simulation time	39094750 ps
CPU time	0.76 seconds
Started	Apr 28 12:56:33 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	200956 kb
Host	smart-a328188e-c0fd-419b-92df-9f7f949e074c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907945418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.2907945418
Directory	/workspace/17.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_extclk.3124156893
Short name	T23
Test name
Test status
Simulation time	101353882 ps
CPU time	1.08 seconds
Started	Apr 28 12:56:27 PM PDT 24
Finished	Apr 28 12:56:30 PM PDT 24
Peak memory	201004 kb
Host	smart-2ae73134-e380-471d-82f3-a89a7bb7287b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124156893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3124156893
Directory	/workspace/17.clkmgr_extclk/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency.3628636253
Short name	T16
Test name
Test status
Simulation time	477912049 ps
CPU time	2.44 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:33 PM PDT 24
Peak memory	200892 kb
Host	smart-718721c2-fe7f-4b76-aed3-ff5c08bf404b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628636253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3628636253
Directory	/workspace/17.clkmgr_frequency/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency_timeout.1862393390
Short name	T232
Test name
Test status
Simulation time	2424119587 ps
CPU time	12.44 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	201364 kb
Host	smart-0919b547-ca38-4dfd-abee-c2e2d091af4c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862393390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t imeout.1862393390
Directory	/workspace/17.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/17.clkmgr_idle_intersig_mubi.1402155830
Short name	T61
Test name
Test status
Simulation time	53832214 ps
CPU time	1.03 seconds
Started	Apr 28 12:56:31 PM PDT 24
Finished	Apr 28 12:56:33 PM PDT 24
Peak memory	201000 kb
Host	smart-4cf2842e-1cb0-4410-9722-82c99b56743f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402155830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.1402155830
Directory	/workspace/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.215331043
Short name	T677
Test name
Test status
Simulation time	24369658 ps
CPU time	0.85 seconds
Started	Apr 28 12:56:29 PM PDT 24
Finished	Apr 28 12:56:31 PM PDT 24
Peak memory	201008 kb
Host	smart-80bf0ee9-a2c9-4d57-8fde-c0ec5acd371d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215331043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.clkmgr_lc_clk_byp_req_intersig_mubi.215331043
Directory	/workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.3791123497
Short name	T752
Test name
Test status
Simulation time	25678650 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:30 PM PDT 24
Peak memory	200976 kb
Host	smart-7c07224d-5d10-4379-b257-c7a33bf050dd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791123497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_ctrl_intersig_mubi.3791123497
Directory	/workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_peri.2186082498
Short name	T24
Test name
Test status
Simulation time	40840568 ps
CPU time	0.73 seconds
Started	Apr 28 12:56:34 PM PDT 24
Finished	Apr 28 12:56:35 PM PDT 24
Peak memory	200872 kb
Host	smart-25aa1b56-8642-4fa8-a607-3c12a3e6b497
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186082498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2186082498
Directory	/workspace/17.clkmgr_peri/latest

Test location	/workspace/coverage/default/17.clkmgr_smoke.223289939
Short name	T737
Test name
Test status
Simulation time	22795900 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:33 PM PDT 24
Finished	Apr 28 12:56:35 PM PDT 24
Peak memory	201044 kb
Host	smart-2072bc5d-520d-4af5-add8-26c6d78e419e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223289939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.223289939
Directory	/workspace/17.clkmgr_smoke/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all.4092805601
Short name	T373
Test name
Test status
Simulation time	1884506678 ps
CPU time	13.87 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:43 PM PDT 24
Peak memory	201296 kb
Host	smart-9781cb9f-b46d-48bf-a0d8-3e43b4ef2922
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092805601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.4092805601
Directory	/workspace/17.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.1205345649
Short name	T821
Test name
Test status
Simulation time	38763728875 ps
CPU time	714.93 seconds
Started	Apr 28 12:56:32 PM PDT 24
Finished	Apr 28 01:08:28 PM PDT 24
Peak memory	217728 kb
Host	smart-c2fa4131-6b1a-435c-b4e8-4ae77b31c125
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1205345649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.1205345649
Directory	/workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.clkmgr_trans.1929075779
Short name	T253
Test name
Test status
Simulation time	12509531 ps
CPU time	0.72 seconds
Started	Apr 28 12:56:32 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	200876 kb
Host	smart-cfe6d727-f7c5-4ce9-b316-adb6d90451cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929075779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.1929075779
Directory	/workspace/17.clkmgr_trans/latest

Test location	/workspace/coverage/default/18.clkmgr_alert_test.2515217477
Short name	T394
Test name
Test status
Simulation time	23329593 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:41 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	200964 kb
Host	smart-ee7192d0-6b44-47a3-a644-912939aaac4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515217477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk mgr_alert_test.2515217477
Directory	/workspace/18.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.2162774502
Short name	T835
Test name
Test status
Simulation time	15881170 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:49 PM PDT 24
Finished	Apr 28 12:56:51 PM PDT 24
Peak memory	201044 kb
Host	smart-b57b524f-1426-406d-97d4-935e197ea198
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162774502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.2162774502
Directory	/workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_status.2683693804
Short name	T728
Test name
Test status
Simulation time	14289537 ps
CPU time	0.71 seconds
Started	Apr 28 12:56:37 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	200024 kb
Host	smart-9fb07ed4-a81f-4096-ba93-0234c34d13c5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683693804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.2683693804
Directory	/workspace/18.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/18.clkmgr_div_intersig_mubi.3410444797
Short name	T498
Test name
Test status
Simulation time	25801456 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:36 PM PDT 24
Finished	Apr 28 12:56:37 PM PDT 24
Peak memory	200904 kb
Host	smart-1573fcdb-ffb1-47e2-844f-dcaa74d0da1c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410444797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.3410444797
Directory	/workspace/18.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_extclk.2970031108
Short name	T348
Test name
Test status
Simulation time	67049658 ps
CPU time	0.92 seconds
Started	Apr 28 12:56:28 PM PDT 24
Finished	Apr 28 12:56:30 PM PDT 24
Peak memory	200984 kb
Host	smart-57667cc2-c464-42ac-be67-01d00bb42987
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970031108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2970031108
Directory	/workspace/18.clkmgr_extclk/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency.1934395064
Short name	T748
Test name
Test status
Simulation time	1075253683 ps
CPU time	5.08 seconds
Started	Apr 28 12:56:31 PM PDT 24
Finished	Apr 28 12:56:36 PM PDT 24
Peak memory	200924 kb
Host	smart-b539a5da-02be-4801-9e20-137161d446a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934395064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1934395064
Directory	/workspace/18.clkmgr_frequency/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency_timeout.1525909458
Short name	T645
Test name
Test status
Simulation time	2091149772 ps
CPU time	7.73 seconds
Started	Apr 28 12:56:29 PM PDT 24
Finished	Apr 28 12:56:38 PM PDT 24
Peak memory	201296 kb
Host	smart-df66cfd3-83ac-4eea-85a2-b83a6349df3e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525909458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t imeout.1525909458
Directory	/workspace/18.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/18.clkmgr_idle_intersig_mubi.3110374289
Short name	T168
Test name
Test status
Simulation time	155167033 ps
CPU time	1.15 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 12:56:40 PM PDT 24
Peak memory	201016 kb
Host	smart-fc68961f-60b2-4aab-a02a-bdaa7fafd01c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110374289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.3110374289
Directory	/workspace/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3078053701
Short name	T461
Test name
Test status
Simulation time	30811201 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:41 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	200876 kb
Host	smart-c19c969c-5130-43f1-a4e5-e9b5481ec150
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078053701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3078053701
Directory	/workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.980930463
Short name	T203
Test name
Test status
Simulation time	16595687 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:33 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	200924 kb
Host	smart-605953ce-b54c-4a85-96d1-c0d6d74cb31b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980930463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.clkmgr_lc_ctrl_intersig_mubi.980930463
Directory	/workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_peri.4042979421
Short name	T528
Test name
Test status
Simulation time	91522719 ps
CPU time	0.92 seconds
Started	Apr 28 12:56:32 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	200880 kb
Host	smart-dad4b398-2a5e-4234-9a01-82dd92e508c0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042979421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.4042979421
Directory	/workspace/18.clkmgr_peri/latest

Test location	/workspace/coverage/default/18.clkmgr_regwen.996768071
Short name	T671
Test name
Test status
Simulation time	1004390452 ps
CPU time	3.91 seconds
Started	Apr 28 12:56:37 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	200984 kb
Host	smart-76eddfda-298b-4864-8314-6bf68abbf3e2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996768071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.996768071
Directory	/workspace/18.clkmgr_regwen/latest

Test location	/workspace/coverage/default/18.clkmgr_smoke.1569499143
Short name	T534
Test name
Test status
Simulation time	41783536 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:33 PM PDT 24
Finished	Apr 28 12:56:34 PM PDT 24
Peak memory	201068 kb
Host	smart-d2d8d8d8-772a-4a12-8c68-62b398eea097
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569499143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.1569499143
Directory	/workspace/18.clkmgr_smoke/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all.3531376163
Short name	T240
Test name
Test status
Simulation time	3797941463 ps
CPU time	21.89 seconds
Started	Apr 28 12:56:40 PM PDT 24
Finished	Apr 28 12:57:03 PM PDT 24
Peak memory	201440 kb
Host	smart-fadc8244-f66a-4d31-94dd-dff0ce2440b6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531376163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.3531376163
Directory	/workspace/18.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3963576619
Short name	T708
Test name
Test status
Simulation time	47113735995 ps
CPU time	530.31 seconds
Started	Apr 28 12:56:35 PM PDT 24
Finished	Apr 28 01:05:26 PM PDT 24
Peak memory	217832 kb
Host	smart-908e975a-b6ec-449f-99f6-88c08ef8af8a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3963576619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.3963576619
Directory	/workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.clkmgr_trans.3906153211
Short name	T328
Test name
Test status
Simulation time	30949973 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:40 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	200880 kb
Host	smart-0c14b4a2-128d-4198-92e7-565f69f51f6c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906153211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3906153211
Directory	/workspace/18.clkmgr_trans/latest

Test location	/workspace/coverage/default/19.clkmgr_alert_test.1965443384
Short name	T736
Test name
Test status
Simulation time	34180751 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:44 PM PDT 24
Finished	Apr 28 12:56:45 PM PDT 24
Peak memory	200960 kb
Host	smart-82bd0975-b4e9-4002-a447-6b8cb4995cec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965443384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk mgr_alert_test.1965443384
Directory	/workspace/19.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.614312212
Short name	T799
Test name
Test status
Simulation time	50997560 ps
CPU time	0.9 seconds
Started	Apr 28 12:56:45 PM PDT 24
Finished	Apr 28 12:56:47 PM PDT 24
Peak memory	201048 kb
Host	smart-79391947-e170-4b15-8372-43af641a3083
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614312212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.614312212
Directory	/workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_status.1393389370
Short name	T152
Test name
Test status
Simulation time	17213063 ps
CPU time	0.72 seconds
Started	Apr 28 12:56:41 PM PDT 24
Finished	Apr 28 12:56:43 PM PDT 24
Peak memory	200768 kb
Host	smart-ca1dd898-220c-49ca-a276-62662dd4d77a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393389370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1393389370
Directory	/workspace/19.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/19.clkmgr_div_intersig_mubi.1240183771
Short name	T599
Test name
Test status
Simulation time	372153605 ps
CPU time	1.81 seconds
Started	Apr 28 12:56:35 PM PDT 24
Finished	Apr 28 12:56:37 PM PDT 24
Peak memory	200980 kb
Host	smart-a519007b-5842-4bb2-bdd3-ab7836d34dfa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240183771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.1240183771
Directory	/workspace/19.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_extclk.2990794929
Short name	T271
Test name
Test status
Simulation time	86253824 ps
CPU time	0.98 seconds
Started	Apr 28 12:56:37 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	200892 kb
Host	smart-1bae2e0e-8f55-4fcc-9d9b-3f8c42c411bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990794929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2990794929
Directory	/workspace/19.clkmgr_extclk/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency.1708228
Short name	T629
Test name
Test status
Simulation time	1742207211 ps
CPU time	7.29 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:57:06 PM PDT 24
Peak memory	200956 kb
Host	smart-f5ee141e-85dd-46b2-9623-3034dd7d035d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.1708228
Directory	/workspace/19.clkmgr_frequency/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency_timeout.3263285500
Short name	T164
Test name
Test status
Simulation time	2303439702 ps
CPU time	14.27 seconds
Started	Apr 28 12:56:34 PM PDT 24
Finished	Apr 28 12:56:49 PM PDT 24
Peak memory	201316 kb
Host	smart-c7b1b490-780f-464a-9ff8-e4a4978028cc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263285500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t imeout.3263285500
Directory	/workspace/19.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/19.clkmgr_idle_intersig_mubi.2771375959
Short name	T181
Test name
Test status
Simulation time	38320073 ps
CPU time	0.96 seconds
Started	Apr 28 12:56:37 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	200924 kb
Host	smart-8071602c-b454-4891-ac7a-4811da3c20f3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771375959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.2771375959
Directory	/workspace/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2087605490
Short name	T501
Test name
Test status
Simulation time	15120050 ps
CPU time	0.72 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 12:56:40 PM PDT 24
Peak memory	201016 kb
Host	smart-917974d9-1386-4500-b24f-9dc624ade6fe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087605490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2087605490
Directory	/workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.4201331037
Short name	T210
Test name
Test status
Simulation time	27578153 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 12:56:40 PM PDT 24
Peak memory	200892 kb
Host	smart-4a59afa4-e24f-4846-841d-50bd7ddf5c2f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201331037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_ctrl_intersig_mubi.4201331037
Directory	/workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_peri.3856957403
Short name	T472
Test name
Test status
Simulation time	35158047 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:40 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	200868 kb
Host	smart-42c48fd4-3910-4d50-b7ce-2a64718524b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856957403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3856957403
Directory	/workspace/19.clkmgr_peri/latest

Test location	/workspace/coverage/default/19.clkmgr_regwen.2147346268
Short name	T572
Test name
Test status
Simulation time	964501450 ps
CPU time	4.35 seconds
Started	Apr 28 12:56:45 PM PDT 24
Finished	Apr 28 12:56:50 PM PDT 24
Peak memory	201132 kb
Host	smart-54277963-e042-4a2e-8542-c9ebe23264f9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147346268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2147346268
Directory	/workspace/19.clkmgr_regwen/latest

Test location	/workspace/coverage/default/19.clkmgr_smoke.403685721
Short name	T598
Test name
Test status
Simulation time	24557387 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 12:56:40 PM PDT 24
Peak memory	201080 kb
Host	smart-8ceb3c7e-950d-433a-aa92-4d1104e5e58a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403685721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.403685721
Directory	/workspace/19.clkmgr_smoke/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all.3564465403
Short name	T435
Test name
Test status
Simulation time	3277682984 ps
CPU time	15.61 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 12:56:55 PM PDT 24
Peak memory	201420 kb
Host	smart-93554cb2-f865-4946-bb9b-60df098ac971
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564465403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.3564465403
Directory	/workspace/19.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.3878786837
Short name	T715
Test name
Test status
Simulation time	46829105358 ps
CPU time	678.76 seconds
Started	Apr 28 12:56:34 PM PDT 24
Finished	Apr 28 01:07:54 PM PDT 24
Peak memory	209628 kb
Host	smart-8afe336f-0c97-4bef-abfa-957c6eaf98e6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3878786837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.3878786837
Directory	/workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.clkmgr_trans.2711782266
Short name	T234
Test name
Test status
Simulation time	17897076 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:41 PM PDT 24
Finished	Apr 28 12:56:43 PM PDT 24
Peak memory	200948 kb
Host	smart-ff6c5cf5-0104-4612-afa0-3a9aca057c90
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711782266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2711782266
Directory	/workspace/19.clkmgr_trans/latest

Test location	/workspace/coverage/default/2.clkmgr_alert_test.497962082
Short name	T475
Test name
Test status
Simulation time	43006861 ps
CPU time	0.84 seconds
Started	Apr 28 12:55:55 PM PDT 24
Finished	Apr 28 12:55:56 PM PDT 24
Peak memory	200964 kb
Host	smart-cd5ac1ec-b997-462d-a76d-785aae92b9d7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497962082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg r_alert_test.497962082
Directory	/workspace/2.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2650887300
Short name	T426
Test name
Test status
Simulation time	23444697 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	201040 kb
Host	smart-286e7f9a-9b8c-46df-abdb-4a139741987d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650887300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.2650887300
Directory	/workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_status.1477284125
Short name	T382
Test name
Test status
Simulation time	75123165 ps
CPU time	0.83 seconds
Started	Apr 28 12:55:54 PM PDT 24
Finished	Apr 28 12:55:55 PM PDT 24
Peak memory	199952 kb
Host	smart-717c3bb6-c19b-49cd-b43b-8c2720621eb8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477284125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1477284125
Directory	/workspace/2.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/2.clkmgr_div_intersig_mubi.1574264879
Short name	T613
Test name
Test status
Simulation time	64137922 ps
CPU time	0.96 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:58 PM PDT 24
Peak memory	200896 kb
Host	smart-34581b03-d00b-4b99-ba57-4cecd7917a62
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574264879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.1574264879
Directory	/workspace/2.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_extclk.1933791127
Short name	T165
Test name
Test status
Simulation time	64448907 ps
CPU time	1.04 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	201044 kb
Host	smart-fbe1fc2f-8288-4e57-a676-00fd55e91472
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933791127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1933791127
Directory	/workspace/2.clkmgr_extclk/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency.744147524
Short name	T64
Test name
Test status
Simulation time	1754445876 ps
CPU time	13.7 seconds
Started	Apr 28 12:55:53 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	201076 kb
Host	smart-594cc63c-57f5-4ad1-bbcb-f39f62b5205f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744147524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.744147524
Directory	/workspace/2.clkmgr_frequency/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency_timeout.3782801347
Short name	T413
Test name
Test status
Simulation time	1099886177 ps
CPU time	8.22 seconds
Started	Apr 28 12:55:55 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	201120 kb
Host	smart-a0c7300a-a524-4700-8122-db292a750098
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782801347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti meout.3782801347
Directory	/workspace/2.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/2.clkmgr_idle_intersig_mubi.95008900
Short name	T791
Test name
Test status
Simulation time	18366554 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:03 PM PDT 24
Peak memory	200896 kb
Host	smart-d2dbb5f7-f49a-4438-82de-22040d473088
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95008900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. clkmgr_idle_intersig_mubi.95008900
Directory	/workspace/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.3453493261
Short name	T236
Test name
Test status
Simulation time	48457680 ps
CPU time	0.76 seconds
Started	Apr 28 12:55:55 PM PDT 24
Finished	Apr 28 12:55:56 PM PDT 24
Peak memory	200884 kb
Host	smart-0d86a2cf-8d9b-481b-b3ae-883474221206
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453493261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_clk_byp_req_intersig_mubi.3453493261
Directory	/workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1575622943
Short name	T169
Test name
Test status
Simulation time	17171549 ps
CPU time	0.75 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:58 PM PDT 24
Peak memory	200812 kb
Host	smart-93ee2905-e4fb-47be-9e2f-931d41bbd393
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575622943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_ctrl_intersig_mubi.1575622943
Directory	/workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_peri.2367711065
Short name	T445
Test name
Test status
Simulation time	14360544 ps
CPU time	0.73 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:00 PM PDT 24
Peak memory	200944 kb
Host	smart-92ecb162-e97f-42c8-8619-06cbd0d8145a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367711065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2367711065
Directory	/workspace/2.clkmgr_peri/latest

Test location	/workspace/coverage/default/2.clkmgr_regwen.1643733821
Short name	T508
Test name
Test status
Simulation time	567427150 ps
CPU time	2.32 seconds
Started	Apr 28 12:55:57 PM PDT 24
Finished	Apr 28 12:56:01 PM PDT 24
Peak memory	200960 kb
Host	smart-3a55ce26-58f3-4e8b-bf16-93901df914b6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643733821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1643733821
Directory	/workspace/2.clkmgr_regwen/latest

Test location	/workspace/coverage/default/2.clkmgr_smoke.2679404618
Short name	T468
Test name
Test status
Simulation time	56197769 ps
CPU time	0.96 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:00 PM PDT 24
Peak memory	200956 kb
Host	smart-b2c472d2-b405-43a7-a03b-ccbdd82809b5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679404618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2679404618
Directory	/workspace/2.clkmgr_smoke/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all.2438407794
Short name	T663
Test name
Test status
Simulation time	10562969822 ps
CPU time	37.64 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:56:35 PM PDT 24
Peak memory	201464 kb
Host	smart-0109129c-72d9-44bb-9923-5c7fd9a2030c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438407794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.2438407794
Directory	/workspace/2.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.4105173093
Short name	T760
Test name
Test status
Simulation time	129494741648 ps
CPU time	742.69 seconds
Started	Apr 28 12:55:55 PM PDT 24
Finished	Apr 28 01:08:18 PM PDT 24
Peak memory	212888 kb
Host	smart-0eb1bccf-4eb1-4ce3-b02f-58dd0138a126
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4105173093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.4105173093
Directory	/workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.clkmgr_trans.2906821213
Short name	T443
Test name
Test status
Simulation time	29395637 ps
CPU time	0.94 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:58 PM PDT 24
Peak memory	201000 kb
Host	smart-dbae8d63-451c-4d23-b003-d3fba150aeed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906821213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2906821213
Directory	/workspace/2.clkmgr_trans/latest

Test location	/workspace/coverage/default/20.clkmgr_alert_test.1177062249
Short name	T718
Test name
Test status
Simulation time	58844457 ps
CPU time	0.93 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	201024 kb
Host	smart-b959c858-a5e8-440b-9247-068c865fdc75
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177062249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk mgr_alert_test.1177062249
Directory	/workspace/20.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.2796518502
Short name	T301
Test name
Test status
Simulation time	21356288 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	200876 kb
Host	smart-5bae5f63-d51e-48b8-bc99-52d1076c4143
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796518502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.2796518502
Directory	/workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_status.233759900
Short name	T606
Test name
Test status
Simulation time	27946373 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:36 PM PDT 24
Finished	Apr 28 12:56:38 PM PDT 24
Peak memory	200856 kb
Host	smart-bf25016f-efec-4eec-a4e6-8272eacc5ec9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233759900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.233759900
Directory	/workspace/20.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/20.clkmgr_div_intersig_mubi.3422623933
Short name	T347
Test name
Test status
Simulation time	41245872 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:40 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	200840 kb
Host	smart-8d88548a-aea5-475f-bbce-7c949c8d0ff8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422623933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.3422623933
Directory	/workspace/20.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_extclk.4294532780
Short name	T185
Test name
Test status
Simulation time	96108304 ps
CPU time	1.1 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	200888 kb
Host	smart-ccc484e8-24b9-41fd-a2a7-1b3383d3aaf6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294532780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.4294532780
Directory	/workspace/20.clkmgr_extclk/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency.3388020987
Short name	T656
Test name
Test status
Simulation time	1712883420 ps
CPU time	7.56 seconds
Started	Apr 28 12:56:52 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	200964 kb
Host	smart-343eb90c-26fa-4f39-9257-db55227b5dd8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388020987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.3388020987
Directory	/workspace/20.clkmgr_frequency/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency_timeout.2182973444
Short name	T543
Test name
Test status
Simulation time	1746492961 ps
CPU time	5.77 seconds
Started	Apr 28 12:56:41 PM PDT 24
Finished	Apr 28 12:56:48 PM PDT 24
Peak memory	201008 kb
Host	smart-f02d98e5-fc6c-4315-a543-d87f25f73b43
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182973444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t imeout.2182973444
Directory	/workspace/20.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/20.clkmgr_idle_intersig_mubi.774885520
Short name	T207
Test name
Test status
Simulation time	30063528 ps
CPU time	0.93 seconds
Started	Apr 28 12:56:36 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	200984 kb
Host	smart-b756cf72-5a56-4a74-a658-435b36eb7375
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774885520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.clkmgr_idle_intersig_mubi.774885520
Directory	/workspace/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2632305250
Short name	T664
Test name
Test status
Simulation time	15606856 ps
CPU time	0.75 seconds
Started	Apr 28 12:56:34 PM PDT 24
Finished	Apr 28 12:56:36 PM PDT 24
Peak memory	200952 kb
Host	smart-c9318cdf-6733-488e-8c44-1540e0737951
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632305250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2632305250
Directory	/workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2254243062
Short name	T291
Test name
Test status
Simulation time	96391376 ps
CPU time	1.1 seconds
Started	Apr 28 12:56:36 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	200988 kb
Host	smart-af56d6e5-6d43-471b-b9aa-7b57fccb3d3b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254243062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_ctrl_intersig_mubi.2254243062
Directory	/workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_peri.1571120153
Short name	T274
Test name
Test status
Simulation time	128172928 ps
CPU time	1.04 seconds
Started	Apr 28 12:56:37 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	200892 kb
Host	smart-1cc5eec2-2c6d-47af-b8f6-ba14fbfdb4e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571120153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.1571120153
Directory	/workspace/20.clkmgr_peri/latest

Test location	/workspace/coverage/default/20.clkmgr_regwen.1696461839
Short name	T279
Test name
Test status
Simulation time	1242280120 ps
CPU time	5.31 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:46 PM PDT 24
Peak memory	201040 kb
Host	smart-56c2767d-27a8-4438-beed-4df079f065cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696461839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1696461839
Directory	/workspace/20.clkmgr_regwen/latest

Test location	/workspace/coverage/default/20.clkmgr_smoke.2977211783
Short name	T481
Test name
Test status
Simulation time	60854946 ps
CPU time	0.97 seconds
Started	Apr 28 12:56:53 PM PDT 24
Finished	Apr 28 12:56:54 PM PDT 24
Peak memory	200972 kb
Host	smart-08dcd0a9-88c2-477b-8475-e00c313781e8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977211783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.2977211783
Directory	/workspace/20.clkmgr_smoke/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all.3737762355
Short name	T511
Test name
Test status
Simulation time	2854685103 ps
CPU time	12.68 seconds
Started	Apr 28 12:56:45 PM PDT 24
Finished	Apr 28 12:56:58 PM PDT 24
Peak memory	201272 kb
Host	smart-acaa85b2-108c-4a3e-a7bf-77e9b4293fde
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737762355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3737762355
Directory	/workspace/20.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.1619506236
Short name	T775
Test name
Test status
Simulation time	20303605471 ps
CPU time	300.78 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 01:01:49 PM PDT 24
Peak memory	209680 kb
Host	smart-5f7bdc57-56bd-4386-b498-67ee6ade268f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1619506236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.1619506236
Directory	/workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.clkmgr_trans.1310176931
Short name	T355
Test name
Test status
Simulation time	17950373 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:37 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	200880 kb
Host	smart-aa17e5db-0302-4828-a41d-9256be0d3e8d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310176931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.1310176931
Directory	/workspace/20.clkmgr_trans/latest

Test location	/workspace/coverage/default/21.clkmgr_alert_test.2827820113
Short name	T345
Test name
Test status
Simulation time	61973979 ps
CPU time	0.89 seconds
Started	Apr 28 12:56:36 PM PDT 24
Finished	Apr 28 12:56:38 PM PDT 24
Peak memory	200944 kb
Host	smart-9cf52660-81da-4e66-86bf-fd182a30be38
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827820113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk mgr_alert_test.2827820113
Directory	/workspace/21.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.1041822358
Short name	T80
Test name
Test status
Simulation time	52656634 ps
CPU time	0.9 seconds
Started	Apr 28 12:56:42 PM PDT 24
Finished	Apr 28 12:56:44 PM PDT 24
Peak memory	200860 kb
Host	smart-81af0d17-8b82-458a-aa21-29c7b3b121f5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041822358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.1041822358
Directory	/workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_status.3609673617
Short name	T662
Test name
Test status
Simulation time	46910843 ps
CPU time	0.76 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	199908 kb
Host	smart-d92dd149-389d-47d6-804c-2b902ace1210
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609673617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.3609673617
Directory	/workspace/21.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/21.clkmgr_div_intersig_mubi.2694122068
Short name	T148
Test name
Test status
Simulation time	15253899 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:40 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	201004 kb
Host	smart-e3901ea1-3e50-4165-b68d-33a52e14e971
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694122068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.2694122068
Directory	/workspace/21.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_extclk.1295257431
Short name	T408
Test name
Test status
Simulation time	39830529 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	200840 kb
Host	smart-c1385c88-e92f-4237-8a9d-711668f6993b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295257431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1295257431
Directory	/workspace/21.clkmgr_extclk/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency.873751513
Short name	T637
Test name
Test status
Simulation time	1281768044 ps
CPU time	7.42 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:48 PM PDT 24
Peak memory	201000 kb
Host	smart-a4e6a408-48cc-49e8-bf92-0a10b2914e5b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873751513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.873751513
Directory	/workspace/21.clkmgr_frequency/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency_timeout.3461546216
Short name	T491
Test name
Test status
Simulation time	1937911145 ps
CPU time	14.25 seconds
Started	Apr 28 12:56:46 PM PDT 24
Finished	Apr 28 12:57:01 PM PDT 24
Peak memory	201000 kb
Host	smart-f8f92572-f8cb-4890-a3b8-7a08dfc60d85
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461546216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t imeout.3461546216
Directory	/workspace/21.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/21.clkmgr_idle_intersig_mubi.3016127330
Short name	T493
Test name
Test status
Simulation time	66094631 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 12:56:40 PM PDT 24
Peak memory	200868 kb
Host	smart-be3cbbf6-f1ca-458c-b904-4a14eb68d27b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016127330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3016127330
Directory	/workspace/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.866637426
Short name	T621
Test name
Test status
Simulation time	45232408 ps
CPU time	0.85 seconds
Started	Apr 28 12:56:43 PM PDT 24
Finished	Apr 28 12:56:45 PM PDT 24
Peak memory	201000 kb
Host	smart-2884f09a-7373-4b29-8bce-b990c1eae329
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866637426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.clkmgr_lc_clk_byp_req_intersig_mubi.866637426
Directory	/workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.2111767231
Short name	T175
Test name
Test status
Simulation time	50037903 ps
CPU time	0.94 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	200976 kb
Host	smart-a2b7f3ca-9412-4b94-a1e7-3578c0f4f75d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111767231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_ctrl_intersig_mubi.2111767231
Directory	/workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_peri.2591315621
Short name	T448
Test name
Test status
Simulation time	26766912 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	200992 kb
Host	smart-05d1b746-6b4b-4ca3-87f2-6610b9352ef4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591315621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.2591315621
Directory	/workspace/21.clkmgr_peri/latest

Test location	/workspace/coverage/default/21.clkmgr_regwen.1854616152
Short name	T492
Test name
Test status
Simulation time	56954323 ps
CPU time	0.95 seconds
Started	Apr 28 12:56:46 PM PDT 24
Finished	Apr 28 12:56:47 PM PDT 24
Peak memory	200892 kb
Host	smart-2850e824-248f-4cd6-97ed-89cbd04cc059
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854616152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1854616152
Directory	/workspace/21.clkmgr_regwen/latest

Test location	/workspace/coverage/default/21.clkmgr_smoke.4159897906
Short name	T478
Test name
Test status
Simulation time	54883515 ps
CPU time	0.88 seconds
Started	Apr 28 12:56:37 PM PDT 24
Finished	Apr 28 12:56:39 PM PDT 24
Peak memory	201060 kb
Host	smart-46cd5a68-e23a-451a-97e8-dbbb384ced1b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159897906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.4159897906
Directory	/workspace/21.clkmgr_smoke/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all.2188133828
Short name	T66
Test name
Test status
Simulation time	2169945250 ps
CPU time	10.38 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:51 PM PDT 24
Peak memory	201140 kb
Host	smart-9a3f8493-3814-4d99-9e57-d1fbce3500d3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188133828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.2188133828
Directory	/workspace/21.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.1453059079
Short name	T473
Test name
Test status
Simulation time	21253324019 ps
CPU time	396.37 seconds
Started	Apr 28 12:56:38 PM PDT 24
Finished	Apr 28 01:03:16 PM PDT 24
Peak memory	209720 kb
Host	smart-522b5d31-6e81-4641-97b9-7b3204b7e5d6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1453059079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.1453059079
Directory	/workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.clkmgr_trans.2877373859
Short name	T549
Test name
Test status
Simulation time	16416063 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:40 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	200960 kb
Host	smart-5d17d5a0-e77a-4093-8c83-3d092e4479c0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877373859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2877373859
Directory	/workspace/21.clkmgr_trans/latest

Test location	/workspace/coverage/default/22.clkmgr_alert_test.2901272853
Short name	T290
Test name
Test status
Simulation time	17593596 ps
CPU time	0.76 seconds
Started	Apr 28 12:56:40 PM PDT 24
Finished	Apr 28 12:56:42 PM PDT 24
Peak memory	201028 kb
Host	smart-0ca8199a-3e98-4846-8708-c0270c69c3fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901272853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk mgr_alert_test.2901272853
Directory	/workspace/22.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.3084966180
Short name	T397
Test name
Test status
Simulation time	31282346 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:50 PM PDT 24
Finished	Apr 28 12:56:52 PM PDT 24
Peak memory	200996 kb
Host	smart-16be21bf-3798-41e1-a3e5-765d88939782
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084966180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.3084966180
Directory	/workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_status.480005344
Short name	T451
Test name
Test status
Simulation time	19522205 ps
CPU time	0.73 seconds
Started	Apr 28 12:56:41 PM PDT 24
Finished	Apr 28 12:56:43 PM PDT 24
Peak memory	199872 kb
Host	smart-300e680d-e440-4b08-b8ad-c5fe34902457
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480005344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.480005344
Directory	/workspace/22.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/22.clkmgr_div_intersig_mubi.151741082
Short name	T520
Test name
Test status
Simulation time	33975558 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201000 kb
Host	smart-c7d872ab-1aaf-4663-8d1d-66bae676c428
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151741082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.clkmgr_div_intersig_mubi.151741082
Directory	/workspace/22.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_extclk.298891048
Short name	T444
Test name
Test status
Simulation time	47050736 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201000 kb
Host	smart-921b6de4-a9b5-4062-b714-90c41cb9dfc2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298891048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.298891048
Directory	/workspace/22.clkmgr_extclk/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency.3899618955
Short name	T633
Test name
Test status
Simulation time	1483982403 ps
CPU time	6.64 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201072 kb
Host	smart-6602b600-75d3-45a7-b724-c4308ef07818
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899618955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3899618955
Directory	/workspace/22.clkmgr_frequency/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency_timeout.2664183332
Short name	T368
Test name
Test status
Simulation time	2180990005 ps
CPU time	15.57 seconds
Started	Apr 28 12:56:40 PM PDT 24
Finished	Apr 28 12:56:57 PM PDT 24
Peak memory	201224 kb
Host	smart-3c1f8007-80b6-4c6d-97ba-dcc893bb1847
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664183332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t imeout.2664183332
Directory	/workspace/22.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/22.clkmgr_idle_intersig_mubi.1626312228
Short name	T341
Test name
Test status
Simulation time	37456469 ps
CPU time	0.85 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:56:58 PM PDT 24
Peak memory	200996 kb
Host	smart-8813d02b-4232-4a9c-8693-f0b04a91d87c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626312228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.1626312228
Directory	/workspace/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.1217286096
Short name	T643
Test name
Test status
Simulation time	24023576 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:56:59 PM PDT 24
Peak memory	200984 kb
Host	smart-95e69c9e-5bf9-4145-8f19-ee4cdd046836
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217286096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_clk_byp_req_intersig_mubi.1217286096
Directory	/workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2990143900
Short name	T488
Test name
Test status
Simulation time	34127565 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:50 PM PDT 24
Finished	Apr 28 12:56:52 PM PDT 24
Peak memory	201000 kb
Host	smart-f28d9d72-5f18-44b6-a901-c095d2250e0d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990143900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_ctrl_intersig_mubi.2990143900
Directory	/workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_peri.4037904605
Short name	T349
Test name
Test status
Simulation time	15692613 ps
CPU time	0.72 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	200900 kb
Host	smart-c18eed57-ede3-4a7b-b5aa-f1012898f23f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037904605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.4037904605
Directory	/workspace/22.clkmgr_peri/latest

Test location	/workspace/coverage/default/22.clkmgr_regwen.2865097372
Short name	T245
Test name
Test status
Simulation time	315398514 ps
CPU time	2.39 seconds
Started	Apr 28 12:56:47 PM PDT 24
Finished	Apr 28 12:56:50 PM PDT 24
Peak memory	200988 kb
Host	smart-38878605-9182-4da7-804f-42e74d8dc714
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865097372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2865097372
Directory	/workspace/22.clkmgr_regwen/latest

Test location	/workspace/coverage/default/22.clkmgr_smoke.4051478913
Short name	T128
Test name
Test status
Simulation time	50755017 ps
CPU time	0.92 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:56:59 PM PDT 24
Peak memory	201072 kb
Host	smart-66c1833a-0a8e-4365-9299-a939f64c8ada
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051478913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.4051478913
Directory	/workspace/22.clkmgr_smoke/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all.2592701511
Short name	T829
Test name
Test status
Simulation time	10099729042 ps
CPU time	49.71 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	201388 kb
Host	smart-f4253a39-a41f-4fb1-b24c-4eb21d0569fe
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592701511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.2592701511
Directory	/workspace/22.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/22.clkmgr_trans.2123770073
Short name	T626
Test name
Test status
Simulation time	39591657 ps
CPU time	1 seconds
Started	Apr 28 12:56:39 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	200996 kb
Host	smart-0f3a814e-0b06-464b-8cc0-6ae598d30e65
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123770073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.2123770073
Directory	/workspace/22.clkmgr_trans/latest

Test location	/workspace/coverage/default/23.clkmgr_alert_test.3893353060
Short name	T811
Test name
Test status
Simulation time	16968495 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 12:56:50 PM PDT 24
Peak memory	201028 kb
Host	smart-6465e301-5712-4020-9691-24cfbefb696c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893353060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk mgr_alert_test.3893353060
Directory	/workspace/23.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.200316705
Short name	T381
Test name
Test status
Simulation time	30204529 ps
CPU time	0.98 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201048 kb
Host	smart-fdacf250-11ba-4e1e-a05a-9fdc92d6dedd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200316705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.200316705
Directory	/workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_status.3588128558
Short name	T446
Test name
Test status
Simulation time	11798184 ps
CPU time	0.69 seconds
Started	Apr 28 12:56:50 PM PDT 24
Finished	Apr 28 12:56:51 PM PDT 24
Peak memory	200832 kb
Host	smart-11767a10-7e75-4786-b75e-0174fb32909a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588128558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3588128558
Directory	/workspace/23.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/23.clkmgr_div_intersig_mubi.3457370190
Short name	T416
Test name
Test status
Simulation time	64134660 ps
CPU time	0.97 seconds
Started	Apr 28 12:56:50 PM PDT 24
Finished	Apr 28 12:56:52 PM PDT 24
Peak memory	201000 kb
Host	smart-ae6dbec6-6cdc-4c64-8af9-c6a19723b0a3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457370190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.3457370190
Directory	/workspace/23.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_extclk.1567322152
Short name	T670
Test name
Test status
Simulation time	18924145 ps
CPU time	0.7 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 12:56:49 PM PDT 24
Peak memory	200996 kb
Host	smart-db3b02a3-75cb-4bd8-8090-e95b56de125a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567322152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.1567322152
Directory	/workspace/23.clkmgr_extclk/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency.582418174
Short name	T386
Test name
Test status
Simulation time	2115176592 ps
CPU time	16.78 seconds
Started	Apr 28 12:56:47 PM PDT 24
Finished	Apr 28 12:57:05 PM PDT 24
Peak memory	201244 kb
Host	smart-42cc54c0-8d56-471c-9163-828129811dd5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582418174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.582418174
Directory	/workspace/23.clkmgr_frequency/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency_timeout.3810148775
Short name	T170
Test name
Test status
Simulation time	260936827 ps
CPU time	2.49 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	201112 kb
Host	smart-a19710c0-cb72-432d-95e0-8e251d2d0812
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810148775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t imeout.3810148775
Directory	/workspace/23.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/23.clkmgr_idle_intersig_mubi.4113179578
Short name	T561
Test name
Test status
Simulation time	90583061 ps
CPU time	1.12 seconds
Started	Apr 28 12:56:45 PM PDT 24
Finished	Apr 28 12:56:46 PM PDT 24
Peak memory	200836 kb
Host	smart-26a6c9c9-21ba-4594-8766-793019005c9e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113179578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.4113179578
Directory	/workspace/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.4138273773
Short name	T806
Test name
Test status
Simulation time	50268038 ps
CPU time	0.85 seconds
Started	Apr 28 12:56:51 PM PDT 24
Finished	Apr 28 12:56:53 PM PDT 24
Peak memory	200868 kb
Host	smart-115cc8a5-1e12-4937-8ab9-dab7d5091d43
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138273773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_clk_byp_req_intersig_mubi.4138273773
Directory	/workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.403770646
Short name	T198
Test name
Test status
Simulation time	16139199 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:57 PM PDT 24
Peak memory	200988 kb
Host	smart-e94c2e56-016f-4313-81fd-d1bf7a2418ec
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403770646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.clkmgr_lc_ctrl_intersig_mubi.403770646
Directory	/workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_peri.4193687205
Short name	T25
Test name
Test status
Simulation time	32831872 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:44 PM PDT 24
Finished	Apr 28 12:56:45 PM PDT 24
Peak memory	200972 kb
Host	smart-4588e74f-c9de-409a-ab5a-d972870fa4ed
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193687205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.4193687205
Directory	/workspace/23.clkmgr_peri/latest

Test location	/workspace/coverage/default/23.clkmgr_regwen.2504160199
Short name	T725
Test name
Test status
Simulation time	716555791 ps
CPU time	2.98 seconds
Started	Apr 28 12:56:49 PM PDT 24
Finished	Apr 28 12:56:53 PM PDT 24
Peak memory	201148 kb
Host	smart-c315293f-77cb-4806-9928-e7934397500d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504160199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2504160199
Directory	/workspace/23.clkmgr_regwen/latest

Test location	/workspace/coverage/default/23.clkmgr_smoke.3311719037
Short name	T693
Test name
Test status
Simulation time	25402817 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201068 kb
Host	smart-30789d75-3a81-44ae-81d8-1b23e79d1176
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311719037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.3311719037
Directory	/workspace/23.clkmgr_smoke/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all.3992541009
Short name	T362
Test name
Test status
Simulation time	7362741876 ps
CPU time	28.14 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:57:27 PM PDT 24
Peak memory	201196 kb
Host	smart-456c72b1-2947-4c7c-bbff-c40c204c747e
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992541009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.3992541009
Directory	/workspace/23.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/23.clkmgr_trans.3395082236
Short name	T532
Test name
Test status
Simulation time	31712081 ps
CPU time	0.86 seconds
Started	Apr 28 12:56:45 PM PDT 24
Finished	Apr 28 12:56:46 PM PDT 24
Peak memory	201008 kb
Host	smart-88ae6c1d-6200-45cb-afe4-f5c3931d62a0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395082236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3395082236
Directory	/workspace/23.clkmgr_trans/latest

Test location	/workspace/coverage/default/24.clkmgr_alert_test.384066393
Short name	T505
Test name
Test status
Simulation time	48086750 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201068 kb
Host	smart-8b94c8d7-bd14-4b5f-be8b-1b158ed6391a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384066393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkm gr_alert_test.384066393
Directory	/workspace/24.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3540463854
Short name	T588
Test name
Test status
Simulation time	16018657 ps
CPU time	0.76 seconds
Started	Apr 28 12:56:51 PM PDT 24
Finished	Apr 28 12:56:52 PM PDT 24
Peak memory	200860 kb
Host	smart-25e68747-fbdf-4025-bad7-10b42fbb4238
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540463854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.3540463854
Directory	/workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_status.1825217996
Short name	T544
Test name
Test status
Simulation time	14339878 ps
CPU time	0.73 seconds
Started	Apr 28 12:56:46 PM PDT 24
Finished	Apr 28 12:56:47 PM PDT 24
Peak memory	200020 kb
Host	smart-25af2a61-0af4-4b71-81ec-b778d3544665
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825217996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.1825217996
Directory	/workspace/24.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/24.clkmgr_div_intersig_mubi.1863619932
Short name	T754
Test name
Test status
Simulation time	30296879 ps
CPU time	0.93 seconds
Started	Apr 28 12:56:47 PM PDT 24
Finished	Apr 28 12:56:49 PM PDT 24
Peak memory	201000 kb
Host	smart-096ac813-4d73-4d2a-bff8-cbbd7d5cd3ba
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863619932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.1863619932
Directory	/workspace/24.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_extclk.1663220040
Short name	T666
Test name
Test status
Simulation time	71310750 ps
CPU time	1.01 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	200880 kb
Host	smart-0841bc18-1e13-48a3-a8d2-8edab8f98372
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663220040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1663220040
Directory	/workspace/24.clkmgr_extclk/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency.1550556398
Short name	T555
Test name
Test status
Simulation time	205865002 ps
CPU time	1.74 seconds
Started	Apr 28 12:56:43 PM PDT 24
Finished	Apr 28 12:56:45 PM PDT 24
Peak memory	200912 kb
Host	smart-f23e98b9-99f3-4995-b6f2-34c4e963480c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550556398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1550556398
Directory	/workspace/24.clkmgr_frequency/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency_timeout.1758414939
Short name	T673
Test name
Test status
Simulation time	978167284 ps
CPU time	7.24 seconds
Started	Apr 28 12:56:44 PM PDT 24
Finished	Apr 28 12:56:52 PM PDT 24
Peak memory	201116 kb
Host	smart-fc206f81-96c5-48ab-a471-30f4e2a7101c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758414939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t imeout.1758414939
Directory	/workspace/24.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/24.clkmgr_idle_intersig_mubi.117746836
Short name	T217
Test name
Test status
Simulation time	19749670 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:51 PM PDT 24
Finished	Apr 28 12:56:53 PM PDT 24
Peak memory	200864 kb
Host	smart-2bf0294c-ef1e-48f6-aa60-ebd7782d5b0d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117746836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.clkmgr_idle_intersig_mubi.117746836
Directory	/workspace/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.3989157624
Short name	T161
Test name
Test status
Simulation time	36696565 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:50 PM PDT 24
Finished	Apr 28 12:56:51 PM PDT 24
Peak memory	200984 kb
Host	smart-6cdb8000-56ef-4c65-a922-abfbc3bb5d48
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989157624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_clk_byp_req_intersig_mubi.3989157624
Directory	/workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.1497674815
Short name	T755
Test name
Test status
Simulation time	57884237 ps
CPU time	0.89 seconds
Started	Apr 28 12:56:51 PM PDT 24
Finished	Apr 28 12:56:53 PM PDT 24
Peak memory	200856 kb
Host	smart-8d7ef57a-ab12-4386-a7ed-8685c8c0a906
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497674815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_ctrl_intersig_mubi.1497674815
Directory	/workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_peri.811262606
Short name	T546
Test name
Test status
Simulation time	36279850 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:43 PM PDT 24
Finished	Apr 28 12:56:44 PM PDT 24
Peak memory	200836 kb
Host	smart-a7d591f3-face-4f41-a278-11a9274a881c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811262606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.811262606
Directory	/workspace/24.clkmgr_peri/latest

Test location	/workspace/coverage/default/24.clkmgr_regwen.3815040974
Short name	T581
Test name
Test status
Simulation time	1049570361 ps
CPU time	3.89 seconds
Started	Apr 28 12:56:44 PM PDT 24
Finished	Apr 28 12:56:48 PM PDT 24
Peak memory	201084 kb
Host	smart-4bba68fb-a370-4ee7-9a2d-0e29363d4ccc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815040974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3815040974
Directory	/workspace/24.clkmgr_regwen/latest

Test location	/workspace/coverage/default/24.clkmgr_smoke.3666455327
Short name	T739
Test name
Test status
Simulation time	21531986 ps
CPU time	0.85 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	200956 kb
Host	smart-809f0ad9-9c17-4a8f-921e-b6232252af7a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666455327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3666455327
Directory	/workspace/24.clkmgr_smoke/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all.185618154
Short name	T363
Test name
Test status
Simulation time	4318431108 ps
CPU time	17.92 seconds
Started	Apr 28 12:56:49 PM PDT 24
Finished	Apr 28 12:57:08 PM PDT 24
Peak memory	201400 kb
Host	smart-c209b5a4-fda6-4500-951a-f58e3e099342
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185618154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.185618154
Directory	/workspace/24.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.3874473565
Short name	T139
Test name
Test status
Simulation time	116139310963 ps
CPU time	661.43 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 01:08:01 PM PDT 24
Peak memory	212852 kb
Host	smart-eec16813-7a33-4523-a1b8-5be5de9c63e9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3874473565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.3874473565
Directory	/workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.clkmgr_trans.2028470406
Short name	T805
Test name
Test status
Simulation time	21054343 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:53 PM PDT 24
Finished	Apr 28 12:56:55 PM PDT 24
Peak memory	201008 kb
Host	smart-1af9899f-8af7-4fbe-9496-92323fc54b07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028470406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2028470406
Directory	/workspace/24.clkmgr_trans/latest

Test location	/workspace/coverage/default/25.clkmgr_alert_test.1827753255
Short name	T189
Test name
Test status
Simulation time	26366953 ps
CPU time	0.84 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	200932 kb
Host	smart-763f2f18-621e-44d2-ad1e-2cfe4f69dcdc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827753255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk mgr_alert_test.1827753255
Directory	/workspace/25.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1525691625
Short name	T78
Test name
Test status
Simulation time	21640279 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:46 PM PDT 24
Finished	Apr 28 12:56:47 PM PDT 24
Peak memory	200896 kb
Host	smart-67aadb13-6618-40a3-be1e-ce3134892e40
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525691625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.1525691625
Directory	/workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_status.3248386094
Short name	T35
Test name
Test status
Simulation time	23877322 ps
CPU time	0.72 seconds
Started	Apr 28 12:56:47 PM PDT 24
Finished	Apr 28 12:56:48 PM PDT 24
Peak memory	200764 kb
Host	smart-f694bacf-5075-4baf-81c5-ab393317f8b8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248386094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.3248386094
Directory	/workspace/25.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/25.clkmgr_div_intersig_mubi.560492645
Short name	T612
Test name
Test status
Simulation time	15310468 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 12:56:50 PM PDT 24
Peak memory	200964 kb
Host	smart-eeb3450b-8d88-4000-afcb-805968aee58c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560492645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.clkmgr_div_intersig_mubi.560492645
Directory	/workspace/25.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_extclk.847485831
Short name	T537
Test name
Test status
Simulation time	41033644 ps
CPU time	0.86 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 12:56:57 PM PDT 24
Peak memory	200996 kb
Host	smart-35cd9a18-892b-471b-bb1c-ef73c5455253
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847485831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.847485831
Directory	/workspace/25.clkmgr_extclk/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency.4244695275
Short name	T17
Test name
Test status
Simulation time	2119835445 ps
CPU time	15.34 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:57:10 PM PDT 24
Peak memory	201172 kb
Host	smart-b2df4fcb-5750-42e3-9ef2-f7d94aac2c9b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244695275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.4244695275
Directory	/workspace/25.clkmgr_frequency/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency_timeout.2182204247
Short name	T196
Test name
Test status
Simulation time	2407554032 ps
CPU time	9.94 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:57:05 PM PDT 24
Peak memory	201212 kb
Host	smart-f6c6a6c8-0bd7-4d44-9d28-169b75558901
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182204247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t imeout.2182204247
Directory	/workspace/25.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/25.clkmgr_idle_intersig_mubi.2768945335
Short name	T453
Test name
Test status
Simulation time	35625443 ps
CPU time	0.99 seconds
Started	Apr 28 12:56:49 PM PDT 24
Finished	Apr 28 12:56:51 PM PDT 24
Peak memory	200912 kb
Host	smart-9b40e684-0270-44c8-998d-501f5c02593a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768945335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.2768945335
Directory	/workspace/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.4205385675
Short name	T763
Test name
Test status
Simulation time	184894178 ps
CPU time	1.27 seconds
Started	Apr 28 12:56:46 PM PDT 24
Finished	Apr 28 12:56:48 PM PDT 24
Peak memory	200976 kb
Host	smart-0985967e-3d04-4158-9836-2cab4b341eee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205385675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_clk_byp_req_intersig_mubi.4205385675
Directory	/workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.512751905
Short name	T696
Test name
Test status
Simulation time	43455597 ps
CPU time	0.93 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:57 PM PDT 24
Peak memory	200872 kb
Host	smart-042183b8-caa8-4bff-a68e-5f476adbed16
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512751905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.clkmgr_lc_ctrl_intersig_mubi.512751905
Directory	/workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_peri.1998943269
Short name	T465
Test name
Test status
Simulation time	35045231 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:45 PM PDT 24
Finished	Apr 28 12:56:47 PM PDT 24
Peak memory	200976 kb
Host	smart-ac8e0c50-4f9a-4399-86e3-d4022dcf9074
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998943269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.1998943269
Directory	/workspace/25.clkmgr_peri/latest

Test location	/workspace/coverage/default/25.clkmgr_regwen.3176338360
Short name	T634
Test name
Test status
Simulation time	789706341 ps
CPU time	4.96 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	201148 kb
Host	smart-5d7c59d6-4408-48b7-8b07-5de1d70fdcec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176338360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3176338360
Directory	/workspace/25.clkmgr_regwen/latest

Test location	/workspace/coverage/default/25.clkmgr_smoke.1105299273
Short name	T127
Test name
Test status
Simulation time	38101252 ps
CPU time	0.88 seconds
Started	Apr 28 12:56:53 PM PDT 24
Finished	Apr 28 12:56:55 PM PDT 24
Peak memory	201072 kb
Host	smart-8ff57e71-7fb2-4848-b9b6-2cee2c5193b1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105299273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.1105299273
Directory	/workspace/25.clkmgr_smoke/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all.2819580910
Short name	T705
Test name
Test status
Simulation time	6823376710 ps
CPU time	30.55 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	201168 kb
Host	smart-3127428f-282d-4cd5-8609-8290ba6d0474
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819580910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.2819580910
Directory	/workspace/25.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.42333491
Short name	T13
Test name
Test status
Simulation time	41957966356 ps
CPU time	643.39 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 01:07:33 PM PDT 24
Peak memory	211344 kb
Host	smart-18567143-b3f8-45b8-84d7-a852c9979637
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=42333491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.42333491
Directory	/workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.clkmgr_trans.2328879628
Short name	T840
Test name
Test status
Simulation time	30481434 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:55 PM PDT 24
Peak memory	201012 kb
Host	smart-6fff977d-13d4-4a28-9f57-1ea5d698682e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328879628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2328879628
Directory	/workspace/25.clkmgr_trans/latest

Test location	/workspace/coverage/default/26.clkmgr_alert_test.3216601410
Short name	T322
Test name
Test status
Simulation time	18096027 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:52 PM PDT 24
Finished	Apr 28 12:56:53 PM PDT 24
Peak memory	200948 kb
Host	smart-7fd6aeb3-12ad-43c3-8287-68c34f2f6607
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216601410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk mgr_alert_test.3216601410
Directory	/workspace/26.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2923296024
Short name	T469
Test name
Test status
Simulation time	22519371 ps
CPU time	0.81 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:56:59 PM PDT 24
Peak memory	200976 kb
Host	smart-26cf29bf-d33b-4eac-8513-330171942923
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923296024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.2923296024
Directory	/workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_status.628032672
Short name	T37
Test name
Test status
Simulation time	23091718 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:01 PM PDT 24
Peak memory	200012 kb
Host	smart-690e4765-263f-46c0-bbba-43ba15ed2b54
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628032672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.628032672
Directory	/workspace/26.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/26.clkmgr_div_intersig_mubi.2203185214
Short name	T474
Test name
Test status
Simulation time	69336273 ps
CPU time	0.95 seconds
Started	Apr 28 12:56:52 PM PDT 24
Finished	Apr 28 12:56:54 PM PDT 24
Peak memory	200896 kb
Host	smart-06272bec-1222-4e63-a463-3d1412fa42b9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203185214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.2203185214
Directory	/workspace/26.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_extclk.178224751
Short name	T785
Test name
Test status
Simulation time	129082345 ps
CPU time	1.1 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201004 kb
Host	smart-152368c2-d579-44a5-a323-a6645ad7877b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178224751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.178224751
Directory	/workspace/26.clkmgr_extclk/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency.3683406611
Short name	T261
Test name
Test status
Simulation time	1394603180 ps
CPU time	10.8 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:57:09 PM PDT 24
Peak memory	201020 kb
Host	smart-eac042b0-123c-49d2-94ee-1dbd216f3bcd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683406611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3683406611
Directory	/workspace/26.clkmgr_frequency/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency_timeout.2178078382
Short name	T219
Test name
Test status
Simulation time	269564892 ps
CPU time	1.74 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:57 PM PDT 24
Peak memory	201112 kb
Host	smart-c567d8e2-6b62-4e55-bc6f-a67607396356
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178078382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t imeout.2178078382
Directory	/workspace/26.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/26.clkmgr_idle_intersig_mubi.365290528
Short name	T454
Test name
Test status
Simulation time	143194455 ps
CPU time	1.34 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 12:56:58 PM PDT 24
Peak memory	200840 kb
Host	smart-abe591fb-784e-4943-8de2-ac3bc906ebce
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365290528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.clkmgr_idle_intersig_mubi.365290528
Directory	/workspace/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.459892836
Short name	T580
Test name
Test status
Simulation time	17947005 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:47 PM PDT 24
Finished	Apr 28 12:56:49 PM PDT 24
Peak memory	201000 kb
Host	smart-87306963-7f45-4d01-9abd-86af5879687b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459892836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.clkmgr_lc_clk_byp_req_intersig_mubi.459892836
Directory	/workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2510640800
Short name	T490
Test name
Test status
Simulation time	73973524 ps
CPU time	1.03 seconds
Started	Apr 28 12:56:51 PM PDT 24
Finished	Apr 28 12:56:53 PM PDT 24
Peak memory	200872 kb
Host	smart-1ba2eb47-938b-48da-9121-8decf4a05cae
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510640800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_ctrl_intersig_mubi.2510640800
Directory	/workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_peri.759933011
Short name	T277
Test name
Test status
Simulation time	36474572 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 12:56:57 PM PDT 24
Peak memory	200860 kb
Host	smart-cb6b8fdd-2ea5-4e92-9e39-277551db7254
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759933011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.759933011
Directory	/workspace/26.clkmgr_peri/latest

Test location	/workspace/coverage/default/26.clkmgr_regwen.110619279
Short name	T63
Test name
Test status
Simulation time	1072576438 ps
CPU time	4.26 seconds
Started	Apr 28 12:57:00 PM PDT 24
Finished	Apr 28 12:57:06 PM PDT 24
Peak memory	201032 kb
Host	smart-c3203600-a792-4966-84d3-81bb8e083565
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110619279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.110619279
Directory	/workspace/26.clkmgr_regwen/latest

Test location	/workspace/coverage/default/26.clkmgr_smoke.626608321
Short name	T726
Test name
Test status
Simulation time	18185744 ps
CPU time	0.84 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 12:56:57 PM PDT 24
Peak memory	200896 kb
Host	smart-e77821ba-03b6-4a49-b602-aa705445ad2d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626608321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.626608321
Directory	/workspace/26.clkmgr_smoke/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all.141785345
Short name	T550
Test name
Test status
Simulation time	7302971064 ps
CPU time	29.41 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:30 PM PDT 24
Peak memory	201404 kb
Host	smart-d4eec50d-d19e-42ad-b257-e675966406a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141785345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.141785345
Directory	/workspace/26.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.113479867
Short name	T661
Test name
Test status
Simulation time	184141984651 ps
CPU time	1202.36 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 01:16:59 PM PDT 24
Peak memory	216000 kb
Host	smart-ed1cb63c-49ee-4458-bbca-cbd8878e8599
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=113479867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.113479867
Directory	/workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.clkmgr_trans.3045805132
Short name	T602
Test name
Test status
Simulation time	21321251 ps
CPU time	0.85 seconds
Started	Apr 28 12:56:49 PM PDT 24
Finished	Apr 28 12:56:51 PM PDT 24
Peak memory	200840 kb
Host	smart-78e70ba6-b26b-40f0-813e-d8a69ab93055
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045805132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3045805132
Directory	/workspace/26.clkmgr_trans/latest

Test location	/workspace/coverage/default/27.clkmgr_alert_test.2476008697
Short name	T19
Test name
Test status
Simulation time	18819442 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 12:56:58 PM PDT 24
Peak memory	200952 kb
Host	smart-4c6ee771-5502-4d10-a401-eb360921480f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476008697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk mgr_alert_test.2476008697
Directory	/workspace/27.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1259983123
Short name	T464
Test name
Test status
Simulation time	41923110 ps
CPU time	0.84 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:56:59 PM PDT 24
Peak memory	200984 kb
Host	smart-03e13fb3-f3c7-4689-bf37-b082c56fd007
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259983123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.1259983123
Directory	/workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_status.1125631909
Short name	T142
Test name
Test status
Simulation time	38301659 ps
CPU time	0.75 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:56:59 PM PDT 24
Peak memory	200884 kb
Host	smart-0a118cc2-057b-45d7-8dd2-f91eade36dfc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125631909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1125631909
Directory	/workspace/27.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/27.clkmgr_div_intersig_mubi.3891387469
Short name	T228
Test name
Test status
Simulation time	37637370 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:01 PM PDT 24
Peak memory	200992 kb
Host	smart-bb588ea8-2173-4f4a-9283-ffac00a9b548
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891387469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.3891387469
Directory	/workspace/27.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_extclk.1092510521
Short name	T334
Test name
Test status
Simulation time	74071102 ps
CPU time	0.97 seconds
Started	Apr 28 12:56:53 PM PDT 24
Finished	Apr 28 12:56:54 PM PDT 24
Peak memory	200960 kb
Host	smart-0751b037-ccb5-480a-83f4-3eed84d0272e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092510521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.1092510521
Directory	/workspace/27.clkmgr_extclk/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency.3672154386
Short name	T510
Test name
Test status
Simulation time	921082646 ps
CPU time	6.18 seconds
Started	Apr 28 12:56:49 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201012 kb
Host	smart-7a9f89d4-0b2b-467a-8324-c349423b1400
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672154386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.3672154386
Directory	/workspace/27.clkmgr_frequency/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency_timeout.368856700
Short name	T584
Test name
Test status
Simulation time	2060881850 ps
CPU time	15.42 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:57:13 PM PDT 24
Peak memory	201164 kb
Host	smart-d0f5142e-109a-48c9-b6f0-61bfcca18b07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368856700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_ti meout.368856700
Directory	/workspace/27.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/27.clkmgr_idle_intersig_mubi.4067412660
Short name	T420
Test name
Test status
Simulation time	71069823 ps
CPU time	1.15 seconds
Started	Apr 28 12:56:52 PM PDT 24
Finished	Apr 28 12:56:54 PM PDT 24
Peak memory	200840 kb
Host	smart-887a5378-9a62-46f2-a103-fefefeb7f8e4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067412660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.4067412660
Directory	/workspace/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3596759953
Short name	T707
Test name
Test status
Simulation time	21723736 ps
CPU time	0.82 seconds
Started	Apr 28 12:57:00 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	200904 kb
Host	smart-58082730-966b-40dd-9920-ab478c820ab2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596759953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3596759953
Directory	/workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.1269117176
Short name	T822
Test name
Test status
Simulation time	27339777 ps
CPU time	0.76 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:56:58 PM PDT 24
Peak memory	200900 kb
Host	smart-063b6d06-844c-49ac-b6e1-f3c6c4783329
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269117176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_ctrl_intersig_mubi.1269117176
Directory	/workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_peri.2444639376
Short name	T195
Test name
Test status
Simulation time	48432409 ps
CPU time	0.84 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	200900 kb
Host	smart-2970c80c-656d-4095-b9b2-3e980eb9b175
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444639376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.2444639376
Directory	/workspace/27.clkmgr_peri/latest

Test location	/workspace/coverage/default/27.clkmgr_regwen.1911505623
Short name	T10
Test name
Test status
Simulation time	1088195618 ps
CPU time	6.01 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 12:57:06 PM PDT 24
Peak memory	201188 kb
Host	smart-6edb2556-3167-4cd8-83f7-bb19d776a333
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911505623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1911505623
Directory	/workspace/27.clkmgr_regwen/latest

Test location	/workspace/coverage/default/27.clkmgr_smoke.3111808522
Short name	T410
Test name
Test status
Simulation time	24677992 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 12:56:49 PM PDT 24
Peak memory	201072 kb
Host	smart-fe33c647-7118-42d9-b85c-166e0a405bf5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111808522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3111808522
Directory	/workspace/27.clkmgr_smoke/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all.1658174067
Short name	T794
Test name
Test status
Simulation time	5145473360 ps
CPU time	37.82 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 12:57:35 PM PDT 24
Peak memory	201204 kb
Host	smart-40425624-0ff1-45f4-a9e2-bc3b3704ebc2
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658174067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.1658174067
Directory	/workspace/27.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/27.clkmgr_trans.3392281853
Short name	T369
Test name
Test status
Simulation time	38787282 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:48 PM PDT 24
Finished	Apr 28 12:56:50 PM PDT 24
Peak memory	201012 kb
Host	smart-2c48e462-d6f3-4fcc-ab2e-7eb57905e4e1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392281853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.3392281853
Directory	/workspace/27.clkmgr_trans/latest

Test location	/workspace/coverage/default/28.clkmgr_alert_test.3489779385
Short name	T223
Test name
Test status
Simulation time	62375125 ps
CPU time	0.91 seconds
Started	Apr 28 12:57:01 PM PDT 24
Finished	Apr 28 12:57:03 PM PDT 24
Peak memory	201020 kb
Host	smart-0c8de039-4c9a-44a9-a9f1-3d616cb60f83
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489779385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk mgr_alert_test.3489779385
Directory	/workspace/28.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.1862797744
Short name	T129
Test name
Test status
Simulation time	25635707 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:56:58 PM PDT 24
Peak memory	201000 kb
Host	smart-a959616d-7573-4b8b-b23f-654041904106
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862797744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.1862797744
Directory	/workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_status.160762324
Short name	T337
Test name
Test status
Simulation time	16988290 ps
CPU time	0.69 seconds
Started	Apr 28 12:57:00 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	199896 kb
Host	smart-f8e099ce-3e2d-426f-97d7-5044980f8608
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160762324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.160762324
Directory	/workspace/28.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/28.clkmgr_div_intersig_mubi.2496822696
Short name	T180
Test name
Test status
Simulation time	65386478 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	200936 kb
Host	smart-20d6447a-73ae-402e-9b61-423d9b691da5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496822696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.2496822696
Directory	/workspace/28.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_extclk.4288721662
Short name	T779
Test name
Test status
Simulation time	21817190 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:55 PM PDT 24
Finished	Apr 28 12:56:58 PM PDT 24
Peak memory	200896 kb
Host	smart-697d530b-259d-42a1-8421-65017e7c9c3c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288721662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.4288721662
Directory	/workspace/28.clkmgr_extclk/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency.449688478
Short name	T808
Test name
Test status
Simulation time	2508598714 ps
CPU time	8.49 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:57:07 PM PDT 24
Peak memory	201104 kb
Host	smart-5eb1db69-7a5c-4344-abfc-941e31572c59
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449688478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.449688478
Directory	/workspace/28.clkmgr_frequency/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency_timeout.1561320150
Short name	T747
Test name
Test status
Simulation time	2060339069 ps
CPU time	14.68 seconds
Started	Apr 28 12:57:01 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	201104 kb
Host	smart-4f780c24-c365-4411-855d-c67c5ca8120b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561320150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t imeout.1561320150
Directory	/workspace/28.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/28.clkmgr_idle_intersig_mubi.2633175405
Short name	T757
Test name
Test status
Simulation time	44075780 ps
CPU time	0.96 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	200932 kb
Host	smart-913d90b8-0b28-42a5-b6b9-8be75a9b68df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633175405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.2633175405
Directory	/workspace/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.4249082872
Short name	T131
Test name
Test status
Simulation time	20004764 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:01 PM PDT 24
Peak memory	200812 kb
Host	smart-56eaa329-80f0-4c89-9c76-5cc929558f60
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249082872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_clk_byp_req_intersig_mubi.4249082872
Directory	/workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.3146550730
Short name	T392
Test name
Test status
Simulation time	52333288 ps
CPU time	0.89 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:56:58 PM PDT 24
Peak memory	201012 kb
Host	smart-d640d508-7f0d-496a-956c-4b01d75e2dc9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146550730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_ctrl_intersig_mubi.3146550730
Directory	/workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_peri.2085081974
Short name	T47
Test name
Test status
Simulation time	38164719 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:56:59 PM PDT 24
Peak memory	200868 kb
Host	smart-4bcd3af2-ea33-466c-a8dd-b6f1eac51abd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085081974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2085081974
Directory	/workspace/28.clkmgr_peri/latest

Test location	/workspace/coverage/default/28.clkmgr_regwen.621877836
Short name	T522
Test name
Test status
Simulation time	633885885 ps
CPU time	3.12 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:03 PM PDT 24
Peak memory	200984 kb
Host	smart-6646030c-cab1-4ab2-af4c-acd6a27b51c5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621877836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.621877836
Directory	/workspace/28.clkmgr_regwen/latest

Test location	/workspace/coverage/default/28.clkmgr_smoke.1498612632
Short name	T162
Test name
Test status
Simulation time	48047455 ps
CPU time	0.91 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	200948 kb
Host	smart-75511d60-f887-445f-8243-d9e9656aee8e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498612632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1498612632
Directory	/workspace/28.clkmgr_smoke/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all.4047939549
Short name	T697
Test name
Test status
Simulation time	2301319844 ps
CPU time	17.54 seconds
Started	Apr 28 12:57:03 PM PDT 24
Finished	Apr 28 12:57:21 PM PDT 24
Peak memory	201344 kb
Host	smart-9e338841-3b51-406f-ad35-adeba325c355
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047939549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.4047939549
Directory	/workspace/28.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.3271500992
Short name	T851
Test name
Test status
Simulation time	163938529078 ps
CPU time	946.91 seconds
Started	Apr 28 12:56:53 PM PDT 24
Finished	Apr 28 01:12:41 PM PDT 24
Peak memory	209672 kb
Host	smart-9505dd00-ff79-4153-9729-f957312d7d87
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3271500992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3271500992
Directory	/workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.clkmgr_trans.950320093
Short name	T512
Test name
Test status
Simulation time	282775458 ps
CPU time	1.58 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	200924 kb
Host	smart-1bd99ced-c21f-4fff-a1c6-3f2801a5d00a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950320093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.950320093
Directory	/workspace/28.clkmgr_trans/latest

Test location	/workspace/coverage/default/29.clkmgr_alert_test.731705965
Short name	T565
Test name
Test status
Simulation time	16184857 ps
CPU time	0.76 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 12:57:00 PM PDT 24
Peak memory	200912 kb
Host	smart-13df2cb7-49bd-44e4-ac64-4729da3add35
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731705965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkm gr_alert_test.731705965
Directory	/workspace/29.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.875334586
Short name	T82
Test name
Test status
Simulation time	27478846 ps
CPU time	0.93 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:56:56 PM PDT 24
Peak memory	201004 kb
Host	smart-a1933500-398f-4484-ae75-e6ba7e2d016e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875334586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.875334586
Directory	/workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_status.2642044514
Short name	T541
Test name
Test status
Simulation time	18652633 ps
CPU time	0.71 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	199916 kb
Host	smart-8b933ad8-7802-4d44-b55e-e42822198531
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642044514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2642044514
Directory	/workspace/29.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/29.clkmgr_div_intersig_mubi.3989604446
Short name	T332
Test name
Test status
Simulation time	75794494 ps
CPU time	0.98 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 12:57:01 PM PDT 24
Peak memory	201036 kb
Host	smart-89f5d619-70fe-48d4-882e-950c35674dea
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989604446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.3989604446
Directory	/workspace/29.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_extclk.1297364188
Short name	T704
Test name
Test status
Simulation time	81422196 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:03 PM PDT 24
Finished	Apr 28 12:57:04 PM PDT 24
Peak memory	200996 kb
Host	smart-a71863a4-3256-4427-8865-9a8d4205b6d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297364188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1297364188
Directory	/workspace/29.clkmgr_extclk/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency.2057849146
Short name	T507
Test name
Test status
Simulation time	1671598658 ps
CPU time	7.64 seconds
Started	Apr 28 12:56:54 PM PDT 24
Finished	Apr 28 12:57:03 PM PDT 24
Peak memory	201076 kb
Host	smart-5ab2f883-9800-417b-af7e-8387bb0a4a71
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057849146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2057849146
Directory	/workspace/29.clkmgr_frequency/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency_timeout.1632917455
Short name	T30
Test name
Test status
Simulation time	2443423978 ps
CPU time	10.23 seconds
Started	Apr 28 12:56:56 PM PDT 24
Finished	Apr 28 12:57:08 PM PDT 24
Peak memory	201260 kb
Host	smart-1f3192a3-d877-4ff0-af57-f39a83c8fb07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632917455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t imeout.1632917455
Directory	/workspace/29.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/29.clkmgr_idle_intersig_mubi.2071629848
Short name	T97
Test name
Test status
Simulation time	34210041 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	200988 kb
Host	smart-4ebf1e37-1121-4a8a-a9d9-306c037a8178
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071629848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.2071629848
Directory	/workspace/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1429284128
Short name	T485
Test name
Test status
Simulation time	26566329 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:01 PM PDT 24
Peak memory	201000 kb
Host	smart-986b1b73-164e-458c-962a-3b745dfd58c6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429284128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1429284128
Directory	/workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.2935225490
Short name	T618
Test name
Test status
Simulation time	16783425 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:02 PM PDT 24
Finished	Apr 28 12:57:04 PM PDT 24
Peak memory	201004 kb
Host	smart-3a95f30d-5bbd-4c70-8c58-9693001eec21
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935225490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_ctrl_intersig_mubi.2935225490
Directory	/workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_peri.3780912046
Short name	T824
Test name
Test status
Simulation time	23708721 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	200996 kb
Host	smart-62d9414e-64aa-436c-8dcf-b0e2dbc095f2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780912046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.3780912046
Directory	/workspace/29.clkmgr_peri/latest

Test location	/workspace/coverage/default/29.clkmgr_regwen.2339515798
Short name	T270
Test name
Test status
Simulation time	833717663 ps
CPU time	3.91 seconds
Started	Apr 28 12:57:00 PM PDT 24
Finished	Apr 28 12:57:05 PM PDT 24
Peak memory	201116 kb
Host	smart-ad103229-4e1d-42ed-b8c3-75f567d81b50
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339515798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2339515798
Directory	/workspace/29.clkmgr_regwen/latest

Test location	/workspace/coverage/default/29.clkmgr_smoke.3278800063
Short name	T441
Test name
Test status
Simulation time	38086341 ps
CPU time	0.9 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	200908 kb
Host	smart-964c839e-5c98-4e2d-bdbf-cd4446f8a5fd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278800063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.3278800063
Directory	/workspace/29.clkmgr_smoke/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all.3312266798
Short name	T570
Test name
Test status
Simulation time	9678446881 ps
CPU time	68.23 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:58:09 PM PDT 24
Peak memory	201392 kb
Host	smart-addfc552-7179-4698-953f-a97d08e49eb3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312266798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.3312266798
Directory	/workspace/29.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.614702087
Short name	T215
Test name
Test status
Simulation time	20461690141 ps
CPU time	211.43 seconds
Started	Apr 28 12:56:57 PM PDT 24
Finished	Apr 28 01:00:30 PM PDT 24
Peak memory	209508 kb
Host	smart-583471ca-114a-4dc7-a8b9-f63b9b2beb77
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=614702087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.614702087
Directory	/workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.clkmgr_trans.1893676910
Short name	T186
Test name
Test status
Simulation time	84220696 ps
CPU time	0.86 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	201004 kb
Host	smart-e6052fb7-5056-4243-8030-468209878faa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893676910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.1893676910
Directory	/workspace/29.clkmgr_trans/latest

Test location	/workspace/coverage/default/3.clkmgr_alert_test.1109430205
Short name	T248
Test name
Test status
Simulation time	14220943 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:02 PM PDT 24
Peak memory	201028 kb
Host	smart-dd3f9e94-325f-4668-97c1-eaa4dbc4173c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109430205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm gr_alert_test.1109430205
Directory	/workspace/3.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1505831595
Short name	T199
Test name
Test status
Simulation time	20595068 ps
CPU time	0.89 seconds
Started	Apr 28 12:56:00 PM PDT 24
Finished	Apr 28 12:56:02 PM PDT 24
Peak memory	200952 kb
Host	smart-752ffbeb-1b2b-4ad8-bd2d-a939bcb94d8d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505831595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.1505831595
Directory	/workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_status.1249207699
Short name	T614
Test name
Test status
Simulation time	13878750 ps
CPU time	0.71 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:00 PM PDT 24
Peak memory	200020 kb
Host	smart-c0824afb-7732-4a55-9e55-1c4ada0075f4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249207699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.1249207699
Directory	/workspace/3.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/3.clkmgr_div_intersig_mubi.3099825663
Short name	T649
Test name
Test status
Simulation time	28173733 ps
CPU time	0.95 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	200992 kb
Host	smart-1e4d8742-f55a-4912-b103-8202da36a89b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099825663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.3099825663
Directory	/workspace/3.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_extclk.1241243642
Short name	T405
Test name
Test status
Simulation time	66259997 ps
CPU time	0.97 seconds
Started	Apr 28 12:55:57 PM PDT 24
Finished	Apr 28 12:55:59 PM PDT 24
Peak memory	200988 kb
Host	smart-e5f801c0-aef4-46e4-a8e6-b3be6eef50d9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241243642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1241243642
Directory	/workspace/3.clkmgr_extclk/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency.3862727767
Short name	T399
Test name
Test status
Simulation time	1776247928 ps
CPU time	7.77 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	201148 kb
Host	smart-5c6c80dc-71e7-4ad6-a3fe-9b6d17c74d89
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862727767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.3862727767
Directory	/workspace/3.clkmgr_frequency/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency_timeout.2215108293
Short name	T204
Test name
Test status
Simulation time	1707909464 ps
CPU time	7.53 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	201104 kb
Host	smart-9889c668-1a3f-4b8f-8674-102659fbaadd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215108293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti meout.2215108293
Directory	/workspace/3.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/3.clkmgr_idle_intersig_mubi.2998173033
Short name	T150
Test name
Test status
Simulation time	26820349 ps
CPU time	0.89 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:00 PM PDT 24
Peak memory	200840 kb
Host	smart-192b5cfb-abc2-4d94-806e-2baec6457c09
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998173033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.2998173033
Directory	/workspace/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.2852038670
Short name	T315
Test name
Test status
Simulation time	29381469 ps
CPU time	0.84 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	201044 kb
Host	smart-f3d51705-b5e8-4460-92b8-9ca97caf4f5b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852038670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_clk_byp_req_intersig_mubi.2852038670
Directory	/workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3834139764
Short name	T231
Test name
Test status
Simulation time	17753169 ps
CPU time	0.79 seconds
Started	Apr 28 12:55:57 PM PDT 24
Finished	Apr 28 12:55:59 PM PDT 24
Peak memory	200880 kb
Host	smart-311cc766-2cd7-4e8c-aec8-1201a96149bb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834139764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_ctrl_intersig_mubi.3834139764
Directory	/workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_peri.659262448
Short name	T738
Test name
Test status
Simulation time	28778835 ps
CPU time	0.8 seconds
Started	Apr 28 12:55:56 PM PDT 24
Finished	Apr 28 12:55:58 PM PDT 24
Peak memory	200872 kb
Host	smart-2b521b0f-ab64-4ba2-9b0c-6e1602c35aa7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659262448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.659262448
Directory	/workspace/3.clkmgr_peri/latest

Test location	/workspace/coverage/default/3.clkmgr_regwen.3499012122
Short name	T609
Test name
Test status
Simulation time	192115749 ps
CPU time	1.38 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	200940 kb
Host	smart-69466132-0406-49a6-b91a-0ed21c0d2fb2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499012122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3499012122
Directory	/workspace/3.clkmgr_regwen/latest

Test location	/workspace/coverage/default/3.clkmgr_sec_cm.4124323200
Short name	T49
Test name
Test status
Simulation time	444868399 ps
CPU time	2.62 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:56:03 PM PDT 24
Peak memory	216132 kb
Host	smart-42eb2a8f-7f50-400f-b153-ee901b8d95fb
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124323200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg r_sec_cm.4124323200
Directory	/workspace/3.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/3.clkmgr_smoke.1262582674
Short name	T424
Test name
Test status
Simulation time	21073306 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:00 PM PDT 24
Finished	Apr 28 12:56:01 PM PDT 24
Peak memory	200968 kb
Host	smart-6e54fbfb-0407-40d2-a523-2e803b5d365d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262582674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.1262582674
Directory	/workspace/3.clkmgr_smoke/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all.3411606015
Short name	T98
Test name
Test status
Simulation time	9691142836 ps
CPU time	70.72 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:57:11 PM PDT 24
Peak memory	201300 kb
Host	smart-f1fada90-bc7a-4f2c-a491-d6a502d666db
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411606015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.3411606015
Directory	/workspace/3.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.3776014050
Short name	T136
Test name
Test status
Simulation time	76830317826 ps
CPU time	668.69 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 01:07:08 PM PDT 24
Peak memory	209544 kb
Host	smart-0459c522-88ce-4dbf-8636-9e6472588080
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3776014050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.3776014050
Directory	/workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.clkmgr_trans.3475011253
Short name	T285
Test name
Test status
Simulation time	24962927 ps
CPU time	0.94 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:00 PM PDT 24
Peak memory	200940 kb
Host	smart-087edd36-af0c-4842-a313-19b51bd3b67a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475011253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3475011253
Directory	/workspace/3.clkmgr_trans/latest

Test location	/workspace/coverage/default/30.clkmgr_alert_test.2825462407
Short name	T845
Test name
Test status
Simulation time	15888833 ps
CPU time	0.7 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:09 PM PDT 24
Peak memory	200944 kb
Host	smart-5d58b914-476f-4b9e-a1a7-3bcbe8a8aa40
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825462407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk mgr_alert_test.2825462407
Directory	/workspace/30.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1461363844
Short name	T442
Test name
Test status
Simulation time	79775298 ps
CPU time	1 seconds
Started	Apr 28 12:57:01 PM PDT 24
Finished	Apr 28 12:57:04 PM PDT 24
Peak memory	200868 kb
Host	smart-a8812d2e-a03c-40ef-9f96-300bb1510156
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461363844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.1461363844
Directory	/workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_status.1552527481
Short name	T579
Test name
Test status
Simulation time	17334118 ps
CPU time	0.83 seconds
Started	Apr 28 12:57:02 PM PDT 24
Finished	Apr 28 12:57:04 PM PDT 24
Peak memory	199860 kb
Host	smart-cced4026-3593-4866-a971-d09dc9aec54d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552527481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.1552527481
Directory	/workspace/30.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/30.clkmgr_div_intersig_mubi.2712607419
Short name	T216
Test name
Test status
Simulation time	35931113 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:03 PM PDT 24
Finished	Apr 28 12:57:04 PM PDT 24
Peak memory	200996 kb
Host	smart-e4a93d24-b890-4405-a7d1-e4adc36b1b67
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712607419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.2712607419
Directory	/workspace/30.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_extclk.747614221
Short name	T313
Test name
Test status
Simulation time	18549998 ps
CPU time	0.86 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	200896 kb
Host	smart-1449de00-0803-4d03-93cc-aa0964c271ec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747614221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.747614221
Directory	/workspace/30.clkmgr_extclk/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency.3477744410
Short name	T2
Test name
Test status
Simulation time	1922687621 ps
CPU time	7.04 seconds
Started	Apr 28 12:57:01 PM PDT 24
Finished	Apr 28 12:57:10 PM PDT 24
Peak memory	201224 kb
Host	smart-fa78583b-b5c2-4c6f-9f27-790d818368b4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477744410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3477744410
Directory	/workspace/30.clkmgr_frequency/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency_timeout.440734073
Short name	T819
Test name
Test status
Simulation time	1693556173 ps
CPU time	12.6 seconds
Started	Apr 28 12:57:00 PM PDT 24
Finished	Apr 28 12:57:14 PM PDT 24
Peak memory	201112 kb
Host	smart-ee43aaa8-3165-4ebf-b999-bd970a7e9406
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440734073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_ti meout.440734073
Directory	/workspace/30.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/30.clkmgr_idle_intersig_mubi.4238622719
Short name	T675
Test name
Test status
Simulation time	14631275 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:03 PM PDT 24
Finished	Apr 28 12:57:04 PM PDT 24
Peak memory	201016 kb
Host	smart-3ca124ad-0d43-4443-af7a-302f227943ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238622719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.4238622719
Directory	/workspace/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.3492943188
Short name	T731
Test name
Test status
Simulation time	185781412 ps
CPU time	1.24 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 12:57:01 PM PDT 24
Peak memory	200884 kb
Host	smart-a16c3e68-8864-44dc-9ec9-27184d513414
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492943188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_clk_byp_req_intersig_mubi.3492943188
Directory	/workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.461589456
Short name	T354
Test name
Test status
Simulation time	28267829 ps
CPU time	0.88 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	200836 kb
Host	smart-ea7e107c-88a6-4d01-9538-b71fd6aca9e2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461589456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.clkmgr_lc_ctrl_intersig_mubi.461589456
Directory	/workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_peri.1912135210
Short name	T153
Test name
Test status
Simulation time	18779485 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:00 PM PDT 24
Finished	Apr 28 12:57:02 PM PDT 24
Peak memory	200804 kb
Host	smart-f777368e-846d-4f6d-a2a6-c72efa39ba04
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912135210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.1912135210
Directory	/workspace/30.clkmgr_peri/latest

Test location	/workspace/coverage/default/30.clkmgr_regwen.4009374330
Short name	T525
Test name
Test status
Simulation time	1877839001 ps
CPU time	5.56 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:06 PM PDT 24
Peak memory	201112 kb
Host	smart-1caf9c13-82d5-4db1-8603-5223e9a0c887
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009374330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.4009374330
Directory	/workspace/30.clkmgr_regwen/latest

Test location	/workspace/coverage/default/30.clkmgr_smoke.2772304315
Short name	T411
Test name
Test status
Simulation time	17373788 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:59 PM PDT 24
Finished	Apr 28 12:57:01 PM PDT 24
Peak memory	200912 kb
Host	smart-78ae3eab-30e1-4969-9562-110f79b301fb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772304315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.2772304315
Directory	/workspace/30.clkmgr_smoke/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all.3382624305
Short name	T597
Test name
Test status
Simulation time	6454607686 ps
CPU time	46.96 seconds
Started	Apr 28 12:57:01 PM PDT 24
Finished	Apr 28 12:57:49 PM PDT 24
Peak memory	201300 kb
Host	smart-ed1eeb87-6e33-4180-926a-532b587466ef
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382624305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.3382624305
Directory	/workspace/30.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.3462459298
Short name	T592
Test name
Test status
Simulation time	85361090534 ps
CPU time	453.87 seconds
Started	Apr 28 12:56:58 PM PDT 24
Finished	Apr 28 01:04:34 PM PDT 24
Peak memory	217848 kb
Host	smart-dfc6d17c-05be-4218-8e82-47007e092873
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3462459298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.3462459298
Directory	/workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.clkmgr_trans.4166760548
Short name	T149
Test name
Test status
Simulation time	92868131 ps
CPU time	1.01 seconds
Started	Apr 28 12:57:00 PM PDT 24
Finished	Apr 28 12:57:03 PM PDT 24
Peak memory	201000 kb
Host	smart-d4690c94-d776-45d5-b304-ebc73d1a4a21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166760548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.4166760548
Directory	/workspace/30.clkmgr_trans/latest

Test location	/workspace/coverage/default/31.clkmgr_alert_test.3534166236
Short name	T370
Test name
Test status
Simulation time	101352846 ps
CPU time	1.01 seconds
Started	Apr 28 12:57:05 PM PDT 24
Finished	Apr 28 12:57:07 PM PDT 24
Peak memory	200872 kb
Host	smart-d0c35377-1bec-44f5-9d37-ec25affc6ce6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534166236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk mgr_alert_test.3534166236
Directory	/workspace/31.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.963783167
Short name	T834
Test name
Test status
Simulation time	23478138 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:22 PM PDT 24
Finished	Apr 28 12:57:24 PM PDT 24
Peak memory	200976 kb
Host	smart-8064961d-c745-4e42-b69d-3c15084d2370
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963783167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.963783167
Directory	/workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_status.115056133
Short name	T569
Test name
Test status
Simulation time	43954671 ps
CPU time	0.74 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:09 PM PDT 24
Peak memory	200840 kb
Host	smart-9c0c09fb-db29-4fcf-8fd4-3fc76a60861d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115056133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.115056133
Directory	/workspace/31.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/31.clkmgr_div_intersig_mubi.2251377318
Short name	T297
Test name
Test status
Simulation time	23470790 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:04 PM PDT 24
Finished	Apr 28 12:57:05 PM PDT 24
Peak memory	200896 kb
Host	smart-23e3e293-54d6-4e91-aa30-e1d7538d6cbd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251377318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.2251377318
Directory	/workspace/31.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_extclk.2571117571
Short name	T178
Test name
Test status
Simulation time	31736315 ps
CPU time	0.89 seconds
Started	Apr 28 12:57:04 PM PDT 24
Finished	Apr 28 12:57:06 PM PDT 24
Peak memory	200840 kb
Host	smart-c60d24ed-54c9-4685-962a-06a83ee6e0d5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571117571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2571117571
Directory	/workspace/31.clkmgr_extclk/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency.3766447797
Short name	T564
Test name
Test status
Simulation time	2545745140 ps
CPU time	9.42 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	201308 kb
Host	smart-81d0c270-6d0b-44ad-8ecf-a34e3d840d02
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766447797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.3766447797
Directory	/workspace/31.clkmgr_frequency/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency_timeout.4277775137
Short name	T267
Test name
Test status
Simulation time	844209263 ps
CPU time	3.06 seconds
Started	Apr 28 12:57:02 PM PDT 24
Finished	Apr 28 12:57:06 PM PDT 24
Peak memory	201052 kb
Host	smart-76ab6821-032e-466f-9e08-58293adb692c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277775137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t imeout.4277775137
Directory	/workspace/31.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/31.clkmgr_idle_intersig_mubi.3938738470
Short name	T327
Test name
Test status
Simulation time	31613061 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:08 PM PDT 24
Peak memory	200884 kb
Host	smart-7c2f0137-566c-414f-83c0-de6e8eee954c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938738470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.3938738470
Directory	/workspace/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2779857517
Short name	T749
Test name
Test status
Simulation time	35207508 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:08 PM PDT 24
Finished	Apr 28 12:57:11 PM PDT 24
Peak memory	200980 kb
Host	smart-c6d8edbf-4761-488c-a27e-ef6a14fce7d6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779857517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_clk_byp_req_intersig_mubi.2779857517
Directory	/workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2941826673
Short name	T801
Test name
Test status
Simulation time	130537783 ps
CPU time	1.18 seconds
Started	Apr 28 12:57:19 PM PDT 24
Finished	Apr 28 12:57:20 PM PDT 24
Peak memory	200948 kb
Host	smart-190a7ff3-e905-4867-bee4-394296e45de6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941826673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_ctrl_intersig_mubi.2941826673
Directory	/workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_peri.2523231431
Short name	T418
Test name
Test status
Simulation time	21379784 ps
CPU time	0.76 seconds
Started	Apr 28 12:57:01 PM PDT 24
Finished	Apr 28 12:57:03 PM PDT 24
Peak memory	200936 kb
Host	smart-7fa42760-b0f0-4029-9323-b4713e4b3d1a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523231431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.2523231431
Directory	/workspace/31.clkmgr_peri/latest

Test location	/workspace/coverage/default/31.clkmgr_regwen.1667650960
Short name	T672
Test name
Test status
Simulation time	979446465 ps
CPU time	3.78 seconds
Started	Apr 28 12:57:03 PM PDT 24
Finished	Apr 28 12:57:08 PM PDT 24
Peak memory	200984 kb
Host	smart-c453bc10-46b1-4fdd-972a-684d92a1dc59
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667650960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.1667650960
Directory	/workspace/31.clkmgr_regwen/latest

Test location	/workspace/coverage/default/31.clkmgr_smoke.3862071084
Short name	T263
Test name
Test status
Simulation time	344300407 ps
CPU time	1.69 seconds
Started	Apr 28 12:57:01 PM PDT 24
Finished	Apr 28 12:57:04 PM PDT 24
Peak memory	201048 kb
Host	smart-d2112596-8282-4748-9378-5875189f6869
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862071084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.3862071084
Directory	/workspace/31.clkmgr_smoke/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all.2836874925
Short name	T227
Test name
Test status
Simulation time	4027485577 ps
CPU time	30.75 seconds
Started	Apr 28 12:57:18 PM PDT 24
Finished	Apr 28 12:57:49 PM PDT 24
Peak memory	201064 kb
Host	smart-f5f62d8e-4c25-43f8-826e-31a1c114f51c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836874925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.2836874925
Directory	/workspace/31.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.1487392981
Short name	T221
Test name
Test status
Simulation time	43113685459 ps
CPU time	247.8 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 01:01:22 PM PDT 24
Peak memory	216304 kb
Host	smart-f8ddb41a-b378-44ec-b13d-8419d2e4a64d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1487392981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.1487392981
Directory	/workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.clkmgr_trans.1491471446
Short name	T319
Test name
Test status
Simulation time	90326189 ps
CPU time	1.1 seconds
Started	Apr 28 12:57:08 PM PDT 24
Finished	Apr 28 12:57:10 PM PDT 24
Peak memory	200872 kb
Host	smart-07b4b0bc-6d61-4244-b630-12701bc1eeca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491471446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1491471446
Directory	/workspace/31.clkmgr_trans/latest

Test location	/workspace/coverage/default/32.clkmgr_alert_test.695924455
Short name	T699
Test name
Test status
Simulation time	34811164 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:16 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	201004 kb
Host	smart-2914c3c4-ebcd-42fa-9359-266136902845
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695924455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkm gr_alert_test.695924455
Directory	/workspace/32.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.1491293007
Short name	T554
Test name
Test status
Simulation time	96800705 ps
CPU time	1.04 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:10 PM PDT 24
Peak memory	200892 kb
Host	smart-8681e588-056c-43ce-b502-1506533fdfac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491293007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.1491293007
Directory	/workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_status.2562479893
Short name	T746
Test name
Test status
Simulation time	22395704 ps
CPU time	0.72 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:09 PM PDT 24
Peak memory	199860 kb
Host	smart-c0e49b3d-72c0-452a-9996-1923caf5edc6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562479893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.2562479893
Directory	/workspace/32.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/32.clkmgr_div_intersig_mubi.3138365419
Short name	T659
Test name
Test status
Simulation time	40944952 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:25 PM PDT 24
Peak memory	200988 kb
Host	smart-afb72b77-b908-4c47-9f6b-e83f0490b280
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138365419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.3138365419
Directory	/workspace/32.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_extclk.1168112502
Short name	T62
Test name
Test status
Simulation time	166319469 ps
CPU time	1.17 seconds
Started	Apr 28 12:57:09 PM PDT 24
Finished	Apr 28 12:57:11 PM PDT 24
Peak memory	200964 kb
Host	smart-1b7305d7-2e83-4003-9fda-de33a63207bb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168112502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1168112502
Directory	/workspace/32.clkmgr_extclk/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency.3306667951
Short name	T255
Test name
Test status
Simulation time	1044442815 ps
CPU time	7.72 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	201040 kb
Host	smart-e06b4668-249b-4002-85ce-b84a0e0a4ade
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306667951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.3306667951
Directory	/workspace/32.clkmgr_frequency/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency_timeout.2455967516
Short name	T753
Test name
Test status
Simulation time	417353097 ps
CPU time	2.08 seconds
Started	Apr 28 12:57:10 PM PDT 24
Finished	Apr 28 12:57:14 PM PDT 24
Peak memory	200920 kb
Host	smart-b7aaa114-e531-48d5-add8-d990b7d3b659
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455967516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t imeout.2455967516
Directory	/workspace/32.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/32.clkmgr_idle_intersig_mubi.3904279946
Short name	T375
Test name
Test status
Simulation time	79328964 ps
CPU time	1 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	200992 kb
Host	smart-e664198b-4844-424c-a8f3-c952bd9af39a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904279946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.3904279946
Directory	/workspace/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1019585449
Short name	T359
Test name
Test status
Simulation time	25699229 ps
CPU time	0.89 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:15 PM PDT 24
Peak memory	200992 kb
Host	smart-5741f130-81bd-4ffa-8d9e-b86ec1185229
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019585449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_clk_byp_req_intersig_mubi.1019585449
Directory	/workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2565078800
Short name	T636
Test name
Test status
Simulation time	217013505 ps
CPU time	1.67 seconds
Started	Apr 28 12:57:06 PM PDT 24
Finished	Apr 28 12:57:09 PM PDT 24
Peak memory	201040 kb
Host	smart-030ad403-9c8e-499d-9131-000cb19bfd39
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565078800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_ctrl_intersig_mubi.2565078800
Directory	/workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_peri.404761245
Short name	T758
Test name
Test status
Simulation time	25087862 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:15 PM PDT 24
Peak memory	200992 kb
Host	smart-3e0f996a-37d5-4c0e-ba02-cc77b3649ba8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404761245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.404761245
Directory	/workspace/32.clkmgr_peri/latest

Test location	/workspace/coverage/default/32.clkmgr_regwen.161498160
Short name	T377
Test name
Test status
Simulation time	75573240 ps
CPU time	0.97 seconds
Started	Apr 28 12:57:04 PM PDT 24
Finished	Apr 28 12:57:05 PM PDT 24
Peak memory	200900 kb
Host	smart-613de3ff-d227-4f22-91e5-c9f4478387f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161498160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.161498160
Directory	/workspace/32.clkmgr_regwen/latest

Test location	/workspace/coverage/default/32.clkmgr_smoke.3230208599
Short name	T214
Test name
Test status
Simulation time	86425992 ps
CPU time	1.05 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:15 PM PDT 24
Peak memory	201032 kb
Host	smart-358a809e-c3c0-45f7-86d1-1a0a584edbdd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230208599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3230208599
Directory	/workspace/32.clkmgr_smoke/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all.862001795
Short name	T762
Test name
Test status
Simulation time	6337855592 ps
CPU time	24.42 seconds
Started	Apr 28 12:57:17 PM PDT 24
Finished	Apr 28 12:57:42 PM PDT 24
Peak memory	201340 kb
Host	smart-d3852ae5-6c3c-437b-a7b8-4ba53f76943b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862001795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.862001795
Directory	/workspace/32.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.390584397
Short name	T768
Test name
Test status
Simulation time	48112911903 ps
CPU time	412.53 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 01:04:08 PM PDT 24
Peak memory	209680 kb
Host	smart-be7be01b-a715-49f1-bd0e-0c89a3fa477a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=390584397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.390584397
Directory	/workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.clkmgr_trans.1799751293
Short name	T407
Test name
Test status
Simulation time	25778062 ps
CPU time	0.9 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	200984 kb
Host	smart-40d57cd1-b349-48da-ae46-2b0ef3913625
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799751293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1799751293
Directory	/workspace/32.clkmgr_trans/latest

Test location	/workspace/coverage/default/33.clkmgr_alert_test.1034845038
Short name	T243
Test name
Test status
Simulation time	38219064 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:18 PM PDT 24
Finished	Apr 28 12:57:20 PM PDT 24
Peak memory	201048 kb
Host	smart-683b39e2-62d4-499b-adea-853b1fe2a855
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034845038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk mgr_alert_test.1034845038
Directory	/workspace/33.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.124171726
Short name	T283
Test name
Test status
Simulation time	56775275 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:16 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	200820 kb
Host	smart-f12b0d0e-78d3-4853-ba38-68c87b9b5181
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124171726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.124171726
Directory	/workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_status.1588019382
Short name	T610
Test name
Test status
Simulation time	37584840 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:05 PM PDT 24
Finished	Apr 28 12:57:07 PM PDT 24
Peak memory	200012 kb
Host	smart-854f1b4b-6e93-4e7d-a75b-b4f07a16e6e6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588019382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1588019382
Directory	/workspace/33.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/33.clkmgr_div_intersig_mubi.1566190705
Short name	T742
Test name
Test status
Simulation time	44852043 ps
CPU time	0.83 seconds
Started	Apr 28 12:57:10 PM PDT 24
Finished	Apr 28 12:57:11 PM PDT 24
Peak memory	200892 kb
Host	smart-de00976d-d2b8-47b0-96ab-347d9ffa78b1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566190705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.1566190705
Directory	/workspace/33.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_extclk.2028870165
Short name	T770
Test name
Test status
Simulation time	48699599 ps
CPU time	0.98 seconds
Started	Apr 28 12:57:06 PM PDT 24
Finished	Apr 28 12:57:08 PM PDT 24
Peak memory	200892 kb
Host	smart-89b367c0-fa09-41ab-9367-d7e4bda197f4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028870165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2028870165
Directory	/workspace/33.clkmgr_extclk/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency.211849875
Short name	T65
Test name
Test status
Simulation time	207569905 ps
CPU time	1.69 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:09 PM PDT 24
Peak memory	200872 kb
Host	smart-98c4227d-6e48-42c2-824a-3c8fa32fafce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211849875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.211849875
Directory	/workspace/33.clkmgr_frequency/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency_timeout.130148997
Short name	T308
Test name
Test status
Simulation time	151252510 ps
CPU time	1.18 seconds
Started	Apr 28 12:57:07 PM PDT 24
Finished	Apr 28 12:57:10 PM PDT 24
Peak memory	201024 kb
Host	smart-ea36f819-b6f5-4aa3-9422-a807436d7f2c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130148997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti meout.130148997
Directory	/workspace/33.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/33.clkmgr_idle_intersig_mubi.2249682404
Short name	T788
Test name
Test status
Simulation time	57651491 ps
CPU time	0.79 seconds
Started	Apr 28 12:57:03 PM PDT 24
Finished	Apr 28 12:57:05 PM PDT 24
Peak memory	200908 kb
Host	smart-ef8cc0bc-4b80-48c2-8b8a-cfe6389055a9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249682404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.2249682404
Directory	/workspace/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1407905216
Short name	T176
Test name
Test status
Simulation time	26408779 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:18 PM PDT 24
Finished	Apr 28 12:57:20 PM PDT 24
Peak memory	200628 kb
Host	smart-85623adb-ebd8-4136-a409-65ac924b9ae4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407905216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_clk_byp_req_intersig_mubi.1407905216
Directory	/workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1501461081
Short name	T817
Test name
Test status
Simulation time	78737362 ps
CPU time	1 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:25 PM PDT 24
Peak memory	200988 kb
Host	smart-83468c0d-c49d-43b1-b82e-eaf5ba09cd21
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501461081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_ctrl_intersig_mubi.1501461081
Directory	/workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_peri.1706105926
Short name	T582
Test name
Test status
Simulation time	21215173 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:10 PM PDT 24
Finished	Apr 28 12:57:13 PM PDT 24
Peak memory	200928 kb
Host	smart-db2c3779-7a1d-4e8a-87ef-119a09ca457c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706105926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1706105926
Directory	/workspace/33.clkmgr_peri/latest

Test location	/workspace/coverage/default/33.clkmgr_regwen.759221747
Short name	T558
Test name
Test status
Simulation time	1477402837 ps
CPU time	6.27 seconds
Started	Apr 28 12:57:11 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	201032 kb
Host	smart-6c744b2a-e055-42cc-97aa-96a478a25123
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759221747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.759221747
Directory	/workspace/33.clkmgr_regwen/latest

Test location	/workspace/coverage/default/33.clkmgr_smoke.821615227
Short name	T567
Test name
Test status
Simulation time	25459834 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:06 PM PDT 24
Finished	Apr 28 12:57:08 PM PDT 24
Peak memory	201064 kb
Host	smart-e6948a3c-a8e3-4e8c-8252-58f6c475e744
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821615227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.821615227
Directory	/workspace/33.clkmgr_smoke/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all.2955910296
Short name	T657
Test name
Test status
Simulation time	3381495579 ps
CPU time	26.54 seconds
Started	Apr 28 12:57:09 PM PDT 24
Finished	Apr 28 12:57:37 PM PDT 24
Peak memory	201408 kb
Host	smart-0fff7354-8365-4213-b096-a0b0b172fe0a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955910296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.2955910296
Directory	/workspace/33.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.3311635947
Short name	T3
Test name
Test status
Simulation time	227126977006 ps
CPU time	906.81 seconds
Started	Apr 28 12:57:11 PM PDT 24
Finished	Apr 28 01:12:19 PM PDT 24
Peak memory	212356 kb
Host	smart-b14a60cd-6bcf-456a-8ca3-22aed6b860c2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3311635947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.3311635947
Directory	/workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.clkmgr_trans.4079993735
Short name	T194
Test name
Test status
Simulation time	143231215 ps
CPU time	1.14 seconds
Started	Apr 28 12:57:11 PM PDT 24
Finished	Apr 28 12:57:14 PM PDT 24
Peak memory	200892 kb
Host	smart-4c1deff4-d94e-4dc4-85e2-480d7c7d2a5a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079993735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.4079993735
Directory	/workspace/33.clkmgr_trans/latest

Test location	/workspace/coverage/default/34.clkmgr_alert_test.689068951
Short name	T639
Test name
Test status
Simulation time	19496697 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:16 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	201064 kb
Host	smart-826f77da-50ce-4135-8dec-c99f32959a2d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689068951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkm gr_alert_test.689068951
Directory	/workspace/34.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3310875653
Short name	T848
Test name
Test status
Simulation time	73001254 ps
CPU time	0.93 seconds
Started	Apr 28 12:57:11 PM PDT 24
Finished	Apr 28 12:57:13 PM PDT 24
Peak memory	200844 kb
Host	smart-e445df0b-b656-4f39-8764-92ffb6c27e96
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310875653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.3310875653
Directory	/workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_status.358550694
Short name	T571
Test name
Test status
Simulation time	20279603 ps
CPU time	0.74 seconds
Started	Apr 28 12:57:11 PM PDT 24
Finished	Apr 28 12:57:13 PM PDT 24
Peak memory	200772 kb
Host	smart-bd5ee129-6318-40b7-9ae7-aff0bdcdfd30
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358550694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.358550694
Directory	/workspace/34.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/34.clkmgr_div_intersig_mubi.1304665016
Short name	T184
Test name
Test status
Simulation time	47079436 ps
CPU time	0.93 seconds
Started	Apr 28 12:57:17 PM PDT 24
Finished	Apr 28 12:57:19 PM PDT 24
Peak memory	200948 kb
Host	smart-648c2e36-2a11-47ad-994e-291be0c2dd4c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304665016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.1304665016
Directory	/workspace/34.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_extclk.75207416
Short name	T422
Test name
Test status
Simulation time	55594292 ps
CPU time	0.92 seconds
Started	Apr 28 12:57:09 PM PDT 24
Finished	Apr 28 12:57:12 PM PDT 24
Peak memory	201012 kb
Host	smart-2d780e2a-b2ec-4ecd-be0b-56a2e54485e8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75207416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.75207416
Directory	/workspace/34.clkmgr_extclk/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency.654205844
Short name	T741
Test name
Test status
Simulation time	436747924 ps
CPU time	3.7 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:19 PM PDT 24
Peak memory	200904 kb
Host	smart-97bc99a8-ba3c-4071-9f8d-01668c6f920f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654205844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.654205844
Directory	/workspace/34.clkmgr_frequency/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency_timeout.3405569903
Short name	T843
Test name
Test status
Simulation time	867029045 ps
CPU time	4.69 seconds
Started	Apr 28 12:57:11 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	200996 kb
Host	smart-c58334c0-8247-4c13-90f9-8202761ae62b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405569903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t imeout.3405569903
Directory	/workspace/34.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/34.clkmgr_idle_intersig_mubi.4158566745
Short name	T400
Test name
Test status
Simulation time	80335548 ps
CPU time	1 seconds
Started	Apr 28 12:57:16 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	200996 kb
Host	smart-2ea7fe6f-4fe7-4765-8cb2-5b41feed744d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158566745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.4158566745
Directory	/workspace/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.129118436
Short name	T765
Test name
Test status
Simulation time	15595912 ps
CPU time	0.74 seconds
Started	Apr 28 12:57:09 PM PDT 24
Finished	Apr 28 12:57:11 PM PDT 24
Peak memory	201004 kb
Host	smart-f116a4aa-32e8-44e7-97dd-08789b438c4a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129118436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.clkmgr_lc_clk_byp_req_intersig_mubi.129118436
Directory	/workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.732889382
Short name	T721
Test name
Test status
Simulation time	47522900 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:09 PM PDT 24
Finished	Apr 28 12:57:11 PM PDT 24
Peak memory	200900 kb
Host	smart-c55bc6fb-18c5-4aad-82e3-45eea5470591
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732889382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.clkmgr_lc_ctrl_intersig_mubi.732889382
Directory	/workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_peri.1198645070
Short name	T437
Test name
Test status
Simulation time	16527767 ps
CPU time	0.73 seconds
Started	Apr 28 12:57:08 PM PDT 24
Finished	Apr 28 12:57:10 PM PDT 24
Peak memory	200876 kb
Host	smart-d5eaa986-c5e9-494a-87b0-88c8f9a451e3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198645070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1198645070
Directory	/workspace/34.clkmgr_peri/latest

Test location	/workspace/coverage/default/34.clkmgr_regwen.2050697045
Short name	T160
Test name
Test status
Simulation time	1120092499 ps
CPU time	4.86 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:29 PM PDT 24
Peak memory	201204 kb
Host	smart-48d87da3-3bd5-4d12-83fc-f9c07622bea6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050697045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2050697045
Directory	/workspace/34.clkmgr_regwen/latest

Test location	/workspace/coverage/default/34.clkmgr_smoke.3129447475
Short name	T685
Test name
Test status
Simulation time	146634550 ps
CPU time	1.13 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	201056 kb
Host	smart-36549723-d751-48bb-899e-11a69d90ab9a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129447475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.3129447475
Directory	/workspace/34.clkmgr_smoke/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all.3527339987
Short name	T425
Test name
Test status
Simulation time	10185031949 ps
CPU time	57.95 seconds
Started	Apr 28 12:57:22 PM PDT 24
Finished	Apr 28 12:58:21 PM PDT 24
Peak memory	201392 kb
Host	smart-a17ced6a-6d57-4dad-93e9-5100efbcda20
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527339987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.3527339987
Directory	/workspace/34.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.2849321243
Short name	T540
Test name
Test status
Simulation time	35784774610 ps
CPU time	540.24 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 01:06:15 PM PDT 24
Peak memory	210236 kb
Host	smart-65b2797c-6186-4b18-8f81-4117761a769a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2849321243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.2849321243
Directory	/workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.clkmgr_trans.991899248
Short name	T403
Test name
Test status
Simulation time	157523192 ps
CPU time	1.18 seconds
Started	Apr 28 12:57:10 PM PDT 24
Finished	Apr 28 12:57:13 PM PDT 24
Peak memory	200980 kb
Host	smart-2f37ae10-d3f0-4f7b-a5b5-5dc08636a278
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991899248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.991899248
Directory	/workspace/34.clkmgr_trans/latest

Test location	/workspace/coverage/default/35.clkmgr_alert_test.3020463755
Short name	T268
Test name
Test status
Simulation time	46222596 ps
CPU time	0.83 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:25 PM PDT 24
Peak memory	201064 kb
Host	smart-10cbf47d-f62c-4d69-ae1c-123549df00d6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020463755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk mgr_alert_test.3020463755
Directory	/workspace/35.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.4051545686
Short name	T652
Test name
Test status
Simulation time	38192572 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	200896 kb
Host	smart-cbfee4f2-2fd2-4f17-8521-67bdf81cb242
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051545686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.4051545686
Directory	/workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_status.1792643295
Short name	T531
Test name
Test status
Simulation time	41301919 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:10 PM PDT 24
Finished	Apr 28 12:57:12 PM PDT 24
Peak memory	200652 kb
Host	smart-5a85be6e-5fa2-400b-b943-0412c234a67f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792643295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.1792643295
Directory	/workspace/35.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/35.clkmgr_div_intersig_mubi.3038892823
Short name	T792
Test name
Test status
Simulation time	35432786 ps
CPU time	0.82 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	200992 kb
Host	smart-27643c66-f806-4ef9-9752-c5221459d11d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038892823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.3038892823
Directory	/workspace/35.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_extclk.3269278557
Short name	T679
Test name
Test status
Simulation time	71935884 ps
CPU time	0.96 seconds
Started	Apr 28 12:57:20 PM PDT 24
Finished	Apr 28 12:57:22 PM PDT 24
Peak memory	200944 kb
Host	smart-878b29a0-6ba4-470a-849d-164554b16c4e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269278557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3269278557
Directory	/workspace/35.clkmgr_extclk/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency.681422339
Short name	T750
Test name
Test status
Simulation time	1104097128 ps
CPU time	4.99 seconds
Started	Apr 28 12:57:11 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	200964 kb
Host	smart-fa726224-420a-421e-a0d2-961cb22209a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681422339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.681422339
Directory	/workspace/35.clkmgr_frequency/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency_timeout.1406081739
Short name	T218
Test name
Test status
Simulation time	1336621899 ps
CPU time	9.73 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:24 PM PDT 24
Peak memory	201100 kb
Host	smart-3d385654-e072-4b57-9f45-5ca2a3ed1dff
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406081739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t imeout.1406081739
Directory	/workspace/35.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/35.clkmgr_idle_intersig_mubi.2022720465
Short name	T339
Test name
Test status
Simulation time	25535779 ps
CPU time	0.85 seconds
Started	Apr 28 12:57:16 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	200964 kb
Host	smart-98286798-9805-4c44-9e3e-c190ecf00a55
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022720465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.2022720465
Directory	/workspace/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.395116555
Short name	T273
Test name
Test status
Simulation time	19312027 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	201000 kb
Host	smart-f4dcdac0-ae3d-40a2-bed5-aca3ab128cc1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395116555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.clkmgr_lc_clk_byp_req_intersig_mubi.395116555
Directory	/workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1968430652
Short name	T99
Test name
Test status
Simulation time	25890135 ps
CPU time	0.85 seconds
Started	Apr 28 12:57:21 PM PDT 24
Finished	Apr 28 12:57:23 PM PDT 24
Peak memory	200880 kb
Host	smart-95de986b-171f-43e9-b90d-81a7de521ee9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968430652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_ctrl_intersig_mubi.1968430652
Directory	/workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_peri.1331237389
Short name	T229
Test name
Test status
Simulation time	62464877 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:10 PM PDT 24
Finished	Apr 28 12:57:13 PM PDT 24
Peak memory	200992 kb
Host	smart-5b8e1321-0ab9-4bb1-8d90-1dde42bf3b1e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331237389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1331237389
Directory	/workspace/35.clkmgr_peri/latest

Test location	/workspace/coverage/default/35.clkmgr_regwen.2526588721
Short name	T404
Test name
Test status
Simulation time	1146142340 ps
CPU time	3.9 seconds
Started	Apr 28 12:57:20 PM PDT 24
Finished	Apr 28 12:57:24 PM PDT 24
Peak memory	201032 kb
Host	smart-4b587936-a0b7-455c-a02b-3afe27a689bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526588721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.2526588721
Directory	/workspace/35.clkmgr_regwen/latest

Test location	/workspace/coverage/default/35.clkmgr_smoke.1192251220
Short name	T123
Test name
Test status
Simulation time	94219245 ps
CPU time	1.12 seconds
Started	Apr 28 12:57:21 PM PDT 24
Finished	Apr 28 12:57:23 PM PDT 24
Peak memory	200948 kb
Host	smart-fe2f179f-1ca8-4094-b076-22b3f17b389f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192251220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1192251220
Directory	/workspace/35.clkmgr_smoke/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all.2130382021
Short name	T542
Test name
Test status
Simulation time	4199136098 ps
CPU time	17.14 seconds
Started	Apr 28 12:57:20 PM PDT 24
Finished	Apr 28 12:57:38 PM PDT 24
Peak memory	201388 kb
Host	smart-f4ef08bd-1e2e-42f6-9d57-2542b0c140aa
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130382021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.2130382021
Directory	/workspace/35.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.1246775695
Short name	T684
Test name
Test status
Simulation time	125792111611 ps
CPU time	406.64 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 01:04:02 PM PDT 24
Peak memory	217852 kb
Host	smart-c0feb01e-2d7c-4695-bf4d-2caeaddf9f46
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1246775695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.1246775695
Directory	/workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.clkmgr_trans.3821888995
Short name	T44
Test name
Test status
Simulation time	60187286 ps
CPU time	1.09 seconds
Started	Apr 28 12:57:16 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	200996 kb
Host	smart-16bc3816-c953-4b36-9574-5cf4db4663aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821888995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3821888995
Directory	/workspace/35.clkmgr_trans/latest

Test location	/workspace/coverage/default/36.clkmgr_alert_test.3568687899
Short name	T211
Test name
Test status
Simulation time	163083517 ps
CPU time	1.11 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	201032 kb
Host	smart-d38abb63-c252-49cf-8dc1-b25b22fddced
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568687899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk mgr_alert_test.3568687899
Directory	/workspace/36.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.2454886828
Short name	T81
Test name
Test status
Simulation time	81994128 ps
CPU time	0.97 seconds
Started	Apr 28 12:57:20 PM PDT 24
Finished	Apr 28 12:57:21 PM PDT 24
Peak memory	200996 kb
Host	smart-edb87a2a-691e-4d7b-8811-c5493d875eb0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454886828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.2454886828
Directory	/workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_status.2090492324
Short name	T623
Test name
Test status
Simulation time	27763626 ps
CPU time	0.73 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:14 PM PDT 24
Peak memory	200760 kb
Host	smart-5a89ddaf-636b-41ad-8ec4-b04dd8d1d087
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090492324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2090492324
Directory	/workspace/36.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/36.clkmgr_div_intersig_mubi.2256031766
Short name	T282
Test name
Test status
Simulation time	41247516 ps
CPU time	0.79 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:15 PM PDT 24
Peak memory	200988 kb
Host	smart-eb4f081f-a049-48bd-8d96-c0954a6d36fa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256031766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.2256031766
Directory	/workspace/36.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_extclk.570443971
Short name	T854
Test name
Test status
Simulation time	40068998 ps
CPU time	0.86 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:15 PM PDT 24
Peak memory	200872 kb
Host	smart-6e2d86a2-060f-48b1-8bd8-f71ba0999ddd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570443971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.570443971
Directory	/workspace/36.clkmgr_extclk/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency.1680285150
Short name	T855
Test name
Test status
Simulation time	920459311 ps
CPU time	7.53 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:23 PM PDT 24
Peak memory	200992 kb
Host	smart-e30027f9-a0c6-48f1-81eb-43c9e2cfc1ee
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680285150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1680285150
Directory	/workspace/36.clkmgr_frequency/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency_timeout.694706946
Short name	T330
Test name
Test status
Simulation time	138130360 ps
CPU time	1.5 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	200992 kb
Host	smart-d34ef577-b3a7-445e-9055-c27857dabfc5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694706946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_ti meout.694706946
Directory	/workspace/36.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/36.clkmgr_idle_intersig_mubi.766562714
Short name	T342
Test name
Test status
Simulation time	39375331 ps
CPU time	0.97 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	200996 kb
Host	smart-f498e8ec-72e0-4c8f-bc93-c61db9167ba6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766562714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.clkmgr_idle_intersig_mubi.766562714
Directory	/workspace/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.4154092352
Short name	T766
Test name
Test status
Simulation time	43781023 ps
CPU time	0.89 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	200952 kb
Host	smart-22697114-dc98-4870-95a9-92f161806e04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154092352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_clk_byp_req_intersig_mubi.4154092352
Directory	/workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3854604754
Short name	T526
Test name
Test status
Simulation time	28243001 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:25 PM PDT 24
Peak memory	200924 kb
Host	smart-5d1569a2-e059-44b9-878e-be3e9f03ba12
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854604754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.clkmgr_lc_ctrl_intersig_mubi.3854604754
Directory	/workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_peri.1979508026
Short name	T674
Test name
Test status
Simulation time	22478648 ps
CPU time	0.72 seconds
Started	Apr 28 12:57:17 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	200976 kb
Host	smart-e9ece237-8dad-45f9-9830-034aa5f3ee7a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979508026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1979508026
Directory	/workspace/36.clkmgr_peri/latest

Test location	/workspace/coverage/default/36.clkmgr_regwen.38413783
Short name	T458
Test name
Test status
Simulation time	1196292356 ps
CPU time	4.37 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	201112 kb
Host	smart-db6f9302-3626-46f4-82cf-46523bbbe0ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38413783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.38413783
Directory	/workspace/36.clkmgr_regwen/latest

Test location	/workspace/coverage/default/36.clkmgr_smoke.4260177844
Short name	T470
Test name
Test status
Simulation time	37774331 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:20 PM PDT 24
Finished	Apr 28 12:57:22 PM PDT 24
Peak memory	201068 kb
Host	smart-3f3b945d-4a60-44a1-b930-596069c523c7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260177844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.4260177844
Directory	/workspace/36.clkmgr_smoke/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all.4097808699
Short name	T720
Test name
Test status
Simulation time	10946193757 ps
CPU time	48.6 seconds
Started	Apr 28 12:57:18 PM PDT 24
Finished	Apr 28 12:58:08 PM PDT 24
Peak memory	201432 kb
Host	smart-836009b8-c0b1-4b36-b19c-f4bacad3ca92
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097808699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.4097808699
Directory	/workspace/36.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.2340196515
Short name	T58
Test name
Test status
Simulation time	266563546080 ps
CPU time	1217.61 seconds
Started	Apr 28 12:57:20 PM PDT 24
Finished	Apr 28 01:17:38 PM PDT 24
Peak memory	209720 kb
Host	smart-e4a3a825-c726-48d3-847f-f7f96cb6d965
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2340196515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.2340196515
Directory	/workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.clkmgr_trans.1880740345
Short name	T179
Test name
Test status
Simulation time	84831831 ps
CPU time	1.02 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	200880 kb
Host	smart-a357eb7a-cf0f-48e8-a847-007f9af8827c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880740345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1880740345
Directory	/workspace/36.clkmgr_trans/latest

Test location	/workspace/coverage/default/37.clkmgr_alert_test.1909910617
Short name	T692
Test name
Test status
Simulation time	12432999 ps
CPU time	0.7 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	201020 kb
Host	smart-b08a24e7-4fe9-4b7f-8bd9-b9f583d074ba
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909910617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk mgr_alert_test.1909910617
Directory	/workspace/37.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.4170623494
Short name	T209
Test name
Test status
Simulation time	32138880 ps
CPU time	0.93 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:25 PM PDT 24
Peak memory	201008 kb
Host	smart-8f015dab-22e3-47b9-8472-a677eecd3682
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170623494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.4170623494
Directory	/workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_status.2545594478
Short name	T321
Test name
Test status
Simulation time	22910404 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:16 PM PDT 24
Finished	Apr 28 12:57:18 PM PDT 24
Peak memory	200864 kb
Host	smart-c4ef7718-1e13-4e50-be52-b8786d582b95
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545594478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2545594478
Directory	/workspace/37.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/37.clkmgr_div_intersig_mubi.3467502116
Short name	T837
Test name
Test status
Simulation time	38047653 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:17 PM PDT 24
Peak memory	200880 kb
Host	smart-a815a5d4-7b03-47eb-b333-98066b2afe74
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467502116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.3467502116
Directory	/workspace/37.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_extclk.2739376041
Short name	T256
Test name
Test status
Simulation time	29478714 ps
CPU time	0.78 seconds
Started	Apr 28 12:57:17 PM PDT 24
Finished	Apr 28 12:57:19 PM PDT 24
Peak memory	200988 kb
Host	smart-37baaa23-9707-418b-987a-300673939a22
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739376041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2739376041
Directory	/workspace/37.clkmgr_extclk/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency.479747301
Short name	T523
Test name
Test status
Simulation time	1690540099 ps
CPU time	7.4 seconds
Started	Apr 28 12:57:24 PM PDT 24
Finished	Apr 28 12:57:32 PM PDT 24
Peak memory	201056 kb
Host	smart-139a612d-f9c9-4d7a-a330-225c97f75e40
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479747301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.479747301
Directory	/workspace/37.clkmgr_frequency/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency_timeout.4060988735
Short name	T703
Test name
Test status
Simulation time	2333072899 ps
CPU time	9.58 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:24 PM PDT 24
Peak memory	201340 kb
Host	smart-37d9f13f-b83e-4fb5-b3f2-1d3fc84f2a33
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060988735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t imeout.4060988735
Directory	/workspace/37.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/37.clkmgr_idle_intersig_mubi.500624566
Short name	T295
Test name
Test status
Simulation time	324023325 ps
CPU time	1.72 seconds
Started	Apr 28 12:57:19 PM PDT 24
Finished	Apr 28 12:57:22 PM PDT 24
Peak memory	200940 kb
Host	smart-753ffdf0-5272-481c-b3da-48960dd38d27
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500624566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.clkmgr_idle_intersig_mubi.500624566
Directory	/workspace/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.2364587862
Short name	T625
Test name
Test status
Simulation time	37509791 ps
CPU time	0.89 seconds
Started	Apr 28 12:57:18 PM PDT 24
Finished	Apr 28 12:57:20 PM PDT 24
Peak memory	200940 kb
Host	smart-2b9a959f-6651-4568-89d2-4219ea5029e5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364587862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_clk_byp_req_intersig_mubi.2364587862
Directory	/workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.32628991
Short name	T275
Test name
Test status
Simulation time	43091236 ps
CPU time	0.89 seconds
Started	Apr 28 12:57:13 PM PDT 24
Finished	Apr 28 12:57:15 PM PDT 24
Peak memory	200980 kb
Host	smart-e11c64c9-9d7e-4986-87ca-4775740c352c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32628991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.32628991
Directory	/workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_peri.2438729974
Short name	T823
Test name
Test status
Simulation time	21028724 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:20 PM PDT 24
Finished	Apr 28 12:57:22 PM PDT 24
Peak memory	200984 kb
Host	smart-f7b4de0f-9103-4157-afc9-de3f3e83310f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438729974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.2438729974
Directory	/workspace/37.clkmgr_peri/latest

Test location	/workspace/coverage/default/37.clkmgr_regwen.3144027078
Short name	T314
Test name
Test status
Simulation time	1294413886 ps
CPU time	4.64 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:20 PM PDT 24
Peak memory	200984 kb
Host	smart-e775358b-395e-4976-ab91-9391f1666d00
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144027078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.3144027078
Directory	/workspace/37.clkmgr_regwen/latest

Test location	/workspace/coverage/default/37.clkmgr_smoke.1837565737
Short name	T462
Test name
Test status
Simulation time	64973437 ps
CPU time	0.96 seconds
Started	Apr 28 12:57:18 PM PDT 24
Finished	Apr 28 12:57:20 PM PDT 24
Peak memory	200960 kb
Host	smart-70dd5fdb-1eee-40b1-a463-ebe8387f627b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837565737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.1837565737
Directory	/workspace/37.clkmgr_smoke/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all.3607003180
Short name	T294
Test name
Test status
Simulation time	13344145942 ps
CPU time	90.71 seconds
Started	Apr 28 12:57:18 PM PDT 24
Finished	Apr 28 12:58:49 PM PDT 24
Peak memory	201416 kb
Host	smart-d4e467f8-7d7f-4563-8aaf-3b59f6f0ad56
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607003180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.3607003180
Directory	/workspace/37.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.2849153349
Short name	T635
Test name
Test status
Simulation time	174948086941 ps
CPU time	847.1 seconds
Started	Apr 28 12:57:17 PM PDT 24
Finished	Apr 28 01:11:25 PM PDT 24
Peak memory	217804 kb
Host	smart-da6b8b0f-7f2f-4938-b0ad-8f57820deb22
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2849153349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.2849153349
Directory	/workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.clkmgr_trans.2208053605
Short name	T320
Test name
Test status
Simulation time	76973877 ps
CPU time	0.92 seconds
Started	Apr 28 12:57:21 PM PDT 24
Finished	Apr 28 12:57:22 PM PDT 24
Peak memory	200976 kb
Host	smart-ead91836-8b95-4042-859b-0fe2ec475f20
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208053605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2208053605
Directory	/workspace/37.clkmgr_trans/latest

Test location	/workspace/coverage/default/38.clkmgr_alert_test.1473699212
Short name	T415
Test name
Test status
Simulation time	33973514 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:21 PM PDT 24
Finished	Apr 28 12:57:23 PM PDT 24
Peak memory	200960 kb
Host	smart-1ecb655f-e35f-4afc-ac10-820adbae5d53
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473699212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk mgr_alert_test.1473699212
Directory	/workspace/38.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3124755211
Short name	T744
Test name
Test status
Simulation time	28096855 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:18 PM PDT 24
Finished	Apr 28 12:57:20 PM PDT 24
Peak memory	200964 kb
Host	smart-f74011cc-ab3d-4d8e-a25f-6881c321c787
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124755211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.3124755211
Directory	/workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_status.3370834707
Short name	T409
Test name
Test status
Simulation time	31494984 ps
CPU time	0.74 seconds
Started	Apr 28 12:57:32 PM PDT 24
Finished	Apr 28 12:57:33 PM PDT 24
Peak memory	199896 kb
Host	smart-fe7c74a8-0933-4b16-aadf-26d8e9de9eb4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370834707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3370834707
Directory	/workspace/38.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/38.clkmgr_div_intersig_mubi.3901983776
Short name	T396
Test name
Test status
Simulation time	46701939 ps
CPU time	0.92 seconds
Started	Apr 28 12:57:22 PM PDT 24
Finished	Apr 28 12:57:24 PM PDT 24
Peak memory	200904 kb
Host	smart-b776e127-6a72-4eaa-bf21-b8f093d71092
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901983776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.3901983776
Directory	/workspace/38.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_extclk.1645342488
Short name	T269
Test name
Test status
Simulation time	204926543 ps
CPU time	1.35 seconds
Started	Apr 28 12:57:14 PM PDT 24
Finished	Apr 28 12:57:16 PM PDT 24
Peak memory	201000 kb
Host	smart-323dc92a-a69f-4a9b-af00-5149ca0c77d1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645342488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.1645342488
Directory	/workspace/38.clkmgr_extclk/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency.3641835124
Short name	T527
Test name
Test status
Simulation time	1762706139 ps
CPU time	13.49 seconds
Started	Apr 28 12:57:15 PM PDT 24
Finished	Apr 28 12:57:30 PM PDT 24
Peak memory	201168 kb
Host	smart-87b0f5ec-3702-477c-b3ab-b9660c87ffdf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641835124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.3641835124
Directory	/workspace/38.clkmgr_frequency/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency_timeout.4202117497
Short name	T773
Test name
Test status
Simulation time	747838822 ps
CPU time	3.74 seconds
Started	Apr 28 12:57:22 PM PDT 24
Finished	Apr 28 12:57:27 PM PDT 24
Peak memory	200948 kb
Host	smart-7093c0b1-b9e0-43a2-bafe-f5df2a986462
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202117497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t imeout.4202117497
Directory	/workspace/38.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1451056415
Short name	T318
Test name
Test status
Simulation time	64550564 ps
CPU time	0.99 seconds
Started	Apr 28 12:57:24 PM PDT 24
Finished	Apr 28 12:57:26 PM PDT 24
Peak memory	200996 kb
Host	smart-4114349b-ce0e-4302-8bd5-d33e9eab7d67
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451056415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.1451056415
Directory	/workspace/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1586763002
Short name	T190
Test name
Test status
Simulation time	68150201 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:25 PM PDT 24
Finished	Apr 28 12:57:27 PM PDT 24
Peak memory	200992 kb
Host	smart-ec5a51b4-db1a-4b9b-b104-212321b48908
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586763002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_clk_byp_req_intersig_mubi.1586763002
Directory	/workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.566716160
Short name	T296
Test name
Test status
Simulation time	49141161 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:21 PM PDT 24
Finished	Apr 28 12:57:23 PM PDT 24
Peak memory	200952 kb
Host	smart-d8a6f218-cc22-415f-be93-632ae7fa4963
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566716160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.clkmgr_lc_ctrl_intersig_mubi.566716160
Directory	/workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_peri.1960159425
Short name	T286
Test name
Test status
Simulation time	16476129 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:31 PM PDT 24
Finished	Apr 28 12:57:32 PM PDT 24
Peak memory	200892 kb
Host	smart-5756a996-7691-4031-9679-dcbfa8f19185
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960159425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1960159425
Directory	/workspace/38.clkmgr_peri/latest

Test location	/workspace/coverage/default/38.clkmgr_regwen.732529780
Short name	T158
Test name
Test status
Simulation time	837561408 ps
CPU time	3.38 seconds
Started	Apr 28 12:57:22 PM PDT 24
Finished	Apr 28 12:57:26 PM PDT 24
Peak memory	201048 kb
Host	smart-1d1ad698-7a2b-4973-b21f-afba7428382a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732529780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.732529780
Directory	/workspace/38.clkmgr_regwen/latest

Test location	/workspace/coverage/default/38.clkmgr_smoke.557962060
Short name	T96
Test name
Test status
Simulation time	23186978 ps
CPU time	0.96 seconds
Started	Apr 28 12:57:22 PM PDT 24
Finished	Apr 28 12:57:23 PM PDT 24
Peak memory	200960 kb
Host	smart-8056c310-1ca7-4a8a-a64f-0bfd23a19521
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557962060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.557962060
Directory	/workspace/38.clkmgr_smoke/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all.716551144
Short name	T233
Test name
Test status
Simulation time	8603032081 ps
CPU time	35.34 seconds
Started	Apr 28 12:57:25 PM PDT 24
Finished	Apr 28 12:58:01 PM PDT 24
Peak memory	201308 kb
Host	smart-8207bc5e-5987-4c9f-9ab8-2f333ce921e0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716551144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.716551144
Directory	/workspace/38.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.1929762720
Short name	T29
Test name
Test status
Simulation time	54130660277 ps
CPU time	566.6 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 01:06:51 PM PDT 24
Peak memory	210972 kb
Host	smart-eee06e26-ad44-48f2-9646-e27571dbff13
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1929762720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.1929762720
Directory	/workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.clkmgr_trans.537582854
Short name	T815
Test name
Test status
Simulation time	75795075 ps
CPU time	1.03 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	200984 kb
Host	smart-de279895-7a1f-4f84-a7a6-abd34b39cc21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537582854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.537582854
Directory	/workspace/38.clkmgr_trans/latest

Test location	/workspace/coverage/default/39.clkmgr_alert_test.1327830335
Short name	T529
Test name
Test status
Simulation time	45766534 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	201068 kb
Host	smart-e332e2af-f937-4294-9105-eba92cc8dced
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327830335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk mgr_alert_test.1327830335
Directory	/workspace/39.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.4206591223
Short name	T601
Test name
Test status
Simulation time	15783010 ps
CPU time	0.72 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:25 PM PDT 24
Peak memory	200976 kb
Host	smart-b9df399c-6e20-4128-b591-ea5b5bb8da6d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206591223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.4206591223
Directory	/workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_status.1916651752
Short name	T471
Test name
Test status
Simulation time	172254551 ps
CPU time	1.06 seconds
Started	Apr 28 12:57:30 PM PDT 24
Finished	Apr 28 12:57:31 PM PDT 24
Peak memory	200020 kb
Host	smart-a2966162-4b02-40a5-b1bf-6f34eb880415
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916651752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.1916651752
Directory	/workspace/39.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/39.clkmgr_div_intersig_mubi.1832075832
Short name	T346
Test name
Test status
Simulation time	64846923 ps
CPU time	0.92 seconds
Started	Apr 28 12:57:24 PM PDT 24
Finished	Apr 28 12:57:26 PM PDT 24
Peak memory	200896 kb
Host	smart-6b875fdb-2cdd-4e9a-8225-f4b097a653c3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832075832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.1832075832
Directory	/workspace/39.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_extclk.3065582241
Short name	T611
Test name
Test status
Simulation time	81534322 ps
CPU time	1.04 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:25 PM PDT 24
Peak memory	200972 kb
Host	smart-d7f50b69-cff8-4856-80d6-7297c6fbd286
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065582241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.3065582241
Directory	/workspace/39.clkmgr_extclk/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency.725853118
Short name	T434
Test name
Test status
Simulation time	2483259028 ps
CPU time	18.13 seconds
Started	Apr 28 12:57:20 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	201112 kb
Host	smart-8a9d6a76-c1a2-47cc-9825-bff3213e63f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725853118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.725853118
Directory	/workspace/39.clkmgr_frequency/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency_timeout.2490454374
Short name	T827
Test name
Test status
Simulation time	2653111988 ps
CPU time	7.86 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:32 PM PDT 24
Peak memory	201260 kb
Host	smart-d52ff8eb-fc7d-4816-b692-ec56fd1cb0eb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490454374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t imeout.2490454374
Directory	/workspace/39.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/39.clkmgr_idle_intersig_mubi.402882775
Short name	T585
Test name
Test status
Simulation time	28005302 ps
CPU time	0.93 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	200824 kb
Host	smart-5a227abc-e009-4d12-87ca-0d4dc34bc4f0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402882775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.clkmgr_idle_intersig_mubi.402882775
Directory	/workspace/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2730710859
Short name	T702
Test name
Test status
Simulation time	62346563 ps
CPU time	0.96 seconds
Started	Apr 28 12:57:23 PM PDT 24
Finished	Apr 28 12:57:25 PM PDT 24
Peak memory	200876 kb
Host	smart-10907e7e-a119-4804-9aa6-8b2d0193d9cf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730710859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_clk_byp_req_intersig_mubi.2730710859
Directory	/workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1004373436
Short name	T247
Test name
Test status
Simulation time	19337278 ps
CPU time	0.74 seconds
Started	Apr 28 12:57:19 PM PDT 24
Finished	Apr 28 12:57:20 PM PDT 24
Peak memory	201004 kb
Host	smart-a832187a-eca9-442f-91de-ef6325ed78cd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004373436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_ctrl_intersig_mubi.1004373436
Directory	/workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_peri.2703267183
Short name	T759
Test name
Test status
Simulation time	45352061 ps
CPU time	0.9 seconds
Started	Apr 28 12:57:21 PM PDT 24
Finished	Apr 28 12:57:22 PM PDT 24
Peak memory	200988 kb
Host	smart-f11c6f6c-6511-484f-a3da-f624c60e4d5d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703267183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.2703267183
Directory	/workspace/39.clkmgr_peri/latest

Test location	/workspace/coverage/default/39.clkmgr_regwen.2094688366
Short name	T782
Test name
Test status
Simulation time	718785453 ps
CPU time	2.92 seconds
Started	Apr 28 12:57:30 PM PDT 24
Finished	Apr 28 12:57:33 PM PDT 24
Peak memory	201032 kb
Host	smart-b1491409-5435-4f8d-9231-43304bce969d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094688366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.2094688366
Directory	/workspace/39.clkmgr_regwen/latest

Test location	/workspace/coverage/default/39.clkmgr_smoke.1348889786
Short name	T547
Test name
Test status
Simulation time	21364467 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:27 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	201028 kb
Host	smart-c89f6d6f-522b-48b1-902b-0f9e28e3a121
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348889786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1348889786
Directory	/workspace/39.clkmgr_smoke/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all.634545330
Short name	T306
Test name
Test status
Simulation time	4366955225 ps
CPU time	31.68 seconds
Started	Apr 28 12:57:27 PM PDT 24
Finished	Apr 28 12:57:59 PM PDT 24
Peak memory	201448 kb
Host	smart-47a17799-2714-465b-8d46-774865d7b216
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634545330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.634545330
Directory	/workspace/39.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.2276086029
Short name	T138
Test name
Test status
Simulation time	38501279188 ps
CPU time	552.84 seconds
Started	Apr 28 12:57:31 PM PDT 24
Finished	Apr 28 01:06:44 PM PDT 24
Peak memory	209612 kb
Host	smart-bd461d5a-3881-4f51-b680-4b89fdc71f08
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2276086029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.2276086029
Directory	/workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.clkmgr_trans.3825668516
Short name	T250
Test name
Test status
Simulation time	16562834 ps
CPU time	0.73 seconds
Started	Apr 28 12:57:28 PM PDT 24
Finished	Apr 28 12:57:29 PM PDT 24
Peak memory	201012 kb
Host	smart-b9de037e-f0f7-407e-91e9-a6d23e422c5e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825668516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.3825668516
Directory	/workspace/39.clkmgr_trans/latest

Test location	/workspace/coverage/default/4.clkmgr_alert_test.3907678763
Short name	T32
Test name
Test status
Simulation time	17640698 ps
CPU time	0.78 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:56:01 PM PDT 24
Peak memory	200904 kb
Host	smart-9a34e1a3-afef-4c72-b0dd-008240d7fd80
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907678763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm gr_alert_test.3907678763
Directory	/workspace/4.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1950276351
Short name	T309
Test name
Test status
Simulation time	55292941 ps
CPU time	0.95 seconds
Started	Apr 28 12:56:00 PM PDT 24
Finished	Apr 28 12:56:02 PM PDT 24
Peak memory	200836 kb
Host	smart-a93ae9e9-f5a5-4f1b-936a-c35aa55ef230
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950276351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.1950276351
Directory	/workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_status.3088471571
Short name	T147
Test name
Test status
Simulation time	27007979 ps
CPU time	0.75 seconds
Started	Apr 28 12:56:00 PM PDT 24
Finished	Apr 28 12:56:02 PM PDT 24
Peak memory	200768 kb
Host	smart-3a0c83d4-30e4-4afe-9e54-44478be20ba0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088471571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3088471571
Directory	/workspace/4.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/4.clkmgr_div_intersig_mubi.2103745619
Short name	T856
Test name
Test status
Simulation time	18241703 ps
CPU time	0.82 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:56:01 PM PDT 24
Peak memory	200976 kb
Host	smart-85fdc23e-18c8-41d9-bc18-53fe58503d8c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103745619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.2103745619
Directory	/workspace/4.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_extclk.2724518040
Short name	T535
Test name
Test status
Simulation time	15584121 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:03 PM PDT 24
Peak memory	200996 kb
Host	smart-dbb0269c-f30d-4480-93cd-05592af76b2e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724518040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.2724518040
Directory	/workspace/4.clkmgr_extclk/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency.4055727336
Short name	T790
Test name
Test status
Simulation time	2265271666 ps
CPU time	9.6 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:13 PM PDT 24
Peak memory	201148 kb
Host	smart-6d54b586-43e1-4532-973a-419de83f6399
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055727336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.4055727336
Directory	/workspace/4.clkmgr_frequency/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency_timeout.2352223987
Short name	T421
Test name
Test status
Simulation time	2321809817 ps
CPU time	9.22 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:08 PM PDT 24
Peak memory	201224 kb
Host	smart-8b68fe04-8624-4c77-8c7d-01363860e10c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352223987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti meout.2352223987
Directory	/workspace/4.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/4.clkmgr_idle_intersig_mubi.4046104516
Short name	T317
Test name
Test status
Simulation time	114709856 ps
CPU time	1.22 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	200884 kb
Host	smart-c44c3369-fba9-4f3b-bace-e8b2d191d0df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046104516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.4046104516
Directory	/workspace/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.378133987
Short name	T316
Test name
Test status
Simulation time	12751771 ps
CPU time	0.71 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:03 PM PDT 24
Peak memory	201004 kb
Host	smart-b3715ba0-303e-4999-8e21-83154e8a6770
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378133987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.clkmgr_lc_clk_byp_req_intersig_mubi.378133987
Directory	/workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3234774184
Short name	T647
Test name
Test status
Simulation time	58512951 ps
CPU time	0.99 seconds
Started	Apr 28 12:56:03 PM PDT 24
Finished	Apr 28 12:56:05 PM PDT 24
Peak memory	200992 kb
Host	smart-ef3edbd1-9df7-4c7a-ac65-c230f6957f2b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234774184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_ctrl_intersig_mubi.3234774184
Directory	/workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_peri.1248857233
Short name	T298
Test name
Test status
Simulation time	17146755 ps
CPU time	0.76 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:56:01 PM PDT 24
Peak memory	200864 kb
Host	smart-168f371a-2bc9-48b8-9029-d19b7ab8c779
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248857233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.1248857233
Directory	/workspace/4.clkmgr_peri/latest

Test location	/workspace/coverage/default/4.clkmgr_regwen.3733621833
Short name	T4
Test name
Test status
Simulation time	399734013 ps
CPU time	2.02 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	200948 kb
Host	smart-42fd629b-b688-43cc-bbde-fbae64c52e35
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733621833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.3733621833
Directory	/workspace/4.clkmgr_regwen/latest

Test location	/workspace/coverage/default/4.clkmgr_sec_cm.4173608351
Short name	T50
Test name
Test status
Simulation time	832472446 ps
CPU time	3.58 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:06 PM PDT 24
Peak memory	216104 kb
Host	smart-b0ae41cf-71ba-4fea-be9e-7d30a86cad0f
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173608351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg r_sec_cm.4173608351
Directory	/workspace/4.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/4.clkmgr_smoke.1351889886
Short name	T151
Test name
Test status
Simulation time	22886645 ps
CPU time	0.84 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	201060 kb
Host	smart-6f683394-8b94-4130-ab28-80bea618111f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351889886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1351889886
Directory	/workspace/4.clkmgr_smoke/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all.2070481329
Short name	T563
Test name
Test status
Simulation time	7818965336 ps
CPU time	54.87 seconds
Started	Apr 28 12:55:58 PM PDT 24
Finished	Apr 28 12:56:54 PM PDT 24
Peak memory	201376 kb
Host	smart-339652f3-54d0-4428-a458-bee6bed593bf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070481329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.2070481329
Directory	/workspace/4.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.516581214
Short name	T616
Test name
Test status
Simulation time	6482900423 ps
CPU time	96.78 seconds
Started	Apr 28 12:56:00 PM PDT 24
Finished	Apr 28 12:57:38 PM PDT 24
Peak memory	213772 kb
Host	smart-d07bc00a-ee18-421c-84f7-fcb7a6d00b19
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=516581214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.516581214
Directory	/workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.clkmgr_trans.2133760479
Short name	T284
Test name
Test status
Simulation time	24741624 ps
CPU time	0.94 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:03 PM PDT 24
Peak memory	200980 kb
Host	smart-fa94979a-73fe-4b8a-810a-4c782b46f464
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133760479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.2133760479
Directory	/workspace/4.clkmgr_trans/latest

Test location	/workspace/coverage/default/40.clkmgr_alert_test.3175534529
Short name	T259
Test name
Test status
Simulation time	17969456 ps
CPU time	0.7 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:27 PM PDT 24
Peak memory	201068 kb
Host	smart-1e658bb1-24a3-44ff-9ccf-b451a1f93bf4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175534529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk mgr_alert_test.3175534529
Directory	/workspace/40.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1558574497
Short name	T733
Test name
Test status
Simulation time	54026080 ps
CPU time	1.01 seconds
Started	Apr 28 12:57:31 PM PDT 24
Finished	Apr 28 12:57:32 PM PDT 24
Peak memory	200896 kb
Host	smart-57b4c2bd-9481-491d-8e5c-e3c36a550ba9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558574497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.1558574497
Directory	/workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_status.1912007933
Short name	T143
Test name
Test status
Simulation time	124893269 ps
CPU time	1.02 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	200724 kb
Host	smart-d4797638-1651-4b79-85ff-3a78394a743d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912007933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1912007933
Directory	/workspace/40.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/40.clkmgr_div_intersig_mubi.248644157
Short name	T172
Test name
Test status
Simulation time	50202390 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:28 PM PDT 24
Finished	Apr 28 12:57:29 PM PDT 24
Peak memory	201016 kb
Host	smart-e7002a84-5548-4bc5-b98c-72563a92cd04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248644157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.clkmgr_div_intersig_mubi.248644157
Directory	/workspace/40.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_extclk.109577618
Short name	T694
Test name
Test status
Simulation time	26421596 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:29 PM PDT 24
Finished	Apr 28 12:57:30 PM PDT 24
Peak memory	200940 kb
Host	smart-82554496-023f-4602-bba5-57f51aceeb5b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109577618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.109577618
Directory	/workspace/40.clkmgr_extclk/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency.1460500453
Short name	T27
Test name
Test status
Simulation time	1043449863 ps
CPU time	5.91 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:43 PM PDT 24
Peak memory	201036 kb
Host	smart-6d5f1017-ca81-41d6-986d-e593bd978b9d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460500453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1460500453
Directory	/workspace/40.clkmgr_frequency/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency_timeout.3746257054
Short name	T331
Test name
Test status
Simulation time	1224494648 ps
CPU time	5.2 seconds
Started	Apr 28 12:57:29 PM PDT 24
Finished	Apr 28 12:57:34 PM PDT 24
Peak memory	201104 kb
Host	smart-0c458946-5f63-4cec-940c-698af54ad43c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746257054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t imeout.3746257054
Directory	/workspace/40.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/40.clkmgr_idle_intersig_mubi.4067248740
Short name	T787
Test name
Test status
Simulation time	59278908 ps
CPU time	0.91 seconds
Started	Apr 28 12:57:24 PM PDT 24
Finished	Apr 28 12:57:26 PM PDT 24
Peak memory	200948 kb
Host	smart-2099714d-64b4-4326-bbdc-79d49aa5dc0d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067248740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.4067248740
Directory	/workspace/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.4071282482
Short name	T222
Test name
Test status
Simulation time	20726728 ps
CPU time	0.79 seconds
Started	Apr 28 12:57:27 PM PDT 24
Finished	Apr 28 12:57:29 PM PDT 24
Peak memory	200884 kb
Host	smart-5d32ad5d-4292-41f5-a990-de0170dc23d3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071282482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_clk_byp_req_intersig_mubi.4071282482
Directory	/workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2234898073
Short name	T205
Test name
Test status
Simulation time	18643328 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:25 PM PDT 24
Finished	Apr 28 12:57:27 PM PDT 24
Peak memory	200900 kb
Host	smart-fc27d759-b2ac-413e-a8fc-922f8900d2d0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234898073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_ctrl_intersig_mubi.2234898073
Directory	/workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_peri.2734565900
Short name	T395
Test name
Test status
Simulation time	36019858 ps
CPU time	0.78 seconds
Started	Apr 28 12:57:28 PM PDT 24
Finished	Apr 28 12:57:29 PM PDT 24
Peak memory	200944 kb
Host	smart-4bf9616a-2fd0-40cc-b5fd-a09905322a6d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734565900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2734565900
Directory	/workspace/40.clkmgr_peri/latest

Test location	/workspace/coverage/default/40.clkmgr_regwen.3619439073
Short name	T644
Test name
Test status
Simulation time	587116910 ps
CPU time	2.71 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:29 PM PDT 24
Peak memory	201136 kb
Host	smart-a93eb23d-d691-4f28-9e8e-ce9f9a30aba2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619439073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3619439073
Directory	/workspace/40.clkmgr_regwen/latest

Test location	/workspace/coverage/default/40.clkmgr_smoke.2536786085
Short name	T797
Test name
Test status
Simulation time	88427838 ps
CPU time	1.04 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	201068 kb
Host	smart-4767a1d7-07bd-4800-bbac-61297760a503
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536786085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2536786085
Directory	/workspace/40.clkmgr_smoke/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all.2654971352
Short name	T252
Test name
Test status
Simulation time	11344778444 ps
CPU time	75.71 seconds
Started	Apr 28 12:57:28 PM PDT 24
Finished	Apr 28 12:58:44 PM PDT 24
Peak memory	201352 kb
Host	smart-d5368270-1aa8-4c52-aef8-f93a934b0edc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654971352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.2654971352
Directory	/workspace/40.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.1403558480
Short name	T503
Test name
Test status
Simulation time	23489391554 ps
CPU time	421.7 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 01:04:28 PM PDT 24
Peak memory	209668 kb
Host	smart-4f921f30-7335-4dc3-83ce-53d5a641231d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1403558480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.1403558480
Directory	/workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.clkmgr_trans.187471103
Short name	T280
Test name
Test status
Simulation time	120064358 ps
CPU time	1.2 seconds
Started	Apr 28 12:57:28 PM PDT 24
Finished	Apr 28 12:57:30 PM PDT 24
Peak memory	200992 kb
Host	smart-0054eacc-522d-43cb-a3e6-0f2a39f03b59
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187471103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.187471103
Directory	/workspace/40.clkmgr_trans/latest

Test location	/workspace/coverage/default/41.clkmgr_alert_test.2258275072
Short name	T239
Test name
Test status
Simulation time	16346424 ps
CPU time	0.76 seconds
Started	Apr 28 12:57:29 PM PDT 24
Finished	Apr 28 12:57:31 PM PDT 24
Peak memory	201052 kb
Host	smart-4212d87c-959c-44e6-835a-c315f4951e3f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258275072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk mgr_alert_test.2258275072
Directory	/workspace/41.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.3011312680
Short name	T292
Test name
Test status
Simulation time	104276421 ps
CPU time	1.08 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:33 PM PDT 24
Peak memory	200836 kb
Host	smart-4b89349d-d6a0-458c-b496-eb7acb7adba1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011312680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.3011312680
Directory	/workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_status.3397227622
Short name	T504
Test name
Test status
Simulation time	15955775 ps
CPU time	0.76 seconds
Started	Apr 28 12:57:27 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	200016 kb
Host	smart-7e0cb423-de99-43d9-a142-3b8b7c533822
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397227622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3397227622
Directory	/workspace/41.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/41.clkmgr_div_intersig_mubi.2782937304
Short name	T438
Test name
Test status
Simulation time	24399972 ps
CPU time	0.89 seconds
Started	Apr 28 12:57:25 PM PDT 24
Finished	Apr 28 12:57:26 PM PDT 24
Peak memory	200988 kb
Host	smart-3acf50eb-10d3-4a6e-98f4-5c67c447a282
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782937304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.2782937304
Directory	/workspace/41.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_extclk.470620511
Short name	T293
Test name
Test status
Simulation time	18944228 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:25 PM PDT 24
Finished	Apr 28 12:57:26 PM PDT 24
Peak memory	200892 kb
Host	smart-b3bd33b8-69fe-4fc6-a67f-d6f6f0931043
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470620511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.470620511
Directory	/workspace/41.clkmgr_extclk/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency.1493134610
Short name	T595
Test name
Test status
Simulation time	561733869 ps
CPU time	4.51 seconds
Started	Apr 28 12:57:24 PM PDT 24
Finished	Apr 28 12:57:30 PM PDT 24
Peak memory	200912 kb
Host	smart-9bb8a566-6d78-476e-aa67-795b1ceade89
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493134610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1493134610
Directory	/workspace/41.clkmgr_frequency/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency_timeout.2812508903
Short name	T262
Test name
Test status
Simulation time	1696175136 ps
CPU time	12.11 seconds
Started	Apr 28 12:57:28 PM PDT 24
Finished	Apr 28 12:57:41 PM PDT 24
Peak memory	201012 kb
Host	smart-b9d2dd21-a358-4bd8-a47e-459e57337086
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812508903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t imeout.2812508903
Directory	/workspace/41.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1006735546
Short name	T238
Test name
Test status
Simulation time	24983517 ps
CPU time	0.9 seconds
Started	Apr 28 12:57:25 PM PDT 24
Finished	Apr 28 12:57:27 PM PDT 24
Peak memory	200808 kb
Host	smart-e3091b8d-457a-434b-9bbc-4aaf3eec0318
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006735546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.1006735546
Directory	/workspace/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2874948110
Short name	T8
Test name
Test status
Simulation time	21546104 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:25 PM PDT 24
Finished	Apr 28 12:57:27 PM PDT 24
Peak memory	200984 kb
Host	smart-63c358bc-4234-4c5a-91e6-66d359004637
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874948110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_clk_byp_req_intersig_mubi.2874948110
Directory	/workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.66206092
Short name	T711
Test name
Test status
Simulation time	31690562 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:24 PM PDT 24
Finished	Apr 28 12:57:26 PM PDT 24
Peak memory	200880 kb
Host	smart-2e2b613c-8f75-4c68-afb3-62cef5bcd38e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66206092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.66206092
Directory	/workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_peri.2485975656
Short name	T372
Test name
Test status
Simulation time	23439139 ps
CPU time	0.74 seconds
Started	Apr 28 12:57:26 PM PDT 24
Finished	Apr 28 12:57:28 PM PDT 24
Peak memory	200916 kb
Host	smart-1402d914-575b-4475-abbc-f02d794ba70d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485975656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2485975656
Directory	/workspace/41.clkmgr_peri/latest

Test location	/workspace/coverage/default/41.clkmgr_regwen.1286211783
Short name	T556
Test name
Test status
Simulation time	511781205 ps
CPU time	3.23 seconds
Started	Apr 28 12:57:27 PM PDT 24
Finished	Apr 28 12:57:31 PM PDT 24
Peak memory	201000 kb
Host	smart-e82fe744-cdd3-4bc3-a32d-b66cfa85de08
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286211783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1286211783
Directory	/workspace/41.clkmgr_regwen/latest

Test location	/workspace/coverage/default/41.clkmgr_smoke.1743512440
Short name	T177
Test name
Test status
Simulation time	65554370 ps
CPU time	0.96 seconds
Started	Apr 28 12:57:24 PM PDT 24
Finished	Apr 28 12:57:26 PM PDT 24
Peak memory	201068 kb
Host	smart-ab424684-e445-4991-92c5-c520aa167156
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743512440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1743512440
Directory	/workspace/41.clkmgr_smoke/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all.2195612837
Short name	T627
Test name
Test status
Simulation time	2059730370 ps
CPU time	15.62 seconds
Started	Apr 28 12:57:31 PM PDT 24
Finished	Apr 28 12:57:47 PM PDT 24
Peak memory	201304 kb
Host	smart-4ad081fe-6c16-4f66-9159-c26b579ac7ed
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195612837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.2195612837
Directory	/workspace/41.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.4116787781
Short name	T751
Test name
Test status
Simulation time	30274668166 ps
CPU time	436.4 seconds
Started	Apr 28 12:57:31 PM PDT 24
Finished	Apr 28 01:04:48 PM PDT 24
Peak memory	209576 kb
Host	smart-2aacbb7e-9d39-4ea0-8420-798db5e61dbc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4116787781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.4116787781
Directory	/workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.clkmgr_trans.3555079572
Short name	T789
Test name
Test status
Simulation time	22658989 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:25 PM PDT 24
Finished	Apr 28 12:57:27 PM PDT 24
Peak memory	200996 kb
Host	smart-22cfa104-d3f5-4971-bb53-bdfc8a4b78aa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555079572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.3555079572
Directory	/workspace/41.clkmgr_trans/latest

Test location	/workspace/coverage/default/42.clkmgr_alert_test.3577703354
Short name	T536
Test name
Test status
Simulation time	37216479 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:31 PM PDT 24
Finished	Apr 28 12:57:33 PM PDT 24
Peak memory	201036 kb
Host	smart-4d6d7ef0-aa37-4a53-a196-8ffeda86d74f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577703354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk mgr_alert_test.3577703354
Directory	/workspace/42.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1857128328
Short name	T450
Test name
Test status
Simulation time	66987927 ps
CPU time	0.91 seconds
Started	Apr 28 12:57:30 PM PDT 24
Finished	Apr 28 12:57:31 PM PDT 24
Peak memory	200996 kb
Host	smart-b3757278-27ff-4b2f-8809-df6daa776310
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857128328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.1857128328
Directory	/workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_status.750165653
Short name	T449
Test name
Test status
Simulation time	12518996 ps
CPU time	0.68 seconds
Started	Apr 28 12:57:29 PM PDT 24
Finished	Apr 28 12:57:31 PM PDT 24
Peak memory	200868 kb
Host	smart-a6cf4dbf-91e5-48c4-ada0-357e7a684d09
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750165653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.750165653
Directory	/workspace/42.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/42.clkmgr_div_intersig_mubi.2514302883
Short name	T533
Test name
Test status
Simulation time	23308060 ps
CPU time	0.82 seconds
Started	Apr 28 12:57:42 PM PDT 24
Finished	Apr 28 12:57:44 PM PDT 24
Peak memory	200732 kb
Host	smart-29a2d911-5051-4a38-9637-a7c471a6f563
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514302883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.2514302883
Directory	/workspace/42.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_extclk.166240686
Short name	T431
Test name
Test status
Simulation time	21752141 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:33 PM PDT 24
Finished	Apr 28 12:57:35 PM PDT 24
Peak memory	201000 kb
Host	smart-cbf0ef88-d116-4e75-876c-432aedcc7bcb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166240686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.166240686
Directory	/workspace/42.clkmgr_extclk/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency.484100326
Short name	T810
Test name
Test status
Simulation time	442725081 ps
CPU time	3.76 seconds
Started	Apr 28 12:57:29 PM PDT 24
Finished	Apr 28 12:57:33 PM PDT 24
Peak memory	201052 kb
Host	smart-fe14b058-ecb2-4e3b-8d01-47ee6a00c974
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484100326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.484100326
Directory	/workspace/42.clkmgr_frequency/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency_timeout.1711117312
Short name	T31
Test name
Test status
Simulation time	2176709138 ps
CPU time	15.33 seconds
Started	Apr 28 12:57:28 PM PDT 24
Finished	Apr 28 12:57:44 PM PDT 24
Peak memory	201220 kb
Host	smart-0ef214b0-bdf3-4dbf-ac78-1e16c6ac0e73
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711117312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t imeout.1711117312
Directory	/workspace/42.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/42.clkmgr_idle_intersig_mubi.2592551255
Short name	T772
Test name
Test status
Simulation time	22601425 ps
CPU time	0.86 seconds
Started	Apr 28 12:57:37 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	200960 kb
Host	smart-a934e0dd-d2bf-48a5-ac38-dee5033f4a22
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592551255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.2592551255
Directory	/workspace/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.1592973430
Short name	T353
Test name
Test status
Simulation time	125495479 ps
CPU time	1.15 seconds
Started	Apr 28 12:57:33 PM PDT 24
Finished	Apr 28 12:57:35 PM PDT 24
Peak memory	200988 kb
Host	smart-49b87bd1-30c5-45c6-b2e7-dfee2d13e9f4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592973430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_clk_byp_req_intersig_mubi.1592973430
Directory	/workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.522824236
Short name	T586
Test name
Test status
Simulation time	23841812 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:37 PM PDT 24
Finished	Apr 28 12:57:38 PM PDT 24
Peak memory	200880 kb
Host	smart-61eade29-3d11-437e-b2e8-70a3618a312d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522824236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.clkmgr_lc_ctrl_intersig_mubi.522824236
Directory	/workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_peri.1916396540
Short name	T249
Test name
Test status
Simulation time	27572533 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:32 PM PDT 24
Finished	Apr 28 12:57:33 PM PDT 24
Peak memory	200988 kb
Host	smart-b6b94f96-ca36-4137-a1d2-5fdca88e25f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916396540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.1916396540
Directory	/workspace/42.clkmgr_peri/latest

Test location	/workspace/coverage/default/42.clkmgr_regwen.1359856896
Short name	T676
Test name
Test status
Simulation time	897650896 ps
CPU time	3.61 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:41 PM PDT 24
Peak memory	200956 kb
Host	smart-92a8b063-74f2-4717-8627-cf2cf87feb93
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359856896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1359856896
Directory	/workspace/42.clkmgr_regwen/latest

Test location	/workspace/coverage/default/42.clkmgr_smoke.1942758472
Short name	T513
Test name
Test status
Simulation time	105596802 ps
CPU time	1.05 seconds
Started	Apr 28 12:57:33 PM PDT 24
Finished	Apr 28 12:57:35 PM PDT 24
Peak memory	201080 kb
Host	smart-58dd6877-817f-449b-bfb2-2f1fe8108f85
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942758472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1942758472
Directory	/workspace/42.clkmgr_smoke/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all.3287852390
Short name	T307
Test name
Test status
Simulation time	4614883883 ps
CPU time	25.28 seconds
Started	Apr 28 12:57:50 PM PDT 24
Finished	Apr 28 12:58:17 PM PDT 24
Peak memory	201164 kb
Host	smart-83c5d877-25f5-49f3-b8aa-2aba4b520359
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287852390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.3287852390
Directory	/workspace/42.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.626117526
Short name	T669
Test name
Test status
Simulation time	217034989863 ps
CPU time	1278.98 seconds
Started	Apr 28 12:57:35 PM PDT 24
Finished	Apr 28 01:18:54 PM PDT 24
Peak memory	209548 kb
Host	smart-33ea962d-432a-42fe-8027-c8c1681d602a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=626117526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.626117526
Directory	/workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.clkmgr_trans.635299707
Short name	T360
Test name
Test status
Simulation time	27795302 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:32 PM PDT 24
Finished	Apr 28 12:57:33 PM PDT 24
Peak memory	200992 kb
Host	smart-30e38e19-055f-4a22-b4d1-155a326de5a4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635299707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.635299707
Directory	/workspace/42.clkmgr_trans/latest

Test location	/workspace/coverage/default/43.clkmgr_alert_test.4242994765
Short name	T566
Test name
Test status
Simulation time	42801603 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:37 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	201012 kb
Host	smart-0e004320-a763-4519-a430-5737ffa08a9f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242994765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk mgr_alert_test.4242994765
Directory	/workspace/43.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2321732412
Short name	T414
Test name
Test status
Simulation time	40816400 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:32 PM PDT 24
Finished	Apr 28 12:57:34 PM PDT 24
Peak memory	200832 kb
Host	smart-ca8d61ff-4384-4e8f-a743-aca4b3224a0c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321732412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.2321732412
Directory	/workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_status.740640868
Short name	T487
Test name
Test status
Simulation time	17864888 ps
CPU time	0.72 seconds
Started	Apr 28 12:57:33 PM PDT 24
Finished	Apr 28 12:57:35 PM PDT 24
Peak memory	199860 kb
Host	smart-401070d4-e20d-4b76-8ad0-639ca29aeef0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740640868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.740640868
Directory	/workspace/43.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/43.clkmgr_div_intersig_mubi.2569953140
Short name	T383
Test name
Test status
Simulation time	44738809 ps
CPU time	0.82 seconds
Started	Apr 28 12:57:40 PM PDT 24
Finished	Apr 28 12:57:41 PM PDT 24
Peak memory	201040 kb
Host	smart-564d4d2e-152b-4fb2-9098-fa0d075f2bc0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569953140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.2569953140
Directory	/workspace/43.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_extclk.1574504705
Short name	T428
Test name
Test status
Simulation time	19449302 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:38 PM PDT 24
Peak memory	200984 kb
Host	smart-37a55759-557f-470d-ac79-32789c4b2d66
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574504705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.1574504705
Directory	/workspace/43.clkmgr_extclk/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency.1017870303
Short name	T577
Test name
Test status
Simulation time	1794735858 ps
CPU time	7.39 seconds
Started	Apr 28 12:57:41 PM PDT 24
Finished	Apr 28 12:57:49 PM PDT 24
Peak memory	200948 kb
Host	smart-e53cbaa0-ff0b-4e03-b3d8-bd9cd347772b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017870303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1017870303
Directory	/workspace/43.clkmgr_frequency/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency_timeout.2143919237
Short name	T251
Test name
Test status
Simulation time	874767975 ps
CPU time	4.08 seconds
Started	Apr 28 12:57:40 PM PDT 24
Finished	Apr 28 12:57:44 PM PDT 24
Peak memory	201172 kb
Host	smart-395af2ce-00d7-400f-a0bc-edabc6d1fa81
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143919237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t imeout.2143919237
Directory	/workspace/43.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/43.clkmgr_idle_intersig_mubi.473938548
Short name	T688
Test name
Test status
Simulation time	122030822 ps
CPU time	1.08 seconds
Started	Apr 28 12:57:32 PM PDT 24
Finished	Apr 28 12:57:34 PM PDT 24
Peak memory	200988 kb
Host	smart-f5069f1e-8167-45c6-a584-ec7021012bf4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473938548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.clkmgr_idle_intersig_mubi.473938548
Directory	/workspace/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.1643056378
Short name	T323
Test name
Test status
Simulation time	123097005 ps
CPU time	1.04 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:38 PM PDT 24
Peak memory	200868 kb
Host	smart-81f26bdb-7907-47b1-892d-da628905b706
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643056378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_clk_byp_req_intersig_mubi.1643056378
Directory	/workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.4235098880
Short name	T771
Test name
Test status
Simulation time	49059176 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:40 PM PDT 24
Finished	Apr 28 12:57:41 PM PDT 24
Peak memory	201044 kb
Host	smart-905e260e-0f61-4f74-9499-6cdd97823333
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235098880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_ctrl_intersig_mubi.4235098880
Directory	/workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_peri.1074381777
Short name	T716
Test name
Test status
Simulation time	16428737 ps
CPU time	0.72 seconds
Started	Apr 28 12:57:54 PM PDT 24
Finished	Apr 28 12:57:56 PM PDT 24
Peak memory	200772 kb
Host	smart-b1120397-914d-49b7-8cfc-fe6c7166dbeb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074381777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.1074381777
Directory	/workspace/43.clkmgr_peri/latest

Test location	/workspace/coverage/default/43.clkmgr_regwen.3336662370
Short name	T482
Test name
Test status
Simulation time	550336338 ps
CPU time	2.36 seconds
Started	Apr 28 12:57:40 PM PDT 24
Finished	Apr 28 12:57:42 PM PDT 24
Peak memory	201016 kb
Host	smart-25f076a8-08d4-4b4a-84e8-a566ee30a632
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336662370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3336662370
Directory	/workspace/43.clkmgr_regwen/latest

Test location	/workspace/coverage/default/43.clkmgr_smoke.3460259351
Short name	T202
Test name
Test status
Simulation time	30337081 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:32 PM PDT 24
Finished	Apr 28 12:57:34 PM PDT 24
Peak memory	200948 kb
Host	smart-14ca0e9c-24f4-4072-9078-c6b22edcd1b8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460259351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3460259351
Directory	/workspace/43.clkmgr_smoke/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all.81222178
Short name	T844
Test name
Test status
Simulation time	5178078625 ps
CPU time	17.56 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:55 PM PDT 24
Peak memory	201264 kb
Host	smart-a1801fd5-e253-4436-ac4a-cac3fab9709b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81222178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.clkmgr_stress_all.81222178
Directory	/workspace/43.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.4098402158
Short name	T126
Test name
Test status
Simulation time	43157923440 ps
CPU time	306.84 seconds
Started	Apr 28 12:57:54 PM PDT 24
Finished	Apr 28 01:03:02 PM PDT 24
Peak memory	217400 kb
Host	smart-815cb78b-f663-4763-846a-de13c7860967
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4098402158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.4098402158
Directory	/workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.clkmgr_trans.1715497878
Short name	T391
Test name
Test status
Simulation time	37902295 ps
CPU time	1.01 seconds
Started	Apr 28 12:57:32 PM PDT 24
Finished	Apr 28 12:57:34 PM PDT 24
Peak memory	200992 kb
Host	smart-ebbafd4d-2773-4572-892c-8436c5da7be0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715497878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1715497878
Directory	/workspace/43.clkmgr_trans/latest

Test location	/workspace/coverage/default/44.clkmgr_alert_test.1477263758
Short name	T796
Test name
Test status
Simulation time	82286149 ps
CPU time	0.99 seconds
Started	Apr 28 12:57:35 PM PDT 24
Finished	Apr 28 12:57:37 PM PDT 24
Peak memory	201068 kb
Host	smart-8a2ba578-6f94-4a5e-a2bd-66008b42c131
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477263758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk mgr_alert_test.1477263758
Directory	/workspace/44.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.952552034
Short name	T530
Test name
Test status
Simulation time	15924253 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:50 PM PDT 24
Finished	Apr 28 12:57:53 PM PDT 24
Peak memory	200888 kb
Host	smart-78321bcd-a7dc-4138-81a7-278dc4f3a53f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952552034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.952552034
Directory	/workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_status.3319236919
Short name	T689
Test name
Test status
Simulation time	16841179 ps
CPU time	0.71 seconds
Started	Apr 28 12:57:40 PM PDT 24
Finished	Apr 28 12:57:41 PM PDT 24
Peak memory	200056 kb
Host	smart-fc17af8e-d4e3-4ff0-91b3-08504d52362a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319236919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.3319236919
Directory	/workspace/44.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/44.clkmgr_div_intersig_mubi.1995110216
Short name	T364
Test name
Test status
Simulation time	75373771 ps
CPU time	1.03 seconds
Started	Apr 28 12:57:37 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	200896 kb
Host	smart-da7ee83d-8864-45ad-a754-17872289a2b3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995110216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.1995110216
Directory	/workspace/44.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_extclk.165653261
Short name	T660
Test name
Test status
Simulation time	35647011 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:31 PM PDT 24
Finished	Apr 28 12:57:32 PM PDT 24
Peak memory	200940 kb
Host	smart-2ae908cc-72e8-4140-8ffd-37643ee2587d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165653261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.165653261
Directory	/workspace/44.clkmgr_extclk/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency.2970243507
Short name	T406
Test name
Test status
Simulation time	1677902640 ps
CPU time	5.73 seconds
Started	Apr 28 12:57:42 PM PDT 24
Finished	Apr 28 12:57:49 PM PDT 24
Peak memory	200804 kb
Host	smart-b0c0ef68-d054-492f-8dd2-e80814926cbe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970243507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2970243507
Directory	/workspace/44.clkmgr_frequency/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency_timeout.1142703640
Short name	T304
Test name
Test status
Simulation time	1455102330 ps
CPU time	10.1 seconds
Started	Apr 28 12:57:52 PM PDT 24
Finished	Apr 28 12:58:03 PM PDT 24
Peak memory	200880 kb
Host	smart-0cfeae90-8130-4499-b8e2-ca79055bca5e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142703640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t imeout.1142703640
Directory	/workspace/44.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/44.clkmgr_idle_intersig_mubi.580584869
Short name	T745
Test name
Test status
Simulation time	26749767 ps
CPU time	0.88 seconds
Started	Apr 28 12:57:34 PM PDT 24
Finished	Apr 28 12:57:36 PM PDT 24
Peak memory	200864 kb
Host	smart-3b86038d-9c2a-4665-b97e-8b6911b1324f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580584869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.clkmgr_idle_intersig_mubi.580584869
Directory	/workspace/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.3452176055
Short name	T329
Test name
Test status
Simulation time	24522867 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:50 PM PDT 24
Finished	Apr 28 12:57:52 PM PDT 24
Peak memory	200740 kb
Host	smart-0f5f8b5a-3e76-4cc2-83e2-3fc361f0b776
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452176055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_clk_byp_req_intersig_mubi.3452176055
Directory	/workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.39675416
Short name	T213
Test name
Test status
Simulation time	54301258 ps
CPU time	0.83 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:38 PM PDT 24
Peak memory	200988 kb
Host	smart-b9224755-9b27-4271-9101-94789cccbac1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39675416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.39675416
Directory	/workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_peri.2561039214
Short name	T310
Test name
Test status
Simulation time	28289643 ps
CPU time	0.79 seconds
Started	Apr 28 12:57:40 PM PDT 24
Finished	Apr 28 12:57:41 PM PDT 24
Peak memory	200992 kb
Host	smart-53485dec-0d8c-4f01-a9fc-3008e30e3501
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561039214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2561039214
Directory	/workspace/44.clkmgr_peri/latest

Test location	/workspace/coverage/default/44.clkmgr_regwen.4221441158
Short name	T608
Test name
Test status
Simulation time	195938888 ps
CPU time	1.66 seconds
Started	Apr 28 12:57:33 PM PDT 24
Finished	Apr 28 12:57:36 PM PDT 24
Peak memory	200808 kb
Host	smart-e297968c-62d2-410e-b6a5-83be44ce6bce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221441158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.4221441158
Directory	/workspace/44.clkmgr_regwen/latest

Test location	/workspace/coverage/default/44.clkmgr_smoke.183736416
Short name	T538
Test name
Test status
Simulation time	24748877 ps
CPU time	0.85 seconds
Started	Apr 28 12:57:32 PM PDT 24
Finished	Apr 28 12:57:34 PM PDT 24
Peak memory	200884 kb
Host	smart-f2d19ec5-1757-4613-8e36-6d86d88d7fa7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183736416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.183736416
Directory	/workspace/44.clkmgr_smoke/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all.491242878
Short name	T499
Test name
Test status
Simulation time	6088186142 ps
CPU time	43.34 seconds
Started	Apr 28 12:57:35 PM PDT 24
Finished	Apr 28 12:58:19 PM PDT 24
Peak memory	201380 kb
Host	smart-fe62b0c1-7824-4271-abad-d83f67f6dda8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491242878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.491242878
Directory	/workspace/44.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.2865669212
Short name	T242
Test name
Test status
Simulation time	252527848019 ps
CPU time	1214.2 seconds
Started	Apr 28 12:57:33 PM PDT 24
Finished	Apr 28 01:17:49 PM PDT 24
Peak memory	209560 kb
Host	smart-616bfea1-9d80-44d5-ac88-caa03d33cfbe
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2865669212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.2865669212
Directory	/workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.clkmgr_trans.1768708469
Short name	T417
Test name
Test status
Simulation time	35720887 ps
CPU time	0.72 seconds
Started	Apr 28 12:57:52 PM PDT 24
Finished	Apr 28 12:57:54 PM PDT 24
Peak memory	200736 kb
Host	smart-2dc52aa4-7473-4e29-853d-59e4f9e81db3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768708469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1768708469
Directory	/workspace/44.clkmgr_trans/latest

Test location	/workspace/coverage/default/45.clkmgr_alert_test.1783061300
Short name	T212
Test name
Test status
Simulation time	17722560 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:45 PM PDT 24
Finished	Apr 28 12:57:46 PM PDT 24
Peak memory	200960 kb
Host	smart-57cceb6b-3c6e-4064-a89b-58e13ab3a832
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783061300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk mgr_alert_test.1783061300
Directory	/workspace/45.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.4078294156
Short name	T388
Test name
Test status
Simulation time	16285202 ps
CPU time	0.76 seconds
Started	Apr 28 12:57:35 PM PDT 24
Finished	Apr 28 12:57:36 PM PDT 24
Peak memory	200840 kb
Host	smart-27b8ff46-aefd-4c71-8286-d16df6c5cc8d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078294156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.4078294156
Directory	/workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_status.2464544599
Short name	T141
Test name
Test status
Simulation time	16554730 ps
CPU time	0.71 seconds
Started	Apr 28 12:57:42 PM PDT 24
Finished	Apr 28 12:57:43 PM PDT 24
Peak memory	200016 kb
Host	smart-e4898e2e-1f56-4a84-a0d6-a52b07413b59
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464544599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.2464544599
Directory	/workspace/45.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/45.clkmgr_div_intersig_mubi.402390793
Short name	T208
Test name
Test status
Simulation time	57911404 ps
CPU time	0.86 seconds
Started	Apr 28 12:57:33 PM PDT 24
Finished	Apr 28 12:57:35 PM PDT 24
Peak memory	200984 kb
Host	smart-6f0e9456-669e-414e-9de1-7575ab84f7dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402390793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.clkmgr_div_intersig_mubi.402390793
Directory	/workspace/45.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_extclk.98614610
Short name	T384
Test name
Test status
Simulation time	23730008 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:45 PM PDT 24
Finished	Apr 28 12:57:47 PM PDT 24
Peak memory	200900 kb
Host	smart-4596dcb0-061b-4fd4-ae9f-1579939cd5ea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98614610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.98614610
Directory	/workspace/45.clkmgr_extclk/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency.2686152863
Short name	T466
Test name
Test status
Simulation time	1995088541 ps
CPU time	15.1 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:52 PM PDT 24
Peak memory	201196 kb
Host	smart-9cde82b5-a043-46e8-aae4-d5a888361af6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686152863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.2686152863
Directory	/workspace/45.clkmgr_frequency/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency_timeout.3697591157
Short name	T769
Test name
Test status
Simulation time	1061548659 ps
CPU time	4.1 seconds
Started	Apr 28 12:57:34 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	200976 kb
Host	smart-8957d04f-5213-417a-aa79-98b5f2a2db21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697591157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t imeout.3697591157
Directory	/workspace/45.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/45.clkmgr_idle_intersig_mubi.742903174
Short name	T743
Test name
Test status
Simulation time	104068687 ps
CPU time	1.11 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	200880 kb
Host	smart-3ade6c47-ba8e-48bc-a1dd-ffd5d237d196
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742903174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.clkmgr_idle_intersig_mubi.742903174
Directory	/workspace/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1509082890
Short name	T809
Test name
Test status
Simulation time	29042171 ps
CPU time	0.83 seconds
Started	Apr 28 12:57:34 PM PDT 24
Finished	Apr 28 12:57:35 PM PDT 24
Peak memory	200932 kb
Host	smart-7475c6cf-476a-4847-a48a-83551d3badcf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509082890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1509082890
Directory	/workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.638909274
Short name	T514
Test name
Test status
Simulation time	35276204 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:37 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	201004 kb
Host	smart-f1dd0547-0cf3-4501-8b47-bda163d1e495
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638909274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.clkmgr_lc_ctrl_intersig_mubi.638909274
Directory	/workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_peri.1755755948
Short name	T701
Test name
Test status
Simulation time	18069104 ps
CPU time	0.76 seconds
Started	Apr 28 12:57:33 PM PDT 24
Finished	Apr 28 12:57:35 PM PDT 24
Peak memory	200880 kb
Host	smart-1fbaad42-9e6c-4f9d-b456-de711cb37668
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755755948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1755755948
Directory	/workspace/45.clkmgr_peri/latest

Test location	/workspace/coverage/default/45.clkmgr_regwen.518132851
Short name	T385
Test name
Test status
Simulation time	1120218233 ps
CPU time	4.08 seconds
Started	Apr 28 12:57:38 PM PDT 24
Finished	Apr 28 12:57:43 PM PDT 24
Peak memory	201148 kb
Host	smart-c8b3d7f5-910c-47e5-afc7-647b62173fea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518132851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.518132851
Directory	/workspace/45.clkmgr_regwen/latest

Test location	/workspace/coverage/default/45.clkmgr_smoke.2970770480
Short name	T712
Test name
Test status
Simulation time	36625851 ps
CPU time	0.9 seconds
Started	Apr 28 12:57:34 PM PDT 24
Finished	Apr 28 12:57:36 PM PDT 24
Peak memory	201084 kb
Host	smart-b4b6ead5-203c-4a15-b0dd-3a0b67ecc201
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970770480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2970770480
Directory	/workspace/45.clkmgr_smoke/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all.2903618849
Short name	T419
Test name
Test status
Simulation time	3940443771 ps
CPU time	21.01 seconds
Started	Apr 28 12:57:35 PM PDT 24
Finished	Apr 28 12:57:57 PM PDT 24
Peak memory	201276 kb
Host	smart-ba124bb1-0678-43bb-bb34-194b789bd141
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903618849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.2903618849
Directory	/workspace/45.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.138339340
Short name	T137
Test name
Test status
Simulation time	63330854823 ps
CPU time	355.41 seconds
Started	Apr 28 12:57:39 PM PDT 24
Finished	Apr 28 01:03:35 PM PDT 24
Peak memory	209564 kb
Host	smart-4b190cf7-a14c-414a-bd56-da3806130537
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=138339340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.138339340
Directory	/workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.clkmgr_trans.3328338140
Short name	T476
Test name
Test status
Simulation time	18011703 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:34 PM PDT 24
Finished	Apr 28 12:57:36 PM PDT 24
Peak memory	200892 kb
Host	smart-eb4abe26-9b12-47ac-9ac8-a0d450642e1c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328338140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3328338140
Directory	/workspace/45.clkmgr_trans/latest

Test location	/workspace/coverage/default/46.clkmgr_alert_test.3615619081
Short name	T727
Test name
Test status
Simulation time	13219469 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:51 PM PDT 24
Finished	Apr 28 12:57:53 PM PDT 24
Peak memory	201068 kb
Host	smart-b05a7327-9771-4bf3-80f5-8c70d9cdc5e1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615619081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk mgr_alert_test.3615619081
Directory	/workspace/46.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.2248816905
Short name	T838
Test name
Test status
Simulation time	18957989 ps
CPU time	0.78 seconds
Started	Apr 28 12:57:35 PM PDT 24
Finished	Apr 28 12:57:36 PM PDT 24
Peak memory	200984 kb
Host	smart-4d0ba781-fc59-4898-9285-dcb04fb71924
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248816905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.2248816905
Directory	/workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_status.3517239797
Short name	T591
Test name
Test status
Simulation time	73378322 ps
CPU time	0.83 seconds
Started	Apr 28 12:57:42 PM PDT 24
Finished	Apr 28 12:57:43 PM PDT 24
Peak memory	200872 kb
Host	smart-d741b72a-bd60-4989-9581-b8e4506e7ffc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517239797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3517239797
Directory	/workspace/46.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/46.clkmgr_div_intersig_mubi.1012430812
Short name	T42
Test name
Test status
Simulation time	18738799 ps
CPU time	0.78 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:38 PM PDT 24
Peak memory	200904 kb
Host	smart-a180dbde-67a2-4994-a20a-deff95e82a5e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012430812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.1012430812
Directory	/workspace/46.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_extclk.1403933702
Short name	T378
Test name
Test status
Simulation time	21898268 ps
CPU time	0.81 seconds
Started	Apr 28 12:57:38 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	201028 kb
Host	smart-36641a1b-69c4-4da6-ac0b-20fdf08130b5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403933702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1403933702
Directory	/workspace/46.clkmgr_extclk/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency.966478048
Short name	T459
Test name
Test status
Simulation time	323599375 ps
CPU time	2.95 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:40 PM PDT 24
Peak memory	201004 kb
Host	smart-f8ddb0ba-c167-4383-ad32-4fe9abe037f3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966478048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.966478048
Directory	/workspace/46.clkmgr_frequency/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency_timeout.372424226
Short name	T680
Test name
Test status
Simulation time	2373940754 ps
CPU time	7.22 seconds
Started	Apr 28 12:57:42 PM PDT 24
Finished	Apr 28 12:57:50 PM PDT 24
Peak memory	201316 kb
Host	smart-b4b95da7-3932-43fb-ad1a-46e1521a4d87
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372424226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_ti meout.372424226
Directory	/workspace/46.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/46.clkmgr_idle_intersig_mubi.657512255
Short name	T95
Test name
Test status
Simulation time	46544357 ps
CPU time	0.97 seconds
Started	Apr 28 12:57:45 PM PDT 24
Finished	Apr 28 12:57:47 PM PDT 24
Peak memory	201028 kb
Host	smart-9e862f15-68a8-4178-a867-2188421091aa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657512255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.clkmgr_idle_intersig_mubi.657512255
Directory	/workspace/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1268265180
Short name	T651
Test name
Test status
Simulation time	24519159 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:37 PM PDT 24
Peak memory	200884 kb
Host	smart-c1ae3d03-a3cd-48a0-af85-ed412bbc48bc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268265180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1268265180
Directory	/workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3092416266
Short name	T423
Test name
Test status
Simulation time	28132979 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:57:38 PM PDT 24
Peak memory	201012 kb
Host	smart-a2719566-2f4e-43de-84c9-a85b9e4a5b7f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092416266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_ctrl_intersig_mubi.3092416266
Directory	/workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_peri.3378437673
Short name	T486
Test name
Test status
Simulation time	16791220 ps
CPU time	0.71 seconds
Started	Apr 28 12:57:44 PM PDT 24
Finished	Apr 28 12:57:45 PM PDT 24
Peak memory	201024 kb
Host	smart-41b9c299-2806-40fd-875d-b831abea1052
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378437673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3378437673
Directory	/workspace/46.clkmgr_peri/latest

Test location	/workspace/coverage/default/46.clkmgr_regwen.1273218313
Short name	T266
Test name
Test status
Simulation time	1033501860 ps
CPU time	3.85 seconds
Started	Apr 28 12:57:47 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	201048 kb
Host	smart-1dd13ee3-e9fe-4e63-bf89-f1ead7fc1d8e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273218313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1273218313
Directory	/workspace/46.clkmgr_regwen/latest

Test location	/workspace/coverage/default/46.clkmgr_smoke.24645716
Short name	T777
Test name
Test status
Simulation time	40411825 ps
CPU time	0.92 seconds
Started	Apr 28 12:57:42 PM PDT 24
Finished	Apr 28 12:57:43 PM PDT 24
Peak memory	200960 kb
Host	smart-9df4dcc5-4c70-43a7-bfc5-16c2a735fc94
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24645716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.24645716
Directory	/workspace/46.clkmgr_smoke/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all.3545573863
Short name	T836
Test name
Test status
Simulation time	14509560881 ps
CPU time	53.35 seconds
Started	Apr 28 12:57:36 PM PDT 24
Finished	Apr 28 12:58:30 PM PDT 24
Peak memory	201436 kb
Host	smart-5a548c25-36d8-4bd3-8d5f-2113aa0beac7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545573863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.3545573863
Directory	/workspace/46.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.1791875712
Short name	T632
Test name
Test status
Simulation time	27486170847 ps
CPU time	394.44 seconds
Started	Apr 28 12:57:38 PM PDT 24
Finished	Apr 28 01:04:13 PM PDT 24
Peak memory	209728 kb
Host	smart-da931692-bfa8-4cb1-ae2a-e8894d166554
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1791875712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.1791875712
Directory	/workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.clkmgr_trans.2456404404
Short name	T173
Test name
Test status
Simulation time	51322531 ps
CPU time	1.03 seconds
Started	Apr 28 12:57:37 PM PDT 24
Finished	Apr 28 12:57:39 PM PDT 24
Peak memory	200960 kb
Host	smart-50c8b3cb-76d6-4180-83ff-e65290a6c51b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456404404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2456404404
Directory	/workspace/46.clkmgr_trans/latest

Test location	/workspace/coverage/default/47.clkmgr_alert_test.3446468352
Short name	T650
Test name
Test status
Simulation time	15207440 ps
CPU time	0.75 seconds
Started	Apr 28 12:57:46 PM PDT 24
Finished	Apr 28 12:57:48 PM PDT 24
Peak memory	201032 kb
Host	smart-71b90488-a928-4d16-875c-287fef877864
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446468352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk mgr_alert_test.3446468352
Directory	/workspace/47.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.1463130722
Short name	T398
Test name
Test status
Simulation time	226724159 ps
CPU time	1.48 seconds
Started	Apr 28 12:57:52 PM PDT 24
Finished	Apr 28 12:57:55 PM PDT 24
Peak memory	200812 kb
Host	smart-5b9a6d71-d15c-4cec-ad7b-1d216000abcd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463130722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.1463130722
Directory	/workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_status.2405605727
Short name	T144
Test name
Test status
Simulation time	17262982 ps
CPU time	0.73 seconds
Started	Apr 28 12:57:52 PM PDT 24
Finished	Apr 28 12:57:54 PM PDT 24
Peak memory	199996 kb
Host	smart-1eb0bb55-bf0b-4ec0-ae87-34154e382cb1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405605727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2405605727
Directory	/workspace/47.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/47.clkmgr_div_intersig_mubi.2354089940
Short name	T596
Test name
Test status
Simulation time	19619968 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:43 PM PDT 24
Finished	Apr 28 12:57:44 PM PDT 24
Peak memory	200988 kb
Host	smart-aa59fe52-f1ac-4128-9efc-4d985ea9b950
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354089940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.2354089940
Directory	/workspace/47.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_extclk.1437527230
Short name	T258
Test name
Test status
Simulation time	23058901 ps
CPU time	0.9 seconds
Started	Apr 28 12:57:53 PM PDT 24
Finished	Apr 28 12:57:55 PM PDT 24
Peak memory	201000 kb
Host	smart-6fd11540-492d-4a17-8704-12b60544c05f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437527230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1437527230
Directory	/workspace/47.clkmgr_extclk/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency.2508587830
Short name	T603
Test name
Test status
Simulation time	1054812259 ps
CPU time	6.08 seconds
Started	Apr 28 12:57:43 PM PDT 24
Finished	Apr 28 12:57:50 PM PDT 24
Peak memory	201084 kb
Host	smart-f1020576-9eb7-4430-9c55-5d00a24efe31
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508587830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.2508587830
Directory	/workspace/47.clkmgr_frequency/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency_timeout.392586528
Short name	T831
Test name
Test status
Simulation time	261559662 ps
CPU time	1.82 seconds
Started	Apr 28 12:57:47 PM PDT 24
Finished	Apr 28 12:57:49 PM PDT 24
Peak memory	201084 kb
Host	smart-1f60e9a4-d6e5-4d0d-acb5-d47fb559e070
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392586528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_ti meout.392586528
Directory	/workspace/47.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/47.clkmgr_idle_intersig_mubi.1387069183
Short name	T524
Test name
Test status
Simulation time	22979176 ps
CPU time	0.76 seconds
Started	Apr 28 12:57:40 PM PDT 24
Finished	Apr 28 12:57:41 PM PDT 24
Peak memory	200752 kb
Host	smart-71db2b2a-1540-4c54-8e37-dbb5bac9f6cb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387069183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.1387069183
Directory	/workspace/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2788622162
Short name	T452
Test name
Test status
Simulation time	15309323 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:47 PM PDT 24
Finished	Apr 28 12:57:48 PM PDT 24
Peak memory	200952 kb
Host	smart-7cf3e70c-f144-414e-bb7f-7b669f0a0b44
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788622162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_clk_byp_req_intersig_mubi.2788622162
Directory	/workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.3057752112
Short name	T587
Test name
Test status
Simulation time	18665510 ps
CPU time	0.79 seconds
Started	Apr 28 12:57:39 PM PDT 24
Finished	Apr 28 12:57:41 PM PDT 24
Peak memory	200832 kb
Host	smart-9373a493-1d9a-451b-8943-e1aaea8e0551
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057752112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_ctrl_intersig_mubi.3057752112
Directory	/workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_peri.175071131
Short name	T167
Test name
Test status
Simulation time	37032155 ps
CPU time	0.77 seconds
Started	Apr 28 12:57:45 PM PDT 24
Finished	Apr 28 12:57:46 PM PDT 24
Peak memory	201016 kb
Host	smart-6e86d93a-1701-4506-8261-4f88f53ce186
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175071131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.175071131
Directory	/workspace/47.clkmgr_peri/latest

Test location	/workspace/coverage/default/47.clkmgr_regwen.3442159877
Short name	T235
Test name
Test status
Simulation time	445359874 ps
CPU time	2.04 seconds
Started	Apr 28 12:57:51 PM PDT 24
Finished	Apr 28 12:57:55 PM PDT 24
Peak memory	201004 kb
Host	smart-036f74e2-b418-4bcc-ac6b-238417e981e1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442159877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.3442159877
Directory	/workspace/47.clkmgr_regwen/latest

Test location	/workspace/coverage/default/47.clkmgr_smoke.3702573503
Short name	T352
Test name
Test status
Simulation time	16092693 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 12:57:52 PM PDT 24
Peak memory	201060 kb
Host	smart-6c7063e8-1f57-4911-b82f-489b2ceb59e7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702573503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.3702573503
Directory	/workspace/47.clkmgr_smoke/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all.275142441
Short name	T812
Test name
Test status
Simulation time	3208662757 ps
CPU time	12.84 seconds
Started	Apr 28 12:57:37 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	201324 kb
Host	smart-fbe129a1-126a-4bef-854f-341bb278aadf
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275142441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.275142441
Directory	/workspace/47.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.1767523775
Short name	T681
Test name
Test status
Simulation time	10390074488 ps
CPU time	185.17 seconds
Started	Apr 28 12:57:45 PM PDT 24
Finished	Apr 28 01:00:51 PM PDT 24
Peak memory	209520 kb
Host	smart-dc27e531-79d2-41ff-ad2e-be6cf1786ce3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1767523775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.1767523775
Directory	/workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.clkmgr_trans.1731507875
Short name	T839
Test name
Test status
Simulation time	58549809 ps
CPU time	0.89 seconds
Started	Apr 28 12:57:38 PM PDT 24
Finished	Apr 28 12:57:40 PM PDT 24
Peak memory	200880 kb
Host	smart-899140b6-6fd1-494a-88a5-51f921b94767
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731507875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1731507875
Directory	/workspace/47.clkmgr_trans/latest

Test location	/workspace/coverage/default/48.clkmgr_alert_test.201653414
Short name	T497
Test name
Test status
Simulation time	12810656 ps
CPU time	0.74 seconds
Started	Apr 28 12:57:48 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	200900 kb
Host	smart-9c894e2b-edc3-4fa6-baf9-5c218ffa75d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201653414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm gr_alert_test.201653414
Directory	/workspace/48.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.3892669824
Short name	T842
Test name
Test status
Simulation time	15112602 ps
CPU time	0.79 seconds
Started	Apr 28 12:57:48 PM PDT 24
Finished	Apr 28 12:57:49 PM PDT 24
Peak memory	200868 kb
Host	smart-6fb87240-d541-4434-b194-691f0d326886
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892669824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.3892669824
Directory	/workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_status.3718650049
Short name	T813
Test name
Test status
Simulation time	43199156 ps
CPU time	0.8 seconds
Started	Apr 28 12:57:50 PM PDT 24
Finished	Apr 28 12:57:52 PM PDT 24
Peak memory	199916 kb
Host	smart-0d1af1cd-4d54-4dde-9fb3-63321d131bd5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718650049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3718650049
Directory	/workspace/48.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/48.clkmgr_div_intersig_mubi.3821323097
Short name	T365
Test name
Test status
Simulation time	37859317 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	201012 kb
Host	smart-899793db-453f-4493-9caa-715e83b8ce48
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821323097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.3821323097
Directory	/workspace/48.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_extclk.722885165
Short name	T43
Test name
Test status
Simulation time	16528012 ps
CPU time	0.78 seconds
Started	Apr 28 12:57:43 PM PDT 24
Finished	Apr 28 12:57:44 PM PDT 24
Peak memory	201008 kb
Host	smart-e7ca4f34-ef57-4c82-bfc1-2fa29c2522a0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722885165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.722885165
Directory	/workspace/48.clkmgr_extclk/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency.1738904672
Short name	T735
Test name
Test status
Simulation time	927144538 ps
CPU time	3.56 seconds
Started	Apr 28 12:57:39 PM PDT 24
Finished	Apr 28 12:57:43 PM PDT 24
Peak memory	201028 kb
Host	smart-163dc0fd-5c26-4f60-abc8-154efbddf5f3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738904672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1738904672
Directory	/workspace/48.clkmgr_frequency/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency_timeout.1656805809
Short name	T515
Test name
Test status
Simulation time	615866062 ps
CPU time	4.8 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 12:57:55 PM PDT 24
Peak memory	201112 kb
Host	smart-6d60b90a-cebd-4e14-85af-409f12a31941
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656805809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t imeout.1656805809
Directory	/workspace/48.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/48.clkmgr_idle_intersig_mubi.3184425278
Short name	T188
Test name
Test status
Simulation time	27708869 ps
CPU time	0.96 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	200900 kb
Host	smart-bc102f04-8c28-4d6d-b850-a8fbc059d41f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184425278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.3184425278
Directory	/workspace/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.481776460
Short name	T94
Test name
Test status
Simulation time	86247935 ps
CPU time	0.98 seconds
Started	Apr 28 12:57:46 PM PDT 24
Finished	Apr 28 12:57:48 PM PDT 24
Peak memory	201008 kb
Host	smart-e4a2819f-d208-4130-a205-5977e37196ef
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481776460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.clkmgr_lc_clk_byp_req_intersig_mubi.481776460
Directory	/workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.3410839281
Short name	T21
Test name
Test status
Simulation time	45791491 ps
CPU time	0.93 seconds
Started	Apr 28 12:57:48 PM PDT 24
Finished	Apr 28 12:57:49 PM PDT 24
Peak memory	200956 kb
Host	smart-b83cd34a-abaa-4d02-a53c-136fce91dc8c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410839281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_ctrl_intersig_mubi.3410839281
Directory	/workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_peri.902546852
Short name	T605
Test name
Test status
Simulation time	16324684 ps
CPU time	0.73 seconds
Started	Apr 28 12:57:50 PM PDT 24
Finished	Apr 28 12:57:52 PM PDT 24
Peak memory	200828 kb
Host	smart-4073c390-cb9f-4fa3-939b-96678e560783
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902546852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.902546852
Directory	/workspace/48.clkmgr_peri/latest

Test location	/workspace/coverage/default/48.clkmgr_regwen.4258265635
Short name	T335
Test name
Test status
Simulation time	1128582465 ps
CPU time	4.81 seconds
Started	Apr 28 12:57:55 PM PDT 24
Finished	Apr 28 12:58:01 PM PDT 24
Peak memory	201160 kb
Host	smart-dc2daf40-bc3e-4cba-8c77-ab0dafcc4cba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258265635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.4258265635
Directory	/workspace/48.clkmgr_regwen/latest

Test location	/workspace/coverage/default/48.clkmgr_smoke.3777258204
Short name	T41
Test name
Test status
Simulation time	68081880 ps
CPU time	1.01 seconds
Started	Apr 28 12:57:45 PM PDT 24
Finished	Apr 28 12:57:47 PM PDT 24
Peak memory	201072 kb
Host	smart-b5e14125-79fe-4ad5-9f6d-eff13fbea7ae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777258204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.3777258204
Directory	/workspace/48.clkmgr_smoke/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.3036916702
Short name	T730
Test name
Test status
Simulation time	14662629322 ps
CPU time	263.4 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 01:02:13 PM PDT 24
Peak memory	209720 kb
Host	smart-a3eafe95-c15f-4947-a499-ed2d0c474a14
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3036916702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.3036916702
Directory	/workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.clkmgr_trans.2408056114
Short name	T734
Test name
Test status
Simulation time	18434589 ps
CPU time	0.85 seconds
Started	Apr 28 12:57:44 PM PDT 24
Finished	Apr 28 12:57:45 PM PDT 24
Peak memory	200996 kb
Host	smart-bedd38f6-b9a8-4f54-9473-478fa4b7b3f2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408056114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.2408056114
Directory	/workspace/48.clkmgr_trans/latest

Test location	/workspace/coverage/default/49.clkmgr_alert_test.61131413
Short name	T356
Test name
Test status
Simulation time	39529232 ps
CPU time	0.79 seconds
Started	Apr 28 12:57:48 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	201096 kb
Host	smart-b7847d08-8ad9-46b8-a452-b59a4bbf4f71
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61131413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmg r_alert_test.61131413
Directory	/workspace/49.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.2875693718
Short name	T45
Test name
Test status
Simulation time	36837213 ps
CPU time	0.87 seconds
Started	Apr 28 12:57:44 PM PDT 24
Finished	Apr 28 12:57:46 PM PDT 24
Peak memory	200832 kb
Host	smart-eb150d29-224f-4b30-9250-e3c6facc07e2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875693718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.2875693718
Directory	/workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_status.4187057616
Short name	T784
Test name
Test status
Simulation time	32523715 ps
CPU time	0.74 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 12:57:51 PM PDT 24
Peak memory	199896 kb
Host	smart-5b62ca09-9232-486c-9d2e-9ffceb23d26d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187057616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.4187057616
Directory	/workspace/49.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/49.clkmgr_div_intersig_mubi.3439391010
Short name	T281
Test name
Test status
Simulation time	27287926 ps
CPU time	0.89 seconds
Started	Apr 28 12:57:50 PM PDT 24
Finished	Apr 28 12:57:53 PM PDT 24
Peak memory	200896 kb
Host	smart-f5bcb52c-e7a9-4d9d-bc69-8dd6f996090a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439391010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.3439391010
Directory	/workspace/49.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_extclk.3017950752
Short name	T714
Test name
Test status
Simulation time	28058092 ps
CPU time	0.91 seconds
Started	Apr 28 12:57:47 PM PDT 24
Finished	Apr 28 12:57:49 PM PDT 24
Peak memory	200964 kb
Host	smart-6d49752f-74a1-4636-abff-8a70f892e937
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017950752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3017950752
Directory	/workspace/49.clkmgr_extclk/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency.3836669787
Short name	T686
Test name
Test status
Simulation time	2356100789 ps
CPU time	17.54 seconds
Started	Apr 28 12:57:50 PM PDT 24
Finished	Apr 28 12:58:10 PM PDT 24
Peak memory	201220 kb
Host	smart-7b29d66d-b807-4f71-a4dd-7bcef4ffd0b1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836669787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3836669787
Directory	/workspace/49.clkmgr_frequency/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency_timeout.2396916084
Short name	T197
Test name
Test status
Simulation time	1005040795 ps
CPU time	4.38 seconds
Started	Apr 28 12:57:48 PM PDT 24
Finished	Apr 28 12:57:54 PM PDT 24
Peak memory	201096 kb
Host	smart-de679775-df80-41c6-a176-464bb954213e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396916084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t imeout.2396916084
Directory	/workspace/49.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.352103110
Short name	T371
Test name
Test status
Simulation time	99638374 ps
CPU time	1.07 seconds
Started	Apr 28 12:57:46 PM PDT 24
Finished	Apr 28 12:57:48 PM PDT 24
Peak memory	201012 kb
Host	smart-6ab5235a-2246-4eb2-a4b1-20f6dc3c9e4c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352103110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.clkmgr_lc_clk_byp_req_intersig_mubi.352103110
Directory	/workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3103904733
Short name	T246
Test name
Test status
Simulation time	68827120 ps
CPU time	0.95 seconds
Started	Apr 28 12:57:51 PM PDT 24
Finished	Apr 28 12:57:54 PM PDT 24
Peak memory	200892 kb
Host	smart-7219eb39-3a32-4804-9228-e07fc3e076d7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103904733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_ctrl_intersig_mubi.3103904733
Directory	/workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_peri.2782044845
Short name	T560
Test name
Test status
Simulation time	39785591 ps
CPU time	0.78 seconds
Started	Apr 28 12:57:51 PM PDT 24
Finished	Apr 28 12:57:53 PM PDT 24
Peak memory	200868 kb
Host	smart-c1785116-6c90-4c75-a3a0-ce131c92dac8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782044845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.2782044845
Directory	/workspace/49.clkmgr_peri/latest

Test location	/workspace/coverage/default/49.clkmgr_regwen.4190040002
Short name	T713
Test name
Test status
Simulation time	1049021830 ps
CPU time	4.34 seconds
Started	Apr 28 12:57:53 PM PDT 24
Finished	Apr 28 12:57:58 PM PDT 24
Peak memory	200972 kb
Host	smart-8f0d5be2-7aad-4eaa-9013-1ea3ca7519c8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190040002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.4190040002
Directory	/workspace/49.clkmgr_regwen/latest

Test location	/workspace/coverage/default/49.clkmgr_smoke.3562784367
Short name	T182
Test name
Test status
Simulation time	33929751 ps
CPU time	0.84 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 12:57:52 PM PDT 24
Peak memory	200964 kb
Host	smart-6a2dc57a-3ea2-4c95-8d1f-169467e8629b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562784367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3562784367
Directory	/workspace/49.clkmgr_smoke/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all.1275622745
Short name	T641
Test name
Test status
Simulation time	1827576996 ps
CPU time	13.68 seconds
Started	Apr 28 12:57:54 PM PDT 24
Finished	Apr 28 12:58:09 PM PDT 24
Peak memory	201116 kb
Host	smart-b8c9e16f-e32b-407f-8f80-f3dc99d2ed73
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275622745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.1275622745
Directory	/workspace/49.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.3038660776
Short name	T830
Test name
Test status
Simulation time	143814161077 ps
CPU time	808.67 seconds
Started	Apr 28 12:57:49 PM PDT 24
Finished	Apr 28 01:11:20 PM PDT 24
Peak memory	209660 kb
Host	smart-376d6059-c212-4595-975b-b93f7ccf7d9c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3038660776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.3038660776
Directory	/workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.clkmgr_trans.3787307781
Short name	T230
Test name
Test status
Simulation time	18507719 ps
CPU time	0.85 seconds
Started	Apr 28 12:57:50 PM PDT 24
Finished	Apr 28 12:57:53 PM PDT 24
Peak memory	200808 kb
Host	smart-79f4208f-158b-4f75-90df-aba1216dab01
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787307781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3787307781
Directory	/workspace/49.clkmgr_trans/latest

Test location	/workspace/coverage/default/5.clkmgr_alert_test.2619922387
Short name	T640
Test name
Test status
Simulation time	33923388 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:07 PM PDT 24
Finished	Apr 28 12:56:09 PM PDT 24
Peak memory	200944 kb
Host	smart-73bfb1d3-93be-4bf8-a395-db6cebd3f354
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619922387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm gr_alert_test.2619922387
Directory	/workspace/5.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3149411363
Short name	T77
Test name
Test status
Simulation time	22964870 ps
CPU time	1.06 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	200988 kb
Host	smart-f8926c54-d2fe-4636-bf51-65024eabb0a3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149411363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.3149411363
Directory	/workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_status.739561622
Short name	T683
Test name
Test status
Simulation time	16426250 ps
CPU time	0.73 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:02 PM PDT 24
Peak memory	200872 kb
Host	smart-f28b8e09-3b09-491b-9459-04a1e2e12657
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739561622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.739561622
Directory	/workspace/5.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/5.clkmgr_div_intersig_mubi.3106070048
Short name	T183
Test name
Test status
Simulation time	77290571 ps
CPU time	1.14 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:56:01 PM PDT 24
Peak memory	201004 kb
Host	smart-2e43f97c-dffb-431a-8b48-7f80c5e2f886
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106070048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.3106070048
Directory	/workspace/5.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_extclk.3744145628
Short name	T351
Test name
Test status
Simulation time	41971614 ps
CPU time	0.86 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:03 PM PDT 24
Peak memory	200968 kb
Host	smart-e237a342-dd01-4848-ac2c-6210245dcd87
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744145628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.3744145628
Directory	/workspace/5.clkmgr_extclk/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency.1277147068
Short name	T778
Test name
Test status
Simulation time	2009529027 ps
CPU time	10.05 seconds
Started	Apr 28 12:56:00 PM PDT 24
Finished	Apr 28 12:56:11 PM PDT 24
Peak memory	201200 kb
Host	smart-6408b179-e882-48e5-9aff-2f237487e0a9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277147068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.1277147068
Directory	/workspace/5.clkmgr_frequency/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency_timeout.520035871
Short name	T545
Test name
Test status
Simulation time	1234351966 ps
CPU time	5.32 seconds
Started	Apr 28 12:56:00 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	201084 kb
Host	smart-47bb2550-4c09-4864-a6d1-b075ab96f2eb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520035871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_tim eout.520035871
Directory	/workspace/5.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3991605433
Short name	T798
Test name
Test status
Simulation time	221650929 ps
CPU time	1.51 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:56:02 PM PDT 24
Peak memory	200904 kb
Host	smart-eb20945b-58d8-47a2-8cc1-24e7bdaa44ee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991605433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.3991605433
Directory	/workspace/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.3187085315
Short name	T853
Test name
Test status
Simulation time	61113009 ps
CPU time	0.89 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:56:01 PM PDT 24
Peak memory	201004 kb
Host	smart-594d0682-a5a1-4035-ae2f-945fad989a2e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187085315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_clk_byp_req_intersig_mubi.3187085315
Directory	/workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2013979625
Short name	T841
Test name
Test status
Simulation time	44016279 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:03 PM PDT 24
Peak memory	201004 kb
Host	smart-7c744609-d778-40e6-921f-72460b9449f4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013979625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_ctrl_intersig_mubi.2013979625
Directory	/workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_peri.2510893456
Short name	T311
Test name
Test status
Simulation time	24174323 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:02 PM PDT 24
Finished	Apr 28 12:56:04 PM PDT 24
Peak memory	200872 kb
Host	smart-0efab36c-01ec-4849-b0f1-d528636f4243
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510893456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.2510893456
Directory	/workspace/5.clkmgr_peri/latest

Test location	/workspace/coverage/default/5.clkmgr_regwen.1301797069
Short name	T638
Test name
Test status
Simulation time	406623586 ps
CPU time	1.72 seconds
Started	Apr 28 12:55:59 PM PDT 24
Finished	Apr 28 12:56:01 PM PDT 24
Peak memory	200900 kb
Host	smart-48438a44-f11a-46cd-9eba-b14a8555d64f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301797069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1301797069
Directory	/workspace/5.clkmgr_regwen/latest

Test location	/workspace/coverage/default/5.clkmgr_smoke.184714248
Short name	T124
Test name
Test status
Simulation time	185301183 ps
CPU time	1.29 seconds
Started	Apr 28 12:56:09 PM PDT 24
Finished	Apr 28 12:56:11 PM PDT 24
Peak memory	201028 kb
Host	smart-fe887412-a137-45d6-afcd-b6698c281143
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184714248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.184714248
Directory	/workspace/5.clkmgr_smoke/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all.254834480
Short name	T576
Test name
Test status
Simulation time	4703760934 ps
CPU time	33.21 seconds
Started	Apr 28 12:56:07 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	201332 kb
Host	smart-a23e85a5-2768-4747-bf79-7651574ba350
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254834480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.254834480
Directory	/workspace/5.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.2057394645
Short name	T719
Test name
Test status
Simulation time	70126150496 ps
CPU time	758.32 seconds
Started	Apr 28 12:56:03 PM PDT 24
Finished	Apr 28 01:08:42 PM PDT 24
Peak memory	217728 kb
Host	smart-f80412e8-1fb3-44c0-83e7-09cd5391ffd0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2057394645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.2057394645
Directory	/workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.clkmgr_trans.2199163849
Short name	T226
Test name
Test status
Simulation time	133761113 ps
CPU time	1.27 seconds
Started	Apr 28 12:56:01 PM PDT 24
Finished	Apr 28 12:56:03 PM PDT 24
Peak memory	200856 kb
Host	smart-30c603ed-50f0-4741-ab3b-7c91caf647c0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199163849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2199163849
Directory	/workspace/5.clkmgr_trans/latest

Test location	/workspace/coverage/default/6.clkmgr_alert_test.247760076
Short name	T590
Test name
Test status
Simulation time	41344978 ps
CPU time	0.83 seconds
Started	Apr 28 12:56:06 PM PDT 24
Finished	Apr 28 12:56:08 PM PDT 24
Peak memory	201076 kb
Host	smart-f1678c93-a59d-4401-845f-7306bed748e5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247760076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg r_alert_test.247760076
Directory	/workspace/6.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.887064764
Short name	T46
Test name
Test status
Simulation time	232950154 ps
CPU time	1.36 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:08 PM PDT 24
Peak memory	200900 kb
Host	smart-ac1149b5-e5f1-4f8f-a098-941b6cca49fc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887064764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.887064764
Directory	/workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_status.2225476950
Short name	T642
Test name
Test status
Simulation time	23359864 ps
CPU time	0.72 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	200720 kb
Host	smart-a037fc1f-6d52-45dc-8d8e-1760564031f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225476950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2225476950
Directory	/workspace/6.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/6.clkmgr_div_intersig_mubi.3858742787
Short name	T583
Test name
Test status
Simulation time	67125413 ps
CPU time	0.98 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:06 PM PDT 24
Peak memory	200892 kb
Host	smart-0fa7f0ef-0f8a-48bb-9ff8-f24ebd228485
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858742787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.3858742787
Directory	/workspace/6.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_extclk.997296403
Short name	T780
Test name
Test status
Simulation time	30634572 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:15 PM PDT 24
Peak memory	200996 kb
Host	smart-1740c0dd-e98c-4afd-a70e-e46d180e4b93
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997296403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.997296403
Directory	/workspace/6.clkmgr_extclk/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency.538523591
Short name	T551
Test name
Test status
Simulation time	1424290450 ps
CPU time	6.03 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:11 PM PDT 24
Peak memory	201060 kb
Host	smart-a88b7a3d-8716-4dc8-9dae-933880b25ee8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538523591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.538523591
Directory	/workspace/6.clkmgr_frequency/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency_timeout.804921039
Short name	T220
Test name
Test status
Simulation time	137912568 ps
CPU time	1.27 seconds
Started	Apr 28 12:56:06 PM PDT 24
Finished	Apr 28 12:56:09 PM PDT 24
Peak memory	201100 kb
Host	smart-52ba8896-63a5-475a-b01f-7e5f2cbcba6a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804921039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_tim eout.804921039
Directory	/workspace/6.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/6.clkmgr_idle_intersig_mubi.146829649
Short name	T604
Test name
Test status
Simulation time	23055860 ps
CPU time	0.85 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:06 PM PDT 24
Peak memory	200984 kb
Host	smart-21e8a03f-b5cb-45dd-8934-b1acbfc500a8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146829649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .clkmgr_idle_intersig_mubi.146829649
Directory	/workspace/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.770351148
Short name	T518
Test name
Test status
Simulation time	92896116 ps
CPU time	1.06 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	200988 kb
Host	smart-59b50e67-de0f-47ac-b6e8-0d7a92c6c19e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770351148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.clkmgr_lc_clk_byp_req_intersig_mubi.770351148
Directory	/workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.651496772
Short name	T589
Test name
Test status
Simulation time	38074350 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:06 PM PDT 24
Peak memory	200968 kb
Host	smart-68c20c99-15b3-4515-83c5-b3270792b394
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651496772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.clkmgr_lc_ctrl_intersig_mubi.651496772
Directory	/workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_peri.3481353374
Short name	T756
Test name
Test status
Simulation time	36454642 ps
CPU time	0.75 seconds
Started	Apr 28 12:56:03 PM PDT 24
Finished	Apr 28 12:56:05 PM PDT 24
Peak memory	200832 kb
Host	smart-e235fc9b-57a7-4830-80e5-a40bf97accc3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481353374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3481353374
Directory	/workspace/6.clkmgr_peri/latest

Test location	/workspace/coverage/default/6.clkmgr_regwen.383895902
Short name	T134
Test name
Test status
Simulation time	258573254 ps
CPU time	2.09 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:18 PM PDT 24
Peak memory	200944 kb
Host	smart-df0463f5-5a28-4bbd-b17b-7bb42e72d402
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383895902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.383895902
Directory	/workspace/6.clkmgr_regwen/latest

Test location	/workspace/coverage/default/6.clkmgr_smoke.3629766650
Short name	T774
Test name
Test status
Simulation time	15386146 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:06 PM PDT 24
Finished	Apr 28 12:56:08 PM PDT 24
Peak memory	201064 kb
Host	smart-105ec597-e947-49d4-8159-d4d29ebee6e4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629766650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.3629766650
Directory	/workspace/6.clkmgr_smoke/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all.2383664062
Short name	T698
Test name
Test status
Simulation time	4104314873 ps
CPU time	16.85 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:22 PM PDT 24
Peak memory	201272 kb
Host	smart-76dd88a6-c35d-45ba-9cd8-5cb387710ce8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383664062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.2383664062
Directory	/workspace/6.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.2425130892
Short name	T427
Test name
Test status
Simulation time	92797557813 ps
CPU time	622.36 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 01:06:29 PM PDT 24
Peak memory	204544 kb
Host	smart-62adf729-b686-4989-bd98-25222ee32c1f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2425130892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.2425130892
Directory	/workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.clkmgr_trans.1128388453
Short name	T818
Test name
Test status
Simulation time	122008053 ps
CPU time	1.2 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:06 PM PDT 24
Peak memory	200996 kb
Host	smart-e31c5c9a-3a83-4f7d-9277-23ac7cfadfd4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128388453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.1128388453
Directory	/workspace/6.clkmgr_trans/latest

Test location	/workspace/coverage/default/7.clkmgr_alert_test.205214010
Short name	T340
Test name
Test status
Simulation time	41411111 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:06 PM PDT 24
Finished	Apr 28 12:56:08 PM PDT 24
Peak memory	201064 kb
Host	smart-c58c48ec-2a75-4392-a4f6-0b6e027dd8ed
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205214010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmg r_alert_test.205214010
Directory	/workspace/7.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1791096742
Short name	T594
Test name
Test status
Simulation time	50314584 ps
CPU time	0.96 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	200996 kb
Host	smart-c838488f-668e-4efe-acf6-1923f857e086
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791096742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.1791096742
Directory	/workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_status.2328789845
Short name	T648
Test name
Test status
Simulation time	17780365 ps
CPU time	0.76 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	200020 kb
Host	smart-38ba1282-81a4-44c1-b6ce-8ad45686729c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328789845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2328789845
Directory	/workspace/7.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/7.clkmgr_div_intersig_mubi.570511993
Short name	T402
Test name
Test status
Simulation time	60064783 ps
CPU time	0.89 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	200980 kb
Host	smart-4f0cf5c2-41bc-488f-8d46-f024abff6e52
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570511993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .clkmgr_div_intersig_mubi.570511993
Directory	/workspace/7.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_extclk.3989015410
Short name	T237
Test name
Test status
Simulation time	13618646 ps
CPU time	0.71 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:05 PM PDT 24
Peak memory	200932 kb
Host	smart-fc30e97c-5833-4632-ab91-9bba45337384
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989015410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3989015410
Directory	/workspace/7.clkmgr_extclk/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency.219231353
Short name	T687
Test name
Test status
Simulation time	938629900 ps
CPU time	4.36 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 12:56:13 PM PDT 24
Peak memory	201052 kb
Host	smart-a06827c7-214c-4ff9-a272-5b1c5e1ba992
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219231353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.219231353
Directory	/workspace/7.clkmgr_frequency/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency_timeout.657353041
Short name	T786
Test name
Test status
Simulation time	614896533 ps
CPU time	5.03 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	201012 kb
Host	smart-f7b23436-d15d-4382-9c88-3480e99dfcc8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657353041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_tim eout.657353041
Directory	/workspace/7.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/7.clkmgr_idle_intersig_mubi.4277444046
Short name	T289
Test name
Test status
Simulation time	29986869 ps
CPU time	0.9 seconds
Started	Apr 28 12:56:06 PM PDT 24
Finished	Apr 28 12:56:08 PM PDT 24
Peak memory	200988 kb
Host	smart-b9bac2f3-1d3a-4ef7-8128-1d7b45062e1f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277444046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.4277444046
Directory	/workspace/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3060598789
Short name	T620
Test name
Test status
Simulation time	27483120 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	200996 kb
Host	smart-86a09f53-8b66-4c4e-b745-9aa0a6936dda
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060598789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_clk_byp_req_intersig_mubi.3060598789
Directory	/workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.1590194854
Short name	T573
Test name
Test status
Simulation time	21201848 ps
CPU time	0.81 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:06 PM PDT 24
Peak memory	200972 kb
Host	smart-fe3f8308-485f-4e21-8ac8-a452f427abe6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590194854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_ctrl_intersig_mubi.1590194854
Directory	/workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_peri.2840190400
Short name	T412
Test name
Test status
Simulation time	19920003 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	200996 kb
Host	smart-082e7f68-8157-4f61-b23f-6027525951f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840190400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2840190400
Directory	/workspace/7.clkmgr_peri/latest

Test location	/workspace/coverage/default/7.clkmgr_regwen.2971588308
Short name	T509
Test name
Test status
Simulation time	719488142 ps
CPU time	3.55 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	201152 kb
Host	smart-bc710e07-992d-43ae-ad56-f042a8011078
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971588308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.2971588308
Directory	/workspace/7.clkmgr_regwen/latest

Test location	/workspace/coverage/default/7.clkmgr_smoke.3373485371
Short name	T653
Test name
Test status
Simulation time	16421390 ps
CPU time	0.81 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	201068 kb
Host	smart-1b89ace4-a8f7-4e7e-a62d-8c6ff30dae12
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373485371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3373485371
Directory	/workspace/7.clkmgr_smoke/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all.3623605676
Short name	T68
Test name
Test status
Simulation time	7752054863 ps
CPU time	31 seconds
Started	Apr 28 12:56:09 PM PDT 24
Finished	Apr 28 12:56:41 PM PDT 24
Peak memory	201288 kb
Host	smart-db6d1a58-1b96-4bb7-bfb3-ccaef77738bd
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623605676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.3623605676
Directory	/workspace/7.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.3247795326
Short name	T60
Test name
Test status
Simulation time	138256156307 ps
CPU time	656.44 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 01:07:05 PM PDT 24
Peak memory	212820 kb
Host	smart-4c69b5fe-6045-4848-b15d-b865418ee6f6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3247795326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.3247795326
Directory	/workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.clkmgr_trans.1357271608
Short name	T393
Test name
Test status
Simulation time	55879531 ps
CPU time	0.97 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:16 PM PDT 24
Peak memory	200996 kb
Host	smart-17316312-1a4d-4418-a04c-747dc23e1969
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357271608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1357271608
Directory	/workspace/7.clkmgr_trans/latest

Test location	/workspace/coverage/default/8.clkmgr_alert_test.784046023
Short name	T200
Test name
Test status
Simulation time	22485754 ps
CPU time	0.74 seconds
Started	Apr 28 12:56:07 PM PDT 24
Finished	Apr 28 12:56:09 PM PDT 24
Peak memory	200960 kb
Host	smart-5beaeb9a-5983-4d8c-a0e2-f79f18521296
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784046023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg r_alert_test.784046023
Directory	/workspace/8.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.1261938417
Short name	T593
Test name
Test status
Simulation time	48886684 ps
CPU time	0.98 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	200832 kb
Host	smart-26c37dd3-28f9-4067-a4ff-d6898f351d74
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261938417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.1261938417
Directory	/workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_status.2709864932
Short name	T433
Test name
Test status
Simulation time	16839167 ps
CPU time	0.71 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	200016 kb
Host	smart-62e9d283-e4d2-4f0a-82a4-b41346d93c71
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709864932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2709864932
Directory	/workspace/8.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/8.clkmgr_div_intersig_mubi.759293553
Short name	T477
Test name
Test status
Simulation time	24146643 ps
CPU time	0.86 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	200888 kb
Host	smart-996a10b4-6380-44d9-b4ca-2c8d91a21fe4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759293553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .clkmgr_div_intersig_mubi.759293553
Directory	/workspace/8.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_extclk.3384420223
Short name	T723
Test name
Test status
Simulation time	67158293 ps
CPU time	0.93 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	201000 kb
Host	smart-c86ec16c-68e9-494a-ab81-18a464ce6fce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384420223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3384420223
Directory	/workspace/8.clkmgr_extclk/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency.3776648169
Short name	T574
Test name
Test status
Simulation time	608504529 ps
CPU time	3.09 seconds
Started	Apr 28 12:56:06 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	201004 kb
Host	smart-8c6bf7db-5259-404c-9d7e-bc5a887c8b7b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776648169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.3776648169
Directory	/workspace/8.clkmgr_frequency/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency_timeout.1243854006
Short name	T484
Test name
Test status
Simulation time	151510141 ps
CPU time	1.18 seconds
Started	Apr 28 12:56:07 PM PDT 24
Finished	Apr 28 12:56:09 PM PDT 24
Peak memory	201100 kb
Host	smart-f6edf3c8-79e7-4179-8273-6a94d99c6549
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243854006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti meout.1243854006
Directory	/workspace/8.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/8.clkmgr_idle_intersig_mubi.3370357561
Short name	T379
Test name
Test status
Simulation time	29018350 ps
CPU time	0.98 seconds
Started	Apr 28 12:56:04 PM PDT 24
Finished	Apr 28 12:56:06 PM PDT 24
Peak memory	200884 kb
Host	smart-0675a28e-adea-4286-aa67-0151aa3fe08d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370357561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.3370357561
Directory	/workspace/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1865402683
Short name	T709
Test name
Test status
Simulation time	196004483 ps
CPU time	1.35 seconds
Started	Apr 28 12:56:11 PM PDT 24
Finished	Apr 28 12:56:14 PM PDT 24
Peak memory	200952 kb
Host	smart-130ad131-6a67-4da2-9a40-730ab68b1e4e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865402683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_clk_byp_req_intersig_mubi.1865402683
Directory	/workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3761903022
Short name	T187
Test name
Test status
Simulation time	27991263 ps
CPU time	0.79 seconds
Started	Apr 28 12:56:10 PM PDT 24
Finished	Apr 28 12:56:12 PM PDT 24
Peak memory	200880 kb
Host	smart-6894bc73-888a-48c5-b352-7fe611b1a6f1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761903022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_ctrl_intersig_mubi.3761903022
Directory	/workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_peri.171703439
Short name	T802
Test name
Test status
Simulation time	16373740 ps
CPU time	0.77 seconds
Started	Apr 28 12:56:05 PM PDT 24
Finished	Apr 28 12:56:07 PM PDT 24
Peak memory	200860 kb
Host	smart-25c7d07a-2e84-4c0a-aaa0-cb29d449c03f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171703439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.171703439
Directory	/workspace/8.clkmgr_peri/latest

Test location	/workspace/coverage/default/8.clkmgr_regwen.4181336012
Short name	T548
Test name
Test status
Simulation time	1875182772 ps
CPU time	6.15 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:21 PM PDT 24
Peak memory	201036 kb
Host	smart-7e4abd11-9ae7-4243-8dd7-7fe2a991f739
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181336012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.4181336012
Directory	/workspace/8.clkmgr_regwen/latest

Test location	/workspace/coverage/default/8.clkmgr_smoke.2763638985
Short name	T193
Test name
Test status
Simulation time	22172217 ps
CPU time	0.82 seconds
Started	Apr 28 12:56:10 PM PDT 24
Finished	Apr 28 12:56:12 PM PDT 24
Peak memory	201084 kb
Host	smart-2ed3ab14-d1d0-4d11-afa1-a4beb9abad1c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763638985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2763638985
Directory	/workspace/8.clkmgr_smoke/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all.3915354461
Short name	T600
Test name
Test status
Simulation time	6606048987 ps
CPU time	21.83 seconds
Started	Apr 28 12:56:10 PM PDT 24
Finished	Apr 28 12:56:33 PM PDT 24
Peak memory	201304 kb
Host	smart-692cf9a8-30af-40a3-93f0-4c07d3e7b639
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915354461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.3915354461
Directory	/workspace/8.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.4108375580
Short name	T135
Test name
Test status
Simulation time	88565607958 ps
CPU time	316.77 seconds
Started	Apr 28 12:56:10 PM PDT 24
Finished	Apr 28 01:01:28 PM PDT 24
Peak memory	209672 kb
Host	smart-1459dcdd-1180-4d6b-8e0c-bea907a7f591
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4108375580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.4108375580
Directory	/workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.clkmgr_trans.3715619878
Short name	T326
Test name
Test status
Simulation time	201343838 ps
CPU time	1.32 seconds
Started	Apr 28 12:56:03 PM PDT 24
Finished	Apr 28 12:56:05 PM PDT 24
Peak memory	200892 kb
Host	smart-8b0192aa-b0a3-46c9-bc6a-c4634d5b0575
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715619878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3715619878
Directory	/workspace/8.clkmgr_trans/latest

Test location	/workspace/coverage/default/9.clkmgr_alert_test.1471378489
Short name	T305
Test name
Test status
Simulation time	18348592 ps
CPU time	0.78 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:14 PM PDT 24
Peak memory	200952 kb
Host	smart-0783c14c-e3d8-4189-85ab-9ba505a038ea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471378489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm gr_alert_test.1471378489
Directory	/workspace/9.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.2769002185
Short name	T447
Test name
Test status
Simulation time	73996876 ps
CPU time	0.97 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	201000 kb
Host	smart-17ff86b3-276d-448d-a4c4-7d8d9f59d64f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769002185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.2769002185
Directory	/workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_status.3216466630
Short name	T500
Test name
Test status
Simulation time	49674675 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:09 PM PDT 24
Finished	Apr 28 12:56:11 PM PDT 24
Peak memory	199980 kb
Host	smart-6c471e12-64bd-481e-861a-8e2d45c1ad17
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216466630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.3216466630
Directory	/workspace/9.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/9.clkmgr_div_intersig_mubi.3472167154
Short name	T553
Test name
Test status
Simulation time	23857556 ps
CPU time	0.87 seconds
Started	Apr 28 12:56:11 PM PDT 24
Finished	Apr 28 12:56:12 PM PDT 24
Peak memory	200900 kb
Host	smart-e2e3fed3-7442-48e7-8a94-84753bdf7dbf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472167154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.3472167154
Directory	/workspace/9.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_extclk.1581017729
Short name	T502
Test name
Test status
Simulation time	36803229 ps
CPU time	0.88 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:15 PM PDT 24
Peak memory	200872 kb
Host	smart-4d977eb2-8db7-4e2e-970c-f1e982cc3f52
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581017729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1581017729
Directory	/workspace/9.clkmgr_extclk/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency.682796346
Short name	T729
Test name
Test status
Simulation time	1317315518 ps
CPU time	5.04 seconds
Started	Apr 28 12:56:11 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	200960 kb
Host	smart-2ee77e57-508d-47a0-af53-8df30c6ec860
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682796346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.682796346
Directory	/workspace/9.clkmgr_frequency/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency_timeout.3175041079
Short name	T646
Test name
Test status
Simulation time	1778570162 ps
CPU time	7.23 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:22 PM PDT 24
Peak memory	201128 kb
Host	smart-31c8d5b3-f8f3-4aa1-873e-39f22d294afe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175041079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti meout.3175041079
Directory	/workspace/9.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/9.clkmgr_idle_intersig_mubi.2953318747
Short name	T682
Test name
Test status
Simulation time	77568009 ps
CPU time	0.94 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:15 PM PDT 24
Peak memory	200868 kb
Host	smart-dab82d2f-92e6-44b0-a95a-9bb305c92a3c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953318747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.2953318747
Directory	/workspace/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.395718037
Short name	T519
Test name
Test status
Simulation time	33767754 ps
CPU time	0.86 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 12:56:10 PM PDT 24
Peak memory	201012 kb
Host	smart-e74837fc-529b-4354-98d9-8c561247a1e4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395718037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.clkmgr_lc_clk_byp_req_intersig_mubi.395718037
Directory	/workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3450490286
Short name	T191
Test name
Test status
Simulation time	27375984 ps
CPU time	0.8 seconds
Started	Apr 28 12:56:12 PM PDT 24
Finished	Apr 28 12:56:14 PM PDT 24
Peak memory	200904 kb
Host	smart-35e208d8-9671-4370-b865-4059908df74c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450490286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_ctrl_intersig_mubi.3450490286
Directory	/workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_peri.1181272415
Short name	T552
Test name
Test status
Simulation time	28079567 ps
CPU time	0.81 seconds
Started	Apr 28 12:56:10 PM PDT 24
Finished	Apr 28 12:56:12 PM PDT 24
Peak memory	201000 kb
Host	smart-76717424-c03d-4397-a363-ce414d7df5de
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181272415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.1181272415
Directory	/workspace/9.clkmgr_peri/latest

Test location	/workspace/coverage/default/9.clkmgr_regwen.149186694
Short name	T336
Test name
Test status
Simulation time	1497157950 ps
CPU time	5.49 seconds
Started	Apr 28 12:56:10 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	201140 kb
Host	smart-4c724eef-790b-4ab3-b793-ac416ac5014a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149186694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.149186694
Directory	/workspace/9.clkmgr_regwen/latest

Test location	/workspace/coverage/default/9.clkmgr_smoke.1195040175
Short name	T429
Test name
Test status
Simulation time	32029727 ps
CPU time	0.89 seconds
Started	Apr 28 12:56:15 PM PDT 24
Finished	Apr 28 12:56:17 PM PDT 24
Peak memory	201060 kb
Host	smart-14a1a77b-4483-4986-8b13-313734998275
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195040175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1195040175
Directory	/workspace/9.clkmgr_smoke/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all.2381180718
Short name	T125
Test name
Test status
Simulation time	4286491914 ps
CPU time	16.41 seconds
Started	Apr 28 12:56:08 PM PDT 24
Finished	Apr 28 12:56:25 PM PDT 24
Peak memory	201356 kb
Host	smart-8d5a329c-06b0-4078-bc06-fda171cf073a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381180718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.2381180718
Directory	/workspace/9.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.3099767911
Short name	T732
Test name
Test status
Simulation time	14477848557 ps
CPU time	268.84 seconds
Started	Apr 28 12:56:14 PM PDT 24
Finished	Apr 28 01:00:45 PM PDT 24
Peak memory	209712 kb
Host	smart-89977923-bc01-4ec7-9cdb-250c4d6456e7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3099767911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3099767911
Directory	/workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/9.clkmgr_trans.3459590390
Short name	T668
Test name
Test status
Simulation time	37867622 ps
CPU time	1.01 seconds
Started	Apr 28 12:56:13 PM PDT 24
Finished	Apr 28 12:56:15 PM PDT 24
Peak memory	200884 kb
Host	smart-c4963792-0cf1-4091-9412-e04b2d4ee748
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459590390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3459590390
Directory	/workspace/9.clkmgr_trans/latest

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