Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	640183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3659680

1

T1

195

T6

12

T2

157677

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1055378	1			T1	30		T6	13		T2	42556
values[0x0]	1491336	1			T1	190		T6	12		T2	61836
values[0x1]	1753149	1			T1	190		T6	15		T2	73396

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	353678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3946185

1

T1

257

T6

15

T2

168379

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17165	1			T2	717		T19	1		T3	436
valid_sources[0x01]	17442	1			T2	721		T3	464		T67	1
valid_sources[0x02]	15119	1			T1	8		T2	684		T3	505
valid_sources[0x03]	17480	1			T2	678		T3	478		T10	407
valid_sources[0x04]	17143	1			T2	687		T3	490		T10	421
valid_sources[0x05]	17255	1			T2	695		T66	1		T3	497
valid_sources[0x06]	17892	1			T2	739		T19	1		T4	2
valid_sources[0x07]	16239	1			T1	2		T2	679		T66	2
valid_sources[0x08]	17088	1			T1	6		T2	669		T4	3
valid_sources[0x09]	16372	1			T2	739		T39	1		T4	2
valid_sources[0x0a]	18333	1			T2	732		T39	1		T66	1
valid_sources[0x0b]	15569	1			T2	682		T3	499		T10	419
valid_sources[0x0c]	16825	1			T2	662		T20	2		T39	1
valid_sources[0x0d]	15658	1			T2	657		T3	457		T10	382
valid_sources[0x0e]	17152	1			T2	712		T4	1		T3	490
valid_sources[0x0f]	16424	1			T2	682		T3	438		T41	1
valid_sources[0x10]	17589	1			T1	2		T2	705		T23	11
valid_sources[0x11]	15832	1			T2	696		T23	6		T3	459
valid_sources[0x12]	17412	1			T2	650		T4	7		T3	477
valid_sources[0x13]	16894	1			T1	1		T2	641		T3	498
valid_sources[0x14]	16823	1			T2	674		T4	4		T3	497
valid_sources[0x15]	17756	1			T2	851		T4	11		T3	500
valid_sources[0x16]	18523	1			T2	698		T20	1		T21	1
valid_sources[0x17]	15961	1			T1	2		T2	680		T19	1
valid_sources[0x18]	15946	1			T2	740		T66	1		T102	2
valid_sources[0x19]	15234	1			T1	7		T2	683		T4	2
valid_sources[0x1a]	16616	1			T2	654		T4	5		T175	1
valid_sources[0x1b]	15700	1			T2	678		T3	475		T41	1
valid_sources[0x1c]	16357	1			T2	654		T3	496		T10	417
valid_sources[0x1d]	17799	1			T2	670		T3	506		T10	382
valid_sources[0x1e]	17098	1			T1	3		T2	656		T61	7
valid_sources[0x1f]	16126	1			T2	616		T141	2		T3	494
valid_sources[0x20]	16039	1			T2	588		T4	3		T3	485
valid_sources[0x21]	16506	1			T2	682		T3	456		T10	396
valid_sources[0x22]	17144	1			T1	2		T2	679		T20	3
valid_sources[0x23]	17396	1			T2	692		T4	1		T23	12
valid_sources[0x24]	17284	1			T2	703		T4	3		T3	486
valid_sources[0x25]	16189	1			T2	686		T66	1		T175	11
valid_sources[0x26]	16397	1			T1	21		T2	781		T61	1
valid_sources[0x27]	16135	1			T1	1		T2	724		T4	3
valid_sources[0x28]	17052	1			T1	1		T2	756		T3	464
valid_sources[0x29]	15387	1			T2	684		T21	1		T4	3
valid_sources[0x2a]	16245	1			T2	625		T4	4		T3	483
valid_sources[0x2b]	17172	1			T2	721		T39	1		T3	489
valid_sources[0x2c]	15669	1			T2	707		T22	34		T66	1
valid_sources[0x2d]	16761	1			T1	34		T2	718		T4	1
valid_sources[0x2e]	17133	1			T1	5		T2	720		T39	1
valid_sources[0x2f]	15731	1			T1	1		T2	674		T21	2
valid_sources[0x30]	16887	1			T2	709		T19	3		T3	455
valid_sources[0x31]	16192	1			T2	736		T4	1		T141	1
valid_sources[0x32]	16239	1			T2	651		T19	1		T3	444
valid_sources[0x33]	18085	1			T2	733		T66	1		T3	467
valid_sources[0x34]	17444	1			T2	646		T102	4		T3	453
valid_sources[0x35]	17899	1			T1	11		T2	657		T4	4
valid_sources[0x36]	16809	1			T2	712		T20	1		T4	2
valid_sources[0x37]	17065	1			T2	679		T39	1		T4	7
valid_sources[0x38]	17668	1			T2	719		T21	1		T4	5
valid_sources[0x39]	17068	1			T1	24		T2	675		T3	486
valid_sources[0x3a]	17470	1			T2	685		T3	501		T41	1
valid_sources[0x3b]	16580	1			T2	675		T3	480		T10	381
valid_sources[0x3c]	18426	1			T2	696		T4	3		T3	512
valid_sources[0x3d]	18162	1			T1	7		T2	696		T3	462
valid_sources[0x3e]	15610	1			T2	663		T39	1		T4	1
valid_sources[0x3f]	17521	1			T2	659		T39	1		T4	2
valid_sources[0x40]	16756	1			T2	708		T3	512		T10	396
valid_sources[0x41]	16635	1			T2	738		T3	464		T10	419
valid_sources[0x42]	16194	1			T2	782		T39	1		T4	8
valid_sources[0x43]	15532	1			T2	675		T39	1		T3	463
valid_sources[0x44]	14447	1			T2	694		T4	8		T3	477
valid_sources[0x45]	16385	1			T2	762		T4	3		T3	478
valid_sources[0x46]	15626	1			T1	3		T2	720		T4	2
valid_sources[0x47]	17280	1			T2	759		T39	1		T3	473
valid_sources[0x48]	16456	1			T1	5		T2	683		T4	4
valid_sources[0x49]	16318	1			T2	746		T66	1		T3	465
valid_sources[0x4a]	16908	1			T1	6		T2	754		T4	4
valid_sources[0x4b]	15901	1			T2	699		T3	490		T41	1
valid_sources[0x4c]	19290	1			T2	792		T4	1		T66	1
valid_sources[0x4d]	17232	1			T2	719		T4	1		T3	463
valid_sources[0x4e]	16956	1			T1	9		T2	715		T3	483
valid_sources[0x4f]	17429	1			T2	722		T4	4		T141	1
valid_sources[0x50]	16489	1			T2	717		T4	1		T3	471
valid_sources[0x51]	16026	1			T1	2		T2	655		T39	3
valid_sources[0x52]	17799	1			T2	630		T3	509		T10	328
valid_sources[0x53]	17279	1			T2	633		T84	11		T3	432
valid_sources[0x54]	18412	1			T2	700		T3	490		T10	383
valid_sources[0x55]	17817	1			T2	740		T4	3		T3	391
valid_sources[0x56]	17430	1			T2	675		T39	2		T3	503
valid_sources[0x57]	18202	1			T2	654		T19	1		T3	470
valid_sources[0x58]	16163	1			T2	643		T61	2		T3	484
valid_sources[0x59]	16500	1			T2	687		T4	3		T3	448
valid_sources[0x5a]	16836	1			T2	677		T27	21		T3	480
valid_sources[0x5b]	15201	1			T2	670		T21	1		T4	1
valid_sources[0x5c]	16116	1			T2	695		T4	9		T66	2
valid_sources[0x5d]	17313	1			T2	674		T39	1		T37	45
valid_sources[0x5e]	16307	1			T2	654		T19	1		T20	2
valid_sources[0x5f]	17981	1			T2	718		T4	5		T3	508
valid_sources[0x60]	17108	1			T2	674		T66	2		T3	484
valid_sources[0x61]	16472	1			T1	12		T2	698		T61	7
valid_sources[0x62]	17394	1			T2	648		T4	5		T66	1
valid_sources[0x63]	15282	1			T2	728		T4	1		T3	517
valid_sources[0x64]	16145	1			T1	9		T2	663		T4	6
valid_sources[0x65]	16325	1			T2	627		T4	5		T3	502
valid_sources[0x66]	16206	1			T2	676		T4	1		T3	474
valid_sources[0x67]	15309	1			T1	21		T2	689		T4	4
valid_sources[0x68]	17143	1			T1	5		T2	670		T3	478
valid_sources[0x69]	14774	1			T2	683		T61	3		T39	1
valid_sources[0x6a]	17391	1			T2	644		T4	3		T84	5
valid_sources[0x6b]	16639	1			T1	7		T2	743		T39	1
valid_sources[0x6c]	16490	1			T2	717		T66	1		T3	497
valid_sources[0x6d]	15287	1			T2	743		T66	2		T3	481
valid_sources[0x6e]	17853	1			T1	7		T2	706		T4	2
valid_sources[0x6f]	15892	1			T2	672		T4	8		T27	6
valid_sources[0x70]	17966	1			T2	692		T19	1		T61	1
valid_sources[0x71]	17577	1			T2	702		T39	2		T3	475
valid_sources[0x72]	16478	1			T2	648		T4	3		T3	460
valid_sources[0x73]	16741	1			T1	3		T2	731		T3	510
valid_sources[0x74]	18157	1			T2	631		T4	7		T3	501
valid_sources[0x75]	16710	1			T2	666		T39	1		T3	449
valid_sources[0x76]	16730	1			T2	661		T61	1		T141	4
valid_sources[0x77]	17023	1			T2	703		T4	13		T3	493
valid_sources[0x78]	16516	1			T2	607		T4	2		T36	1
valid_sources[0x79]	16844	1			T2	682		T4	4		T27	2
valid_sources[0x7a]	17229	1			T2	662		T39	1		T3	495
valid_sources[0x7b]	16619	1			T2	768		T20	1		T39	2
valid_sources[0x7c]	16120	1			T2	747		T66	1		T3	434
valid_sources[0x7d]	15732	1			T2	723		T4	1		T3	489
valid_sources[0x7e]	18273	1			T1	5		T2	750		T18	11
valid_sources[0x7f]	15764	1			T2	665		T39	2		T3	486
valid_sources[0x80]	16577	1			T1	4		T2	802		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

922736

1

T1

16

T6

7

T2

39335

values[0x0]

all_enables

biggest_size

1392670

1

T1

107

T6

2

T2

59710

values[0x1]

all_enables

biggest_size

1344274

1

T1

72

T6

3

T2

58632