Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	666616	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3908047

1

T7

45

T9

18

T27

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1123311	1			T7	68		T9	14		T27	7
values[0x0]	1587674	1			T7	27		T9	14		T27	4
values[0x1]	1863678	1			T7	24		T9	15		T27	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	366347	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4208316

1

T7

55

T9

22

T27

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18746	1			T1	448		T5	4		T2	223
valid_sources[0x01]	17052	1			T7	1		T1	464		T5	3
valid_sources[0x02]	17295	1			T7	1		T27	1		T1	444
valid_sources[0x03]	18643	1			T1	464		T2	529		T103	1
valid_sources[0x04]	17853	1			T7	2		T1	387		T5	2
valid_sources[0x05]	18937	1			T7	1		T1	385		T5	1
valid_sources[0x06]	17017	1			T4	4		T1	427		T2	197
valid_sources[0x07]	17863	1			T7	1		T1	492		T2	372
valid_sources[0x08]	17990	1			T7	2		T1	461		T2	318
valid_sources[0x09]	18963	1			T4	4		T1	439		T5	3
valid_sources[0x0a]	16452	1			T1	473		T20	1		T5	1
valid_sources[0x0b]	16837	1			T1	416		T2	184		T69	1
valid_sources[0x0c]	18041	1			T7	1		T1	472		T5	1
valid_sources[0x0d]	17982	1			T7	3		T9	1		T1	463
valid_sources[0x0e]	17508	1			T4	2		T1	470		T19	1
valid_sources[0x0f]	17713	1			T1	377		T19	1		T2	78
valid_sources[0x10]	17306	1			T7	1		T4	8		T1	447
valid_sources[0x11]	17552	1			T7	1		T1	415		T2	240
valid_sources[0x12]	18650	1			T7	1		T4	8		T1	466
valid_sources[0x13]	16549	1			T7	1		T9	1		T1	440
valid_sources[0x14]	17933	1			T7	1		T1	379		T20	3
valid_sources[0x15]	17321	1			T7	2		T1	439		T24	1
valid_sources[0x16]	20942	1			T1	422		T19	1		T5	1
valid_sources[0x17]	18262	1			T1	398		T2	217		T36	4
valid_sources[0x18]	16723	1			T9	1		T1	450		T19	3
valid_sources[0x19]	19187	1			T4	14		T1	445		T2	160
valid_sources[0x1a]	17858	1			T7	1		T1	503		T24	2
valid_sources[0x1b]	17685	1			T7	1		T1	384		T2	370
valid_sources[0x1c]	19105	1			T27	5		T1	465		T20	3
valid_sources[0x1d]	17716	1			T4	4		T1	452		T20	5
valid_sources[0x1e]	20019	1			T1	500		T19	1		T2	306
valid_sources[0x1f]	16856	1			T7	1		T1	442		T19	1
valid_sources[0x20]	17822	1			T1	389		T19	1		T2	333
valid_sources[0x21]	18854	1			T7	1		T4	4		T1	397
valid_sources[0x22]	18267	1			T1	448		T2	332		T69	1
valid_sources[0x23]	18882	1			T1	457		T2	397		T112	2
valid_sources[0x24]	16324	1			T4	7		T1	390		T2	455
valid_sources[0x25]	18870	1			T1	406		T19	5		T5	1
valid_sources[0x26]	17428	1			T27	2		T1	393		T19	2
valid_sources[0x27]	16874	1			T7	1		T9	1		T1	435
valid_sources[0x28]	16227	1			T7	1		T1	348		T2	295
valid_sources[0x29]	17029	1			T1	451		T5	4		T24	2
valid_sources[0x2a]	17509	1			T30	42		T4	6		T1	477
valid_sources[0x2b]	18831	1			T27	1		T1	391		T20	2
valid_sources[0x2c]	17797	1			T7	1		T9	1		T1	396
valid_sources[0x2d]	16352	1			T1	388		T5	1		T2	598
valid_sources[0x2e]	17132	1			T29	1		T1	426		T5	3
valid_sources[0x2f]	16983	1			T7	1		T1	425		T2	145
valid_sources[0x30]	17914	1			T1	418		T2	247		T69	1
valid_sources[0x31]	16533	1			T7	1		T9	1		T1	487
valid_sources[0x32]	17212	1			T9	1		T29	1		T1	467
valid_sources[0x33]	16730	1			T7	1		T1	406		T20	2
valid_sources[0x34]	18467	1			T1	470		T2	251		T69	1
valid_sources[0x35]	16913	1			T7	1		T1	440		T2	395
valid_sources[0x36]	18898	1			T1	389		T5	2		T2	271
valid_sources[0x37]	17766	1			T9	3		T4	3		T1	391
valid_sources[0x38]	18859	1			T1	413		T5	1		T2	518
valid_sources[0x39]	17333	1			T7	2		T1	389		T5	4
valid_sources[0x3a]	17677	1			T27	2		T1	449		T5	7
valid_sources[0x3b]	16755	1			T1	426		T6	140		T2	541
valid_sources[0x3c]	19071	1			T7	1		T29	2		T1	357
valid_sources[0x3d]	17748	1			T1	438		T2	102		T103	1
valid_sources[0x3e]	17956	1			T1	475		T5	1		T2	148
valid_sources[0x3f]	18828	1			T1	406		T24	2		T2	358
valid_sources[0x40]	16779	1			T1	417		T2	429		T103	1
valid_sources[0x41]	17151	1			T7	1		T1	426		T5	3
valid_sources[0x42]	16899	1			T1	383		T19	1		T5	4
valid_sources[0x43]	19671	1			T1	454		T5	3		T2	510
valid_sources[0x44]	18008	1			T1	426		T19	4		T2	355
valid_sources[0x45]	16687	1			T1	436		T2	212		T103	1
valid_sources[0x46]	17839	1			T7	2		T1	486		T5	2
valid_sources[0x47]	16165	1			T7	1		T1	443		T19	1
valid_sources[0x48]	17485	1			T28	3		T1	442		T2	216
valid_sources[0x49]	18374	1			T1	464		T2	138		T109	1
valid_sources[0x4a]	18012	1			T1	448		T2	230		T69	1
valid_sources[0x4b]	15465	1			T4	1		T1	486		T2	315
valid_sources[0x4c]	16227	1			T7	2		T1	475		T19	2
valid_sources[0x4d]	17867	1			T1	500		T19	2		T5	3
valid_sources[0x4e]	16856	1			T7	1		T1	405		T2	393
valid_sources[0x4f]	16522	1			T1	383		T2	170		T112	2
valid_sources[0x50]	21227	1			T7	1		T1	468		T20	1
valid_sources[0x51]	17386	1			T7	1		T1	436		T2	654
valid_sources[0x52]	19303	1			T1	454		T2	251		T108	1
valid_sources[0x53]	18353	1			T1	422		T19	1		T5	1
valid_sources[0x54]	17237	1			T29	1		T4	2		T1	440
valid_sources[0x55]	17470	1			T9	1		T29	1		T1	433
valid_sources[0x56]	18720	1			T7	1		T1	401		T5	1
valid_sources[0x57]	17653	1			T1	430		T2	463		T69	1
valid_sources[0x58]	16202	1			T7	1		T1	442		T5	2
valid_sources[0x59]	17976	1			T1	465		T2	305		T69	1
valid_sources[0x5a]	16747	1			T7	1		T1	348		T5	2
valid_sources[0x5b]	17687	1			T7	1		T27	1		T1	483
valid_sources[0x5c]	16378	1			T7	1		T1	503		T19	1
valid_sources[0x5d]	18154	1			T1	522		T21	1		T2	106
valid_sources[0x5e]	19313	1			T1	434		T20	4		T2	310
valid_sources[0x5f]	18060	1			T1	449		T5	1		T2	182
valid_sources[0x60]	17243	1			T1	498		T20	2		T2	263
valid_sources[0x61]	17845	1			T7	1		T1	466		T5	1
valid_sources[0x62]	16677	1			T9	1		T1	440		T21	1
valid_sources[0x63]	17243	1			T29	1		T1	407		T5	3
valid_sources[0x64]	18519	1			T1	427		T20	1		T5	1
valid_sources[0x65]	17251	1			T1	467		T2	161		T140	3
valid_sources[0x66]	18841	1			T1	434		T5	2		T2	179
valid_sources[0x67]	18339	1			T7	1		T1	456		T19	1
valid_sources[0x68]	18217	1			T27	2		T29	1		T1	391
valid_sources[0x69]	17043	1			T1	410		T19	2		T2	208
valid_sources[0x6a]	17231	1			T7	1		T29	1		T1	462
valid_sources[0x6b]	18956	1			T7	2		T1	417		T5	1
valid_sources[0x6c]	19441	1			T7	1		T1	448		T5	1
valid_sources[0x6d]	17823	1			T1	420		T19	1		T5	1
valid_sources[0x6e]	16104	1			T1	413		T20	5		T2	320
valid_sources[0x6f]	16639	1			T1	366		T2	197		T140	1
valid_sources[0x70]	17476	1			T1	483		T19	3		T5	1
valid_sources[0x71]	17158	1			T27	2		T1	472		T24	1
valid_sources[0x72]	18246	1			T1	485		T5	2		T24	2
valid_sources[0x73]	18927	1			T1	404		T19	1		T2	261
valid_sources[0x74]	17234	1			T1	460		T19	1		T2	401
valid_sources[0x75]	18163	1			T1	412		T5	1		T2	270
valid_sources[0x76]	17350	1			T1	446		T2	469		T108	1
valid_sources[0x77]	19643	1			T29	1		T1	474		T2	81
valid_sources[0x78]	21001	1			T1	463		T66	2		T2	269
valid_sources[0x79]	18373	1			T9	3		T1	416		T20	4
valid_sources[0x7a]	16405	1			T7	1		T1	457		T19	1
valid_sources[0x7b]	16955	1			T1	419		T20	2		T24	1
valid_sources[0x7c]	16479	1			T1	404		T2	250		T103	3
valid_sources[0x7d]	17579	1			T7	1		T9	1		T1	432
valid_sources[0x7e]	17715	1			T9	1		T1	426		T19	2
valid_sources[0x7f]	18143	1			T7	1		T9	1		T1	447
valid_sources[0x80]	17079	1			T1	428		T5	1		T2	80

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

985939

1

T7

32

T9

8

T27

4

values[0x0]

all_enables

biggest_size

1487036

1

T7

8

T9

9

T27

1

values[0x1]

all_enables

biggest_size

1435072

1

T7

5

T9

1

T27

1