Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T29
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T1
1	0	Covered	T8,T26,T41
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1272032706	15161	0	0
GateOpen_A	1272032706	21673	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272032706	15161	0	0
T1	1335732	266	0	0
T2	0	203	0	0
T4	50191	0	0	0
T8	11272	17	0	0
T9	10064	0	0	0
T12	0	50	0	0
T19	7019	0	0	0
T20	0	1	0	0
T26	3050	11	0	0
T27	13308	0	0	0
T28	3534	0	0	0
T29	4964	7	0	0
T30	40569	0	0	0
T40	0	4	0	0
T41	0	1	0	0
T67	0	4	0	0
T111	0	4	0	0
T133	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1272032706	21673	0	0
T1	1335732	286	0	0
T4	50191	20	0	0
T5	0	24	0	0
T8	11272	21	0	0
T9	10064	0	0	0
T19	7019	4	0	0
T20	0	1	0	0
T23	0	3	0	0
T26	3050	15	0	0
T27	13308	0	0	0
T28	3534	4	0	0
T29	4964	11	0	0
T30	40569	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T29
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T1
1	0	Covered	T8,T26,T40
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	140507835	3610	0	0
GateOpen_A	140507835	5236	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507835	3610	0	0
T1	734740	61	0	0
T2	0	52	0	0
T4	4210	0	0	0
T8	1211	4	0	0
T9	1170	0	0	0
T12	0	23	0	0
T19	767	0	0	0
T26	338	3	0	0
T27	1516	0	0	0
T28	375	0	0	0
T29	548	2	0	0
T30	4504	0	0	0
T40	0	1	0	0
T67	0	1	0	0
T111	0	1	0	0
T133	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507835	5236	0	0
T1	734740	66	0	0
T4	4210	5	0	0
T5	0	6	0	0
T8	1211	5	0	0
T9	1170	0	0	0
T19	767	1	0	0
T23	0	1	0	0
T26	338	4	0	0
T27	1516	0	0	0
T28	375	1	0	0
T29	548	3	0	0
T30	4504	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T29
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T1
1	0	Covered	T8,T26,T40
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	281016631	3865	0	0
GateOpen_A	281016631	5491	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281016631	3865	0	0
T1	146950	68	0	0
T2	0	55	0	0
T4	8417	0	0	0
T8	2422	4	0	0
T9	2343	0	0	0
T12	0	27	0	0
T19	1533	0	0	0
T26	675	3	0	0
T27	3034	0	0	0
T28	749	0	0	0
T29	1095	2	0	0
T30	9007	0	0	0
T40	0	1	0	0
T67	0	1	0	0
T111	0	1	0	0
T133	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281016631	5491	0	0
T1	146950	73	0	0
T4	8417	5	0	0
T5	0	6	0	0
T8	2422	5	0	0
T9	2343	0	0	0
T19	1533	1	0	0
T23	0	1	0	0
T26	675	4	0	0
T27	3034	0	0	0
T28	749	1	0	0
T29	1095	3	0	0
T30	9007	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T29
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T1
1	0	Covered	T8,T26,T40
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	563294411	3857	0	0
GateOpen_A	563294411	5488	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563294411	3857	0	0
T1	295010	72	0	0
T2	0	49	0	0
T4	25042	0	0	0
T8	4935	4	0	0
T9	4367	0	0	0
T19	3146	0	0	0
T20	0	1	0	0
T26	1374	3	0	0
T27	5839	0	0	0
T28	1607	0	0	0
T29	2214	1	0	0
T30	18038	0	0	0
T40	0	1	0	0
T67	0	1	0	0
T111	0	1	0	0
T133	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563294411	5488	0	0
T1	295010	77	0	0
T4	25042	5	0	0
T5	0	6	0	0
T8	4935	5	0	0
T9	4367	0	0	0
T19	3146	1	0	0
T20	0	1	0	0
T26	1374	4	0	0
T27	5839	0	0	0
T28	1607	1	0	0
T29	2214	2	0	0
T30	18038	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T29
0	1	Covered	T29,T1,T2
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T4,T1
1	0	Covered	T8,T26,T41
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	287213829	3829	0	0
GateOpen_A	287213829	5458	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	287213829	3829	0	0
T1	159032	65	0	0
T2	0	47	0	0
T4	12522	0	0	0
T8	2704	5	0	0
T9	2184	0	0	0
T19	1573	0	0	0
T26	663	2	0	0
T27	2919	0	0	0
T28	803	0	0	0
T29	1107	2	0	0
T30	9020	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T67	0	1	0	0
T111	0	1	0	0
T133	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	287213829	5458	0	0
T1	159032	70	0	0
T4	12522	5	0	0
T5	0	6	0	0
T8	2704	6	0	0
T9	2184	0	0	0
T19	1573	1	0	0
T23	0	1	0	0
T26	663	3	0	0
T27	2919	0	0	0
T28	803	1	0	0
T29	1107	3	0	0
T30	9020	1	0	0