Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	882858130	83779	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	882858130	83779	0	0
T1	1694005	911	0	0
T2	0	1263	0	0
T3	0	267	0	0
T5	137895	0	0	0
T6	168970	0	0	0
T12	0	517	0	0
T13	0	1682	0	0
T14	0	292	0	0
T15	0	464	0	0
T16	0	61	0	0
T17	0	329	0	0
T18	0	982	0	0
T19	16220	0	0	0
T20	8785	0	0	0
T21	5100	0	0	0
T22	5920	0	0	0
T23	5270	0	0	0
T24	9205	0	0	0
T25	13735	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	176571626	12448	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	12448	0	0
T1	338801	118	0	0
T2	0	182	0	0
T3	0	35	0	0
T5	27579	0	0	0
T6	33794	0	0	0
T12	0	76	0	0
T13	0	240	0	0
T14	0	57	0	0
T15	0	75	0	0
T16	0	9	0	0
T17	0	48	0	0
T18	0	185	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T25	2747	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	176571626	16807	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	16807	0	0
T1	338801	186	0	0
T2	0	249	0	0
T3	0	56	0	0
T5	27579	0	0	0
T6	33794	0	0	0
T12	0	103	0	0
T13	0	337	0	0
T14	0	57	0	0
T15	0	95	0	0
T16	0	12	0	0
T17	0	67	0	0
T18	0	186	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T25	2747	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	176571626	25495	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	25495	0	0
T1	338801	306	0	0
T2	0	400	0	0
T3	0	89	0	0
T5	27579	0	0	0
T6	33794	0	0	0
T12	0	170	0	0
T13	0	532	0	0
T14	0	64	0	0
T15	0	126	0	0
T16	0	19	0	0
T17	0	100	0	0
T18	0	236	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T25	2747	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	176571626	12182	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	12182	0	0
T1	338801	116	0	0
T2	0	177	0	0
T3	0	34	0	0
T5	27579	0	0	0
T6	33794	0	0	0
T12	0	65	0	0
T13	0	235	0	0
T14	0	57	0	0
T15	0	74	0	0
T16	0	9	0	0
T17	0	46	0	0
T18	0	185	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T25	2747	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	176571626	16847	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	16847	0	0
T1	338801	185	0	0
T2	0	255	0	0
T3	0	53	0	0
T5	27579	0	0	0
T6	33794	0	0	0
T12	0	103	0	0
T13	0	338	0	0
T14	0	57	0	0
T15	0	94	0	0
T16	0	12	0	0
T17	0	68	0	0
T18	0	190	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T25	2747	0	0	0