Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T8 |
28 |
28 |
0 |
0 |
T9 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
T28 |
28 |
28 |
0 |
0 |
T29 |
28 |
28 |
0 |
0 |
T30 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
9420564 |
9341615 |
0 |
0 |
T4 |
485313 |
102275 |
0 |
0 |
T7 |
198231 |
196787 |
0 |
0 |
T8 |
85074 |
83358 |
0 |
0 |
T9 |
87198 |
83353 |
0 |
0 |
T26 |
38132 |
36169 |
0 |
0 |
T27 |
95138 |
91846 |
0 |
0 |
T28 |
42679 |
36315 |
0 |
0 |
T29 |
44067 |
42679 |
0 |
0 |
T30 |
246113 |
245374 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1059429756 |
1044907416 |
0 |
14490 |
T1 |
2032806 |
2013198 |
0 |
18 |
T4 |
75132 |
8520 |
0 |
18 |
T7 |
18438 |
18258 |
0 |
18 |
T8 |
7356 |
7188 |
0 |
18 |
T9 |
13644 |
12948 |
0 |
18 |
T26 |
8952 |
8442 |
0 |
18 |
T27 |
9114 |
8742 |
0 |
18 |
T28 |
9636 |
8070 |
0 |
18 |
T29 |
6912 |
6648 |
0 |
18 |
T30 |
7890 |
7848 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
2326660 |
2304001 |
0 |
21 |
T4 |
154430 |
17591 |
0 |
21 |
T7 |
69672 |
69042 |
0 |
21 |
T8 |
30367 |
29671 |
0 |
21 |
T9 |
27107 |
25739 |
0 |
21 |
T26 |
10057 |
9456 |
0 |
21 |
T27 |
33200 |
31866 |
0 |
21 |
T28 |
11510 |
9639 |
0 |
21 |
T29 |
13746 |
13228 |
0 |
21 |
T30 |
95823 |
95451 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
212985 |
0 |
0 |
T1 |
2326660 |
2641 |
0 |
0 |
T2 |
0 |
1081 |
0 |
0 |
T4 |
154430 |
20 |
0 |
0 |
T7 |
51232 |
144 |
0 |
0 |
T8 |
22980 |
89 |
0 |
0 |
T9 |
27107 |
138 |
0 |
0 |
T19 |
9633 |
0 |
0 |
0 |
T20 |
5201 |
0 |
0 |
0 |
T22 |
0 |
19 |
0 |
0 |
T25 |
0 |
177 |
0 |
0 |
T26 |
10057 |
24 |
0 |
0 |
T27 |
33200 |
124 |
0 |
0 |
T28 |
11510 |
28 |
0 |
0 |
T29 |
13746 |
38 |
0 |
0 |
T30 |
95823 |
40 |
0 |
0 |
T68 |
0 |
7 |
0 |
0 |
T69 |
0 |
43 |
0 |
0 |
T103 |
0 |
149 |
0 |
0 |
T104 |
0 |
6 |
0 |
0 |
T106 |
0 |
27 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5061098 |
5024377 |
0 |
0 |
T4 |
255751 |
75969 |
0 |
0 |
T7 |
110121 |
109448 |
0 |
0 |
T8 |
47351 |
46460 |
0 |
0 |
T9 |
46447 |
44627 |
0 |
0 |
T26 |
19123 |
18232 |
0 |
0 |
T27 |
52824 |
51199 |
0 |
0 |
T28 |
21533 |
18567 |
0 |
0 |
T29 |
23409 |
22764 |
0 |
0 |
T30 |
142400 |
142036 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563293994 |
559232322 |
0 |
0 |
T1 |
295010 |
292226 |
0 |
0 |
T4 |
25042 |
2870 |
0 |
0 |
T7 |
12294 |
12187 |
0 |
0 |
T8 |
4935 |
4814 |
0 |
0 |
T9 |
4367 |
4150 |
0 |
0 |
T26 |
1373 |
1293 |
0 |
0 |
T27 |
5838 |
5607 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
2214 |
2135 |
0 |
0 |
T30 |
18037 |
17970 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563293994 |
559225386 |
0 |
2415 |
T1 |
295010 |
292223 |
0 |
3 |
T4 |
25042 |
2855 |
0 |
3 |
T7 |
12294 |
12184 |
0 |
3 |
T8 |
4935 |
4811 |
0 |
3 |
T9 |
4367 |
4147 |
0 |
3 |
T26 |
1373 |
1290 |
0 |
3 |
T27 |
5838 |
5604 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
2214 |
2132 |
0 |
3 |
T30 |
18037 |
17967 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563293994 |
29598 |
0 |
0 |
T1 |
295010 |
396 |
0 |
0 |
T2 |
0 |
460 |
0 |
0 |
T4 |
25042 |
0 |
0 |
0 |
T9 |
4367 |
43 |
0 |
0 |
T19 |
3145 |
0 |
0 |
0 |
T20 |
1687 |
0 |
0 |
0 |
T22 |
0 |
10 |
0 |
0 |
T25 |
0 |
106 |
0 |
0 |
T26 |
1373 |
0 |
0 |
0 |
T27 |
5838 |
52 |
0 |
0 |
T28 |
1606 |
7 |
0 |
0 |
T29 |
2214 |
0 |
0 |
0 |
T30 |
18037 |
0 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
21 |
0 |
0 |
T103 |
0 |
59 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174151236 |
0 |
2415 |
T1 |
338801 |
335533 |
0 |
3 |
T4 |
12522 |
1420 |
0 |
3 |
T7 |
3073 |
3043 |
0 |
3 |
T8 |
1226 |
1198 |
0 |
3 |
T9 |
2274 |
2158 |
0 |
3 |
T26 |
1492 |
1407 |
0 |
3 |
T27 |
1519 |
1457 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
1152 |
1108 |
0 |
3 |
T30 |
1315 |
1308 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
18627 |
0 |
0 |
T1 |
338801 |
262 |
0 |
0 |
T2 |
0 |
284 |
0 |
0 |
T4 |
12522 |
0 |
0 |
0 |
T9 |
2274 |
27 |
0 |
0 |
T19 |
3244 |
0 |
0 |
0 |
T20 |
1757 |
0 |
0 |
0 |
T25 |
0 |
34 |
0 |
0 |
T26 |
1492 |
0 |
0 |
0 |
T27 |
1519 |
19 |
0 |
0 |
T28 |
1606 |
11 |
0 |
0 |
T29 |
1152 |
0 |
0 |
0 |
T30 |
1315 |
0 |
0 |
0 |
T69 |
0 |
2 |
0 |
0 |
T103 |
0 |
51 |
0 |
0 |
T104 |
0 |
6 |
0 |
0 |
T106 |
0 |
27 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T9,T27,T28 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T9,T27,T28 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174151236 |
0 |
2415 |
T1 |
338801 |
335533 |
0 |
3 |
T4 |
12522 |
1420 |
0 |
3 |
T7 |
3073 |
3043 |
0 |
3 |
T8 |
1226 |
1198 |
0 |
3 |
T9 |
2274 |
2158 |
0 |
3 |
T26 |
1492 |
1407 |
0 |
3 |
T27 |
1519 |
1457 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
1152 |
1108 |
0 |
3 |
T30 |
1315 |
1308 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
21318 |
0 |
0 |
T1 |
338801 |
272 |
0 |
0 |
T2 |
0 |
337 |
0 |
0 |
T4 |
12522 |
0 |
0 |
0 |
T9 |
2274 |
12 |
0 |
0 |
T19 |
3244 |
0 |
0 |
0 |
T20 |
1757 |
0 |
0 |
0 |
T22 |
0 |
9 |
0 |
0 |
T25 |
0 |
37 |
0 |
0 |
T26 |
1492 |
0 |
0 |
0 |
T27 |
1519 |
13 |
0 |
0 |
T28 |
1606 |
2 |
0 |
0 |
T29 |
1152 |
0 |
0 |
0 |
T30 |
1315 |
0 |
0 |
0 |
T68 |
0 |
4 |
0 |
0 |
T69 |
0 |
20 |
0 |
0 |
T103 |
0 |
39 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
596067480 |
0 |
0 |
T1 |
338512 |
336780 |
0 |
0 |
T4 |
26086 |
17531 |
0 |
0 |
T7 |
12808 |
12782 |
0 |
0 |
T8 |
5745 |
5647 |
0 |
0 |
T9 |
4548 |
4451 |
0 |
0 |
T26 |
1425 |
1399 |
0 |
0 |
T27 |
6081 |
5955 |
0 |
0 |
T28 |
1673 |
1533 |
0 |
0 |
T29 |
2307 |
2281 |
0 |
0 |
T30 |
18789 |
18763 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
596067480 |
0 |
0 |
T1 |
338512 |
336780 |
0 |
0 |
T4 |
26086 |
17531 |
0 |
0 |
T7 |
12808 |
12782 |
0 |
0 |
T8 |
5745 |
5647 |
0 |
0 |
T9 |
4548 |
4451 |
0 |
0 |
T26 |
1425 |
1399 |
0 |
0 |
T27 |
6081 |
5955 |
0 |
0 |
T28 |
1673 |
1533 |
0 |
0 |
T29 |
2307 |
2281 |
0 |
0 |
T30 |
18789 |
18763 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563293994 |
561304215 |
0 |
0 |
T1 |
295010 |
293731 |
0 |
0 |
T4 |
25042 |
16831 |
0 |
0 |
T7 |
12294 |
12269 |
0 |
0 |
T8 |
4935 |
4842 |
0 |
0 |
T9 |
4367 |
4273 |
0 |
0 |
T26 |
1373 |
1348 |
0 |
0 |
T27 |
5838 |
5717 |
0 |
0 |
T28 |
1606 |
1471 |
0 |
0 |
T29 |
2214 |
2189 |
0 |
0 |
T30 |
18037 |
18012 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563293994 |
561304215 |
0 |
0 |
T1 |
295010 |
293731 |
0 |
0 |
T4 |
25042 |
16831 |
0 |
0 |
T7 |
12294 |
12269 |
0 |
0 |
T8 |
4935 |
4842 |
0 |
0 |
T9 |
4367 |
4273 |
0 |
0 |
T26 |
1373 |
1348 |
0 |
0 |
T27 |
5838 |
5717 |
0 |
0 |
T28 |
1606 |
1471 |
0 |
0 |
T29 |
2214 |
2189 |
0 |
0 |
T30 |
18037 |
18012 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
281016201 |
281016201 |
0 |
0 |
T1 |
146950 |
146950 |
0 |
0 |
T4 |
8416 |
8416 |
0 |
0 |
T7 |
6135 |
6135 |
0 |
0 |
T8 |
2421 |
2421 |
0 |
0 |
T9 |
2343 |
2343 |
0 |
0 |
T26 |
674 |
674 |
0 |
0 |
T27 |
3034 |
3034 |
0 |
0 |
T28 |
749 |
749 |
0 |
0 |
T29 |
1095 |
1095 |
0 |
0 |
T30 |
9006 |
9006 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
281016201 |
281016201 |
0 |
0 |
T1 |
146950 |
146950 |
0 |
0 |
T4 |
8416 |
8416 |
0 |
0 |
T7 |
6135 |
6135 |
0 |
0 |
T8 |
2421 |
2421 |
0 |
0 |
T9 |
2343 |
2343 |
0 |
0 |
T26 |
674 |
674 |
0 |
0 |
T27 |
3034 |
3034 |
0 |
0 |
T28 |
749 |
749 |
0 |
0 |
T29 |
1095 |
1095 |
0 |
0 |
T30 |
9006 |
9006 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
140507411 |
140507411 |
0 |
0 |
T1 |
734740 |
734740 |
0 |
0 |
T4 |
4209 |
4209 |
0 |
0 |
T7 |
3067 |
3067 |
0 |
0 |
T8 |
1211 |
1211 |
0 |
0 |
T9 |
1170 |
1170 |
0 |
0 |
T26 |
337 |
337 |
0 |
0 |
T27 |
1515 |
1515 |
0 |
0 |
T28 |
374 |
374 |
0 |
0 |
T29 |
547 |
547 |
0 |
0 |
T30 |
4503 |
4503 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
140507411 |
140507411 |
0 |
0 |
T1 |
734740 |
734740 |
0 |
0 |
T4 |
4209 |
4209 |
0 |
0 |
T7 |
3067 |
3067 |
0 |
0 |
T8 |
1211 |
1211 |
0 |
0 |
T9 |
1170 |
1170 |
0 |
0 |
T26 |
337 |
337 |
0 |
0 |
T27 |
1515 |
1515 |
0 |
0 |
T28 |
374 |
374 |
0 |
0 |
T29 |
547 |
547 |
0 |
0 |
T30 |
4503 |
4503 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
287213419 |
286204173 |
0 |
0 |
T1 |
159032 |
158236 |
0 |
0 |
T4 |
12522 |
8416 |
0 |
0 |
T7 |
6147 |
6135 |
0 |
0 |
T8 |
2703 |
2657 |
0 |
0 |
T9 |
2183 |
2136 |
0 |
0 |
T26 |
662 |
650 |
0 |
0 |
T27 |
2918 |
2858 |
0 |
0 |
T28 |
803 |
736 |
0 |
0 |
T29 |
1106 |
1094 |
0 |
0 |
T30 |
9019 |
9006 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
287213419 |
286204173 |
0 |
0 |
T1 |
159032 |
158236 |
0 |
0 |
T4 |
12522 |
8416 |
0 |
0 |
T7 |
6147 |
6135 |
0 |
0 |
T8 |
2703 |
2657 |
0 |
0 |
T9 |
2183 |
2136 |
0 |
0 |
T26 |
662 |
650 |
0 |
0 |
T27 |
2918 |
2858 |
0 |
0 |
T28 |
803 |
736 |
0 |
0 |
T29 |
1106 |
1094 |
0 |
0 |
T30 |
9019 |
9006 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174151236 |
0 |
2415 |
T1 |
338801 |
335533 |
0 |
3 |
T4 |
12522 |
1420 |
0 |
3 |
T7 |
3073 |
3043 |
0 |
3 |
T8 |
1226 |
1198 |
0 |
3 |
T9 |
2274 |
2158 |
0 |
3 |
T26 |
1492 |
1407 |
0 |
3 |
T27 |
1519 |
1457 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
1152 |
1108 |
0 |
3 |
T30 |
1315 |
1308 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174151236 |
0 |
2415 |
T1 |
338801 |
335533 |
0 |
3 |
T4 |
12522 |
1420 |
0 |
3 |
T7 |
3073 |
3043 |
0 |
3 |
T8 |
1226 |
1198 |
0 |
3 |
T9 |
2274 |
2158 |
0 |
3 |
T26 |
1492 |
1407 |
0 |
3 |
T27 |
1519 |
1457 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
1152 |
1108 |
0 |
3 |
T30 |
1315 |
1308 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174151236 |
0 |
2415 |
T1 |
338801 |
335533 |
0 |
3 |
T4 |
12522 |
1420 |
0 |
3 |
T7 |
3073 |
3043 |
0 |
3 |
T8 |
1226 |
1198 |
0 |
3 |
T9 |
2274 |
2158 |
0 |
3 |
T26 |
1492 |
1407 |
0 |
3 |
T27 |
1519 |
1457 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
1152 |
1108 |
0 |
3 |
T30 |
1315 |
1308 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174151236 |
0 |
2415 |
T1 |
338801 |
335533 |
0 |
3 |
T4 |
12522 |
1420 |
0 |
3 |
T7 |
3073 |
3043 |
0 |
3 |
T8 |
1226 |
1198 |
0 |
3 |
T9 |
2274 |
2158 |
0 |
3 |
T26 |
1492 |
1407 |
0 |
3 |
T27 |
1519 |
1457 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
1152 |
1108 |
0 |
3 |
T30 |
1315 |
1308 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174151236 |
0 |
2415 |
T1 |
338801 |
335533 |
0 |
3 |
T4 |
12522 |
1420 |
0 |
3 |
T7 |
3073 |
3043 |
0 |
3 |
T8 |
1226 |
1198 |
0 |
3 |
T9 |
2274 |
2158 |
0 |
3 |
T26 |
1492 |
1407 |
0 |
3 |
T27 |
1519 |
1457 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
1152 |
1108 |
0 |
3 |
T30 |
1315 |
1308 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174151236 |
0 |
2415 |
T1 |
338801 |
335533 |
0 |
3 |
T4 |
12522 |
1420 |
0 |
3 |
T7 |
3073 |
3043 |
0 |
3 |
T8 |
1226 |
1198 |
0 |
3 |
T9 |
2274 |
2158 |
0 |
3 |
T26 |
1492 |
1407 |
0 |
3 |
T27 |
1519 |
1457 |
0 |
3 |
T28 |
1606 |
1345 |
0 |
3 |
T29 |
1152 |
1108 |
0 |
3 |
T30 |
1315 |
1308 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
174158392 |
0 |
0 |
T1 |
338801 |
335536 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
3073 |
3046 |
0 |
0 |
T8 |
1226 |
1201 |
0 |
0 |
T9 |
2274 |
2161 |
0 |
0 |
T26 |
1492 |
1410 |
0 |
0 |
T27 |
1519 |
1460 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
1152 |
1111 |
0 |
0 |
T30 |
1315 |
1311 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593871913 |
0 |
2415 |
T1 |
338512 |
335178 |
0 |
3 |
T4 |
26086 |
2974 |
0 |
3 |
T7 |
12808 |
12693 |
0 |
3 |
T8 |
5745 |
5616 |
0 |
3 |
T9 |
4548 |
4319 |
0 |
3 |
T26 |
1425 |
1338 |
0 |
3 |
T27 |
6081 |
5837 |
0 |
3 |
T28 |
1673 |
1401 |
0 |
3 |
T29 |
2307 |
2220 |
0 |
3 |
T30 |
18789 |
18717 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
35674 |
0 |
0 |
T1 |
338512 |
415 |
0 |
0 |
T4 |
26086 |
5 |
0 |
0 |
T7 |
12808 |
43 |
0 |
0 |
T8 |
5745 |
13 |
0 |
0 |
T9 |
4548 |
20 |
0 |
0 |
T26 |
1425 |
9 |
0 |
0 |
T27 |
6081 |
11 |
0 |
0 |
T28 |
1673 |
3 |
0 |
0 |
T29 |
2307 |
5 |
0 |
0 |
T30 |
18789 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593871913 |
0 |
2415 |
T1 |
338512 |
335178 |
0 |
3 |
T4 |
26086 |
2974 |
0 |
3 |
T7 |
12808 |
12693 |
0 |
3 |
T8 |
5745 |
5616 |
0 |
3 |
T9 |
4548 |
4319 |
0 |
3 |
T26 |
1425 |
1338 |
0 |
3 |
T27 |
6081 |
5837 |
0 |
3 |
T28 |
1673 |
1401 |
0 |
3 |
T29 |
2307 |
2220 |
0 |
3 |
T30 |
18789 |
18717 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
35955 |
0 |
0 |
T1 |
338512 |
456 |
0 |
0 |
T4 |
26086 |
5 |
0 |
0 |
T7 |
12808 |
27 |
0 |
0 |
T8 |
5745 |
28 |
0 |
0 |
T9 |
4548 |
10 |
0 |
0 |
T26 |
1425 |
5 |
0 |
0 |
T27 |
6081 |
9 |
0 |
0 |
T28 |
1673 |
1 |
0 |
0 |
T29 |
2307 |
9 |
0 |
0 |
T30 |
18789 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593871913 |
0 |
2415 |
T1 |
338512 |
335178 |
0 |
3 |
T4 |
26086 |
2974 |
0 |
3 |
T7 |
12808 |
12693 |
0 |
3 |
T8 |
5745 |
5616 |
0 |
3 |
T9 |
4548 |
4319 |
0 |
3 |
T26 |
1425 |
1338 |
0 |
3 |
T27 |
6081 |
5837 |
0 |
3 |
T28 |
1673 |
1401 |
0 |
3 |
T29 |
2307 |
2220 |
0 |
3 |
T30 |
18789 |
18717 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
35711 |
0 |
0 |
T1 |
338512 |
425 |
0 |
0 |
T4 |
26086 |
5 |
0 |
0 |
T7 |
12808 |
31 |
0 |
0 |
T8 |
5745 |
24 |
0 |
0 |
T9 |
4548 |
12 |
0 |
0 |
T26 |
1425 |
5 |
0 |
0 |
T27 |
6081 |
9 |
0 |
0 |
T28 |
1673 |
1 |
0 |
0 |
T29 |
2307 |
11 |
0 |
0 |
T30 |
18789 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593871913 |
0 |
2415 |
T1 |
338512 |
335178 |
0 |
3 |
T4 |
26086 |
2974 |
0 |
3 |
T7 |
12808 |
12693 |
0 |
3 |
T8 |
5745 |
5616 |
0 |
3 |
T9 |
4548 |
4319 |
0 |
3 |
T26 |
1425 |
1338 |
0 |
3 |
T27 |
6081 |
5837 |
0 |
3 |
T28 |
1673 |
1401 |
0 |
3 |
T29 |
2307 |
2220 |
0 |
3 |
T30 |
18789 |
18717 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
36102 |
0 |
0 |
T1 |
338512 |
415 |
0 |
0 |
T4 |
26086 |
5 |
0 |
0 |
T7 |
12808 |
43 |
0 |
0 |
T8 |
5745 |
24 |
0 |
0 |
T9 |
4548 |
14 |
0 |
0 |
T26 |
1425 |
5 |
0 |
0 |
T27 |
6081 |
11 |
0 |
0 |
T28 |
1673 |
3 |
0 |
0 |
T29 |
2307 |
13 |
0 |
0 |
T30 |
18789 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
598170860 |
593878929 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |