Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T9
0	1	Unreachable
1	0	Covered	T4,T1,T5

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	176571626	173999276	0	0
AllClkBypReqTrue_A	176571626	156804	0	0
IoClkBypReqFalse_A	176571626	173912130	0	2415
IoClkBypReqTrue_A	176571626	239326	0	0
LcClkBypAckFalse_A	176571626	174012837	0	0
LcClkBypAckTrue_A	176571626	143243	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	173999276	0	0
T1	338801	335390	0	0
T4	12522	1430	0	0
T7	3073	3045	0	0
T8	1226	1200	0	0
T9	2274	2160	0	0
T26	1492	1409	0	0
T27	1519	1392	0	0
T28	1606	1347	0	0
T29	1152	1110	0	0
T30	1315	1310	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	156804	0	0
T1	338801	1446	0	0
T2	0	3525	0	0
T4	12522	0	0	0
T6	33794	0	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	0	8	0	0
T25	0	123	0	0
T27	1519	67	0	0
T28	1606	0	0	0
T29	1152	0	0	0
T30	1315	0	0	0
T68	0	23	0	0
T69	0	56	0	0
T103	0	221	0	0
T104	0	8	0	0
T105	0	61	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	173912130	0	2415
T1	338801	335290	0	3
T4	12522	1420	0	3
T7	3073	3043	0	3
T8	1226	1198	0	3
T9	2274	1791	0	3
T26	1492	1407	0	3
T27	1519	1208	0	3
T28	1606	1283	0	3
T29	1152	1108	0	3
T30	1315	1308	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	239326	0	0
T1	338801	2432	0	0
T2	0	5007	0	0
T4	12522	0	0	0
T9	2274	367	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T25	0	470	0	0
T26	1492	0	0	0
T27	1519	249	0	0
T28	1606	62	0	0
T29	1152	0	0	0
T30	1315	0	0	0
T69	0	24	0	0
T103	0	472	0	0
T104	0	53	0	0
T106	0	312	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	174012837	0	0
T1	338801	335397	0	0
T4	12522	1430	0	0
T7	3073	3045	0	0
T8	1226	1200	0	0
T9	2274	1959	0	0
T26	1492	1409	0	0
T27	1519	1384	0	0
T28	1606	1330	0	0
T29	1152	1110	0	0
T30	1315	1310	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	143243	0	0
T1	338801	1379	0	0
T2	0	2837	0	0
T4	12522	0	0	0
T9	2274	201	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T25	0	178	0	0
T26	1492	0	0	0
T27	1519	75	0	0
T28	1606	17	0	0
T29	1152	0	0	0
T30	1315	0	0	0
T103	0	268	0	0
T104	0	10	0	0
T106	0	97	0	0
T107	0	89	0	0