Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	17723	0	0
TransStop_A	2147483647	8828	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17723	0	0
T1	1354048	170	0	0
T2	0	237	0	0
T4	104348	0	0	0
T7	51232	24	0	0
T8	22980	0	0	0
T9	18196	0	0	0
T19	0	34	0	0
T20	0	4	0	0
T26	5704	0	0	0
T27	24328	0	0	0
T28	6692	0	0	0
T29	9228	0	0	0
T30	75156	7	0	0
T108	0	23	0	0
T109	0	35	0	0
T110	0	20	0	0
T111	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8828	0	0
T1	1354048	92	0	0
T2	0	129	0	0
T4	104348	0	0	0
T7	51232	11	0	0
T8	22980	0	0	0
T9	18196	0	0	0
T19	0	29	0	0
T20	0	4	0	0
T26	5704	0	0	0
T27	24328	0	0	0
T28	6692	0	0	0
T29	9228	0	0	0
T30	75156	0	0	0
T108	0	13	0	0
T109	0	20	0	0
T110	0	11	0	0
T111	0	4	0	0
T112	0	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	598171292	4405	0	0
TransStop_A	598171292	2211	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598171292	4405	0	0
T1	338512	42	0	0
T2	0	69	0	0
T4	26087	0	0	0
T7	12808	5	0	0
T8	5745	0	0	0
T9	4549	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1426	0	0	0
T27	6082	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	1	0	0
T108	0	5	0	0
T109	0	7	0	0
T110	0	7	0	0
T111	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598171292	2211	0	0
T1	338512	23	0	0
T2	0	42	0	0
T4	26087	0	0	0
T7	12808	2	0	0
T8	5745	0	0	0
T9	4549	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1426	0	0	0
T27	6082	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	0	0	0
T108	0	3	0	0
T109	0	4	0	0
T110	0	4	0	0
T111	0	1	0	0
T112	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	598171292	4419	0	0
TransStop_A	598171292	2227	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598171292	4419	0	0
T1	338512	38	0	0
T2	0	60	0	0
T4	26087	0	0	0
T7	12808	6	0	0
T8	5745	0	0	0
T9	4549	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1426	0	0	0
T27	6082	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	2	0	0
T108	0	7	0	0
T109	0	6	0	0
T110	0	6	0	0
T111	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598171292	2227	0	0
T1	338512	23	0	0
T2	0	31	0	0
T4	26087	0	0	0
T7	12808	3	0	0
T8	5745	0	0	0
T9	4549	0	0	0
T19	0	6	0	0
T20	0	1	0	0
T26	1426	0	0	0
T27	6082	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	0	0	0
T108	0	4	0	0
T109	0	2	0	0
T110	0	4	0	0
T111	0	1	0	0
T112	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	598171292	4494	0	0
TransStop_A	598171292	2192	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598171292	4494	0	0
T1	338512	45	0	0
T2	0	55	0	0
T4	26087	0	0	0
T7	12808	7	0	0
T8	5745	0	0	0
T9	4549	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1426	0	0	0
T27	6082	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	3	0	0
T108	0	5	0	0
T109	0	12	0	0
T110	0	4	0	0
T111	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598171292	2192	0	0
T1	338512	22	0	0
T2	0	26	0	0
T4	26087	0	0	0
T7	12808	4	0	0
T8	5745	0	0	0
T9	4549	0	0	0
T19	0	7	0	0
T20	0	1	0	0
T26	1426	0	0	0
T27	6082	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	0	0	0
T108	0	2	0	0
T109	0	7	0	0
T110	0	2	0	0
T111	0	1	0	0
T112	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	598171292	4405	0	0
TransStop_A	598171292	2198	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598171292	4405	0	0
T1	338512	45	0	0
T2	0	53	0	0
T4	26087	0	0	0
T7	12808	6	0	0
T8	5745	0	0	0
T9	4549	0	0	0
T19	0	10	0	0
T20	0	1	0	0
T26	1426	0	0	0
T27	6082	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	1	0	0
T108	0	6	0	0
T109	0	10	0	0
T110	0	3	0	0
T111	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598171292	2198	0	0
T1	338512	24	0	0
T2	0	30	0	0
T4	26087	0	0	0
T7	12808	2	0	0
T8	5745	0	0	0
T9	4549	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1426	0	0	0
T27	6082	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	0	0	0
T108	0	4	0	0
T109	0	7	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	4	0	0