Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10CoveredT9,T27,T28 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT9,T27,T28
11CoveredT9,T27,T28 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T27,T28
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 702176267 702173852 0 0
selKnown1 1689881982 1689879567 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 702176267 702173852 0 0
T1 1028556 1028555 0 0
T4 21041 21038 0 0
T7 15337 15334 0 0
T8 6053 6050 0 0
T9 5650 5647 0 0
T26 1685 1682 0 0
T27 7408 7405 0 0
T28 1859 1856 0 0
T29 2737 2734 0 0
T30 22515 22512 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1689881982 1689879567 0 0
T1 885030 885030 0 0
T4 75126 75123 0 0
T7 36882 36879 0 0
T8 14805 14802 0 0
T9 13101 13098 0 0
T26 4119 4116 0 0
T27 17514 17511 0 0
T28 4818 4815 0 0
T29 6642 6639 0 0
T30 54111 54108 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 281016201 281015396 0 0
selKnown1 563293994 563293189 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 281016201 281015396 0 0
T1 146950 146950 0 0
T4 8416 8415 0 0
T7 6135 6134 0 0
T8 2421 2420 0 0
T9 2343 2342 0 0
T26 674 673 0 0
T27 3034 3033 0 0
T28 749 748 0 0
T29 1095 1094 0 0
T30 9006 9005 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 563293994 563293189 0 0
T1 295010 295010 0 0
T4 25042 25041 0 0
T7 12294 12293 0 0
T8 4935 4934 0 0
T9 4367 4366 0 0
T26 1373 1372 0 0
T27 5838 5837 0 0
T28 1606 1605 0 0
T29 2214 2213 0 0
T30 18037 18036 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10CoveredT9,T27,T28 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT9,T27,T28
11CoveredT9,T27,T28 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9,T27,T28
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 280652655 280651850 0 0
selKnown1 563293994 563293189 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 280652655 280651850 0 0
T1 146866 146866 0 0
T4 8416 8415 0 0
T7 6135 6134 0 0
T8 2421 2420 0 0
T9 2137 2136 0 0
T26 674 673 0 0
T27 2859 2858 0 0
T28 736 735 0 0
T29 1095 1094 0 0
T30 9006 9005 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 563293994 563293189 0 0
T1 295010 295010 0 0
T4 25042 25041 0 0
T7 12294 12293 0 0
T8 4935 4934 0 0
T9 4367 4366 0 0
T26 1373 1372 0 0
T27 5838 5837 0 0
T28 1606 1605 0 0
T29 2214 2213 0 0
T30 18037 18036 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT7,T8,T9
01CoveredT7,T8,T9
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT7,T8,T9
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT7,T8,T9
11CoveredT7,T8,T9
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 140507411 140506606 0 0
selKnown1 563293994 563293189 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 140507411 140506606 0 0
T1 734740 734739 0 0
T4 4209 4208 0 0
T7 3067 3066 0 0
T8 1211 1210 0 0
T9 1170 1169 0 0
T26 337 336 0 0
T27 1515 1514 0 0
T28 374 373 0 0
T29 547 546 0 0
T30 4503 4502 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 563293994 563293189 0 0
T1 295010 295010 0 0
T4 25042 25041 0 0
T7 12294 12293 0 0
T8 4935 4934 0 0
T9 4367 4366 0 0
T26 1373 1372 0 0
T27 5838 5837 0 0
T28 1606 1605 0 0
T29 2214 2213 0 0
T30 18037 18036 0 0

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