SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 353143252 | 348316784 | 0 | 0 |
gen_flops.OutputDelay_A | 353143252 | 348302472 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T7 | 2 | 2 | 0 | 0 |
T8 | 2 | 2 | 0 | 0 |
T9 | 2 | 2 | 0 | 0 |
T26 | 2 | 2 | 0 | 0 |
T27 | 2 | 2 | 0 | 0 |
T28 | 2 | 2 | 0 | 0 |
T29 | 2 | 2 | 0 | 0 |
T30 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 353143252 | 348316784 | 0 | 0 |
T1 | 677602 | 671072 | 0 | 0 |
T4 | 25044 | 2870 | 0 | 0 |
T7 | 6146 | 6092 | 0 | 0 |
T8 | 2452 | 2402 | 0 | 0 |
T9 | 4548 | 4322 | 0 | 0 |
T26 | 2984 | 2820 | 0 | 0 |
T27 | 3038 | 2920 | 0 | 0 |
T28 | 3212 | 2696 | 0 | 0 |
T29 | 2304 | 2222 | 0 | 0 |
T30 | 2630 | 2622 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 353143252 | 348302472 | 0 | 4830 |
T1 | 677602 | 671066 | 0 | 6 |
T4 | 25044 | 2840 | 0 | 6 |
T7 | 6146 | 6086 | 0 | 6 |
T8 | 2452 | 2396 | 0 | 6 |
T9 | 4548 | 4316 | 0 | 6 |
T26 | 2984 | 2814 | 0 | 6 |
T27 | 3038 | 2914 | 0 | 6 |
T28 | 3212 | 2690 | 0 | 6 |
T29 | 2304 | 2216 | 0 | 6 |
T30 | 2630 | 2616 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 176571626 | 174158392 | 0 | 0 |
gen_flops.OutputDelay_A | 176571626 | 174151236 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 176571626 | 174158392 | 0 | 0 |
T1 | 338801 | 335536 | 0 | 0 |
T4 | 12522 | 1435 | 0 | 0 |
T7 | 3073 | 3046 | 0 | 0 |
T8 | 1226 | 1201 | 0 | 0 |
T9 | 2274 | 2161 | 0 | 0 |
T26 | 1492 | 1410 | 0 | 0 |
T27 | 1519 | 1460 | 0 | 0 |
T28 | 1606 | 1348 | 0 | 0 |
T29 | 1152 | 1111 | 0 | 0 |
T30 | 1315 | 1311 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 176571626 | 174151236 | 0 | 2415 |
T1 | 338801 | 335533 | 0 | 3 |
T4 | 12522 | 1420 | 0 | 3 |
T7 | 3073 | 3043 | 0 | 3 |
T8 | 1226 | 1198 | 0 | 3 |
T9 | 2274 | 2158 | 0 | 3 |
T26 | 1492 | 1407 | 0 | 3 |
T27 | 1519 | 1457 | 0 | 3 |
T28 | 1606 | 1345 | 0 | 3 |
T29 | 1152 | 1108 | 0 | 3 |
T30 | 1315 | 1308 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 176571626 | 174158392 | 0 | 0 |
gen_flops.OutputDelay_A | 176571626 | 174151236 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
T28 | 1 | 1 | 0 | 0 |
T29 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 176571626 | 174158392 | 0 | 0 |
T1 | 338801 | 335536 | 0 | 0 |
T4 | 12522 | 1435 | 0 | 0 |
T7 | 3073 | 3046 | 0 | 0 |
T8 | 1226 | 1201 | 0 | 0 |
T9 | 2274 | 2161 | 0 | 0 |
T26 | 1492 | 1410 | 0 | 0 |
T27 | 1519 | 1460 | 0 | 0 |
T28 | 1606 | 1348 | 0 | 0 |
T29 | 1152 | 1111 | 0 | 0 |
T30 | 1315 | 1311 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 176571626 | 174151236 | 0 | 2415 |
T1 | 338801 | 335533 | 0 | 3 |
T4 | 12522 | 1420 | 0 | 3 |
T7 | 3073 | 3043 | 0 | 3 |
T8 | 1226 | 1198 | 0 | 3 |
T9 | 2274 | 2158 | 0 | 3 |
T26 | 1492 | 1407 | 0 | 3 |
T27 | 1519 | 1457 | 0 | 3 |
T28 | 1606 | 1345 | 0 | 3 |
T29 | 1152 | 1108 | 0 | 3 |
T30 | 1315 | 1308 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |