Line Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Module :
prim_subreg_shadow
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T54,T55,T56 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T55,T56 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T54,T55,T56 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T55,T56 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T55,T56 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T55,T56 |
Branch Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Module :
prim_subreg_shadow
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10100 |
10100 |
0 |
0 |
T1 |
10 |
10 |
0 |
0 |
T4 |
10 |
10 |
0 |
0 |
T7 |
10 |
10 |
0 |
0 |
T8 |
10 |
10 |
0 |
0 |
T9 |
10 |
10 |
0 |
0 |
T26 |
10 |
10 |
0 |
0 |
T27 |
10 |
10 |
0 |
0 |
T28 |
10 |
10 |
0 |
0 |
T29 |
10 |
10 |
0 |
0 |
T30 |
10 |
10 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
3348488 |
3324098 |
0 |
0 |
T4 |
152550 |
18896 |
0 |
0 |
T7 |
80902 |
80234 |
0 |
0 |
T8 |
34030 |
33374 |
0 |
0 |
T9 |
29222 |
27934 |
0 |
0 |
T26 |
8942 |
8450 |
0 |
0 |
T27 |
38772 |
37432 |
0 |
0 |
T28 |
10410 |
8914 |
0 |
0 |
T29 |
14538 |
14052 |
0 |
0 |
T30 |
118708 |
118306 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T55,T57,T58 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T55,T56 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T55,T57,T58 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T55,T57 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T55,T57 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T55,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
566178526 |
561934471 |
0 |
0 |
T1 |
295010 |
292226 |
0 |
0 |
T4 |
25042 |
2870 |
0 |
0 |
T7 |
12294 |
12187 |
0 |
0 |
T8 |
4935 |
4814 |
0 |
0 |
T9 |
4367 |
4150 |
0 |
0 |
T26 |
1373 |
1293 |
0 |
0 |
T27 |
5838 |
5607 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
2214 |
2135 |
0 |
0 |
T30 |
18037 |
17970 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T55,T56,T57 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T55,T56 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T55,T56,T57 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T55,T57 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T55,T57 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T55,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
566178526 |
561934471 |
0 |
0 |
T1 |
295010 |
292226 |
0 |
0 |
T4 |
25042 |
2870 |
0 |
0 |
T7 |
12294 |
12187 |
0 |
0 |
T8 |
4935 |
4814 |
0 |
0 |
T9 |
4367 |
4150 |
0 |
0 |
T26 |
1373 |
1293 |
0 |
0 |
T27 |
5838 |
5607 |
0 |
0 |
T28 |
1606 |
1348 |
0 |
0 |
T29 |
2214 |
2135 |
0 |
0 |
T30 |
18037 |
17970 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T55,T59,T58 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T55,T57,T59 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T55,T59,T58 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T56,T57,T59 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T56,T57,T59 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T55,T57,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
282413476 |
281330821 |
0 |
0 |
T1 |
146950 |
146197 |
0 |
0 |
T4 |
8416 |
1435 |
0 |
0 |
T7 |
6135 |
6094 |
0 |
0 |
T8 |
2421 |
2407 |
0 |
0 |
T9 |
2343 |
2281 |
0 |
0 |
T26 |
674 |
646 |
0 |
0 |
T27 |
3034 |
2979 |
0 |
0 |
T28 |
749 |
687 |
0 |
0 |
T29 |
1095 |
1068 |
0 |
0 |
T30 |
9006 |
8985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T57,T59,T58 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T55,T56,T57 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T57,T59,T58 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T57,T59,T58 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T57,T59,T58 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T55,T56,T57 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
282413476 |
281330821 |
0 |
0 |
T1 |
146950 |
146197 |
0 |
0 |
T4 |
8416 |
1435 |
0 |
0 |
T7 |
6135 |
6094 |
0 |
0 |
T8 |
2421 |
2407 |
0 |
0 |
T9 |
2343 |
2281 |
0 |
0 |
T26 |
674 |
646 |
0 |
0 |
T27 |
3034 |
2979 |
0 |
0 |
T28 |
749 |
687 |
0 |
0 |
T29 |
1095 |
1068 |
0 |
0 |
T30 |
9006 |
8985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T54,T59,T58 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T56,T57 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T54,T59,T58 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T55,T56 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T55,T56 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T56,T57 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
141206072 |
140664855 |
0 |
0 |
T1 |
734740 |
730977 |
0 |
0 |
T4 |
4209 |
719 |
0 |
0 |
T7 |
3067 |
3046 |
0 |
0 |
T8 |
1211 |
1204 |
0 |
0 |
T9 |
1170 |
1139 |
0 |
0 |
T26 |
337 |
323 |
0 |
0 |
T27 |
1515 |
1487 |
0 |
0 |
T28 |
374 |
343 |
0 |
0 |
T29 |
547 |
533 |
0 |
0 |
T30 |
4503 |
4492 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T54,T59,T58 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T55,T56 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T54,T59,T58 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T55,T56 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T55,T56 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T55,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
141206072 |
140664855 |
0 |
0 |
T1 |
734740 |
730977 |
0 |
0 |
T4 |
4209 |
719 |
0 |
0 |
T7 |
3067 |
3046 |
0 |
0 |
T8 |
1211 |
1204 |
0 |
0 |
T9 |
1170 |
1139 |
0 |
0 |
T26 |
337 |
323 |
0 |
0 |
T27 |
1515 |
1487 |
0 |
0 |
T28 |
374 |
343 |
0 |
0 |
T29 |
547 |
533 |
0 |
0 |
T30 |
4503 |
4492 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T54,T56,T58 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T56,T57 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T54,T56,T58 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T59,T58 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T59,T58 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T56,T57 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
601175708 |
596693766 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T58,T60,T61 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T56,T57 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T58,T60,T61 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T59,T58 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T59,T58 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T56,T57 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
601175708 |
596693766 |
0 |
0 |
T1 |
338512 |
335181 |
0 |
0 |
T4 |
26086 |
2989 |
0 |
0 |
T7 |
12808 |
12696 |
0 |
0 |
T8 |
5745 |
5619 |
0 |
0 |
T9 |
4548 |
4322 |
0 |
0 |
T26 |
1425 |
1341 |
0 |
0 |
T27 |
6081 |
5840 |
0 |
0 |
T28 |
1673 |
1404 |
0 |
0 |
T29 |
2307 |
2223 |
0 |
0 |
T30 |
18789 |
18720 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T57,T58,T62 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T55,T56 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T57,T58,T62 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T55,T63 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T55,T63 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T55,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288655722 |
286497396 |
0 |
0 |
T1 |
159032 |
157468 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
6147 |
6094 |
0 |
0 |
T8 |
2703 |
2643 |
0 |
0 |
T9 |
2183 |
2075 |
0 |
0 |
T26 |
662 |
622 |
0 |
0 |
T27 |
2918 |
2803 |
0 |
0 |
T28 |
803 |
675 |
0 |
0 |
T29 |
1106 |
1067 |
0 |
0 |
T30 |
9019 |
8986 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T57,T58,T64 |
1 | 1 | Covered | T4,T1,T6 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T8,T9 |
0 | 1 | Covered | T54,T55,T56 |
1 | 0 | Covered | T4,T1,T5 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | Covered | T57,T58,T64 |
1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T7,T8,T9 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Covered | T4,T1,T6 |
1 | 1 | 0 | 1 | Covered | T54,T55,T63 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T4,T1,T6 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T4,T1,T6 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T1,T6 |
1 | Covered | T7,T8,T9 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T6 |
1 | 0 | Covered | T4,T1,T6 |
1 | 1 | Covered | T54,T55,T63 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T7,T8,T9 |
1 | Covered | T54,T55,T56 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T8,T9 |
0 |
Covered |
T4,T1,T6 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T7,T8,T9 |
0 |
1 |
- |
Covered |
T4,T1,T6 |
0 |
0 |
1 |
Covered |
T4,T1,T5 |
0 |
0 |
0 |
Covered |
T7,T8,T9 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
288655722 |
286497396 |
0 |
0 |
T1 |
159032 |
157468 |
0 |
0 |
T4 |
12522 |
1435 |
0 |
0 |
T7 |
6147 |
6094 |
0 |
0 |
T8 |
2703 |
2643 |
0 |
0 |
T9 |
2183 |
2075 |
0 |
0 |
T26 |
662 |
622 |
0 |
0 |
T27 |
2918 |
2803 |
0 |
0 |
T28 |
803 |
675 |
0 |
0 |
T29 |
1106 |
1067 |
0 |
0 |
T30 |
9019 |
8986 |
0 |
0 |