Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	176571626	20910157	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176571626	20910157	0	57
T1	338801	109405	0	0
T2	0	281122	0	0
T3	0	34125	0	1
T5	27579	0	0	0
T6	33794	995	0	1
T12	0	61058	0	0
T13	0	862824	0	0
T14	0	12803	0	0
T15	0	30316	0	0
T16	0	6790	0	1
T17	0	28824	0	1
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T25	2747	0	0	0
T31	0	0	0	1
T51	0	0	0	1
T73	0	0	0	1
T113	0	0	0	1
T114	0	0	0	1
T115	0	0	0	1