Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	177521995	5759286	0	0
clk_enables_rd_A	177521995	75131	0	0
clk_hints_rd_A	177521995	65845	0	0
extclk_ctrl_rd_A	177521995	83141	0	0
extclk_ctrl_regwen_rd_A	177521995	63286	0	0
jitter_enable_rd_A	177521995	92829	0	0
jitter_regwen_rd_A	177521995	72213	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	5759286	0	0
T1	338801	145599	0	0
T2	0	94762	0	0
T5	27579	0	0	0
T6	33794	0	0	0
T12	0	117064	0	0
T13	0	163698	0	0
T14	0	79962	0	0
T18	0	90053	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T22	1184	0	0	0
T23	1054	0	0	0
T24	1841	0	0	0
T25	2747	0	0	0
T32	0	134711	0	0
T37	0	126936	0	0
T38	0	199855	0	0
T65	0	217436	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	75131	0	0
T2	320922	3856	0	0
T13	0	3173	0	0
T37	0	5173	0	0
T67	750	0	0	0
T68	758	0	0	0
T69	1507	0	0	0
T103	1933	0	0	0
T104	1084	0	0	0
T105	1374	0	0	0
T106	1627	0	0	0
T108	1559	0	0	0
T109	2735	0	0	0
T133	0	3	0	0
T134	0	3	0	0
T135	0	2	0	0
T136	0	8	0	0
T137	0	3	0	0
T138	0	581	0	0
T139	0	1634	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	65845	0	0
T2	320922	3270	0	0
T13	0	3077	0	0
T37	0	4337	0	0
T67	750	0	0	0
T68	758	0	0	0
T69	1507	0	0	0
T103	1933	0	0	0
T104	1084	0	0	0
T105	1374	0	0	0
T106	1627	0	0	0
T108	1559	0	0	0
T109	2735	0	0	0
T133	0	4	0	0
T134	0	4	0	0
T135	0	12	0	0
T136	0	1	0	0
T137	0	10	0	0
T138	0	449	0	0
T139	0	1428	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	83141	0	0
T1	338801	0	0	0
T2	0	4047	0	0
T4	12522	0	0	0
T6	33794	0	0	0
T13	0	3225	0	0
T19	3244	0	0	0
T20	1757	0	0	0
T21	1020	0	0	0
T27	1519	12	0	0
T28	1606	0	0	0
T29	1152	0	0	0
T30	1315	0	0	0
T36	0	65	0	0
T37	0	5732	0	0
T71	0	97	0	0
T105	0	14	0	0
T135	0	103	0	0
T140	0	57	0	0
T141	0	44	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	63286	0	0
T2	320922	3240	0	0
T13	0	2844	0	0
T36	0	53	0	0
T37	0	4144	0	0
T67	750	0	0	0
T68	758	0	0	0
T69	1507	0	0	0
T71	0	46	0	0
T103	1933	0	0	0
T104	1084	0	0	0
T105	1374	0	0	0
T106	1627	0	0	0
T108	1559	0	0	0
T109	2735	0	0	0
T138	0	620	0	0
T139	0	1337	0	0
T142	0	5	0	0
T143	0	14	0	0
T144	0	4415	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	92829	0	0
T2	320922	4246	0	0
T13	0	3553	0	0
T37	0	6144	0	0
T67	750	0	0	0
T68	758	0	0	0
T69	1507	0	0	0
T103	1933	0	0	0
T104	1084	0	0	0
T105	1374	0	0	0
T106	1627	0	0	0
T108	1559	0	0	0
T109	2735	0	0	0
T133	0	136	0	0
T134	0	109	0	0
T135	0	232	0	0
T136	0	140	0	0
T137	0	114	0	0
T138	0	654	0	0
T139	0	1962	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	177521995	72213	0	0
T2	320922	3895	0	0
T13	0	3096	0	0
T37	0	5011	0	0
T67	750	0	0	0
T68	758	0	0	0
T69	1507	0	0	0
T103	1933	0	0	0
T104	1084	0	0	0
T105	1374	0	0	0
T106	1627	0	0	0
T108	1559	0	0	0
T109	2735	0	0	0
T138	0	602	0	0
T139	0	1434	0	0
T144	0	4758	0	0
T145	0	1265	0	0
T146	0	2032	0	0
T147	0	1767	0	0
T148	0	4739	0	0