SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.63 | 100.00 | 93.15 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T9,T27 |
1 | 0 | Covered | T9,T27,T28 |
1 | 1 | Covered | T9,T27,T28 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 563294411 | 4961 | 0 | 0 |
g_div2.Div2Whole_A | 563294411 | 5737 | 0 | 0 |
g_div4.Div4Stepped_A | 281016631 | 4873 | 0 | 0 |
g_div4.Div4Whole_A | 281016631 | 5502 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 563294411 | 4961 | 0 | 0 |
T1 | 295010 | 48 | 0 | 0 |
T2 | 0 | 80 | 0 | 0 |
T4 | 25042 | 0 | 0 | 0 |
T9 | 4367 | 8 | 0 | 0 |
T19 | 3146 | 0 | 0 | 0 |
T20 | 1687 | 0 | 0 | 0 |
T25 | 0 | 5 | 0 | 0 |
T26 | 1374 | 0 | 0 | 0 |
T27 | 5839 | 4 | 0 | 0 |
T28 | 1607 | 1 | 0 | 0 |
T29 | 2214 | 0 | 0 | 0 |
T30 | 18038 | 0 | 0 | 0 |
T68 | 0 | 1 | 0 | 0 |
T69 | 0 | 5 | 0 | 0 |
T103 | 0 | 10 | 0 | 0 |
T104 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 563294411 | 5737 | 0 | 0 |
T1 | 295010 | 74 | 0 | 0 |
T2 | 0 | 89 | 0 | 0 |
T4 | 25042 | 0 | 0 | 0 |
T9 | 4367 | 9 | 0 | 0 |
T19 | 3146 | 0 | 0 | 0 |
T20 | 1687 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T26 | 1374 | 0 | 0 | 0 |
T27 | 5839 | 4 | 0 | 0 |
T28 | 1607 | 1 | 0 | 0 |
T29 | 2214 | 0 | 0 | 0 |
T30 | 18038 | 0 | 0 | 0 |
T68 | 0 | 1 | 0 | 0 |
T69 | 0 | 5 | 0 | 0 |
T103 | 0 | 12 | 0 | 0 |
T104 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 281016631 | 4873 | 0 | 0 |
T1 | 146950 | 48 | 0 | 0 |
T2 | 0 | 80 | 0 | 0 |
T4 | 8417 | 0 | 0 | 0 |
T9 | 2343 | 8 | 0 | 0 |
T19 | 1533 | 0 | 0 | 0 |
T20 | 791 | 0 | 0 | 0 |
T25 | 0 | 4 | 0 | 0 |
T26 | 675 | 0 | 0 | 0 |
T27 | 3034 | 4 | 0 | 0 |
T28 | 749 | 1 | 0 | 0 |
T29 | 1095 | 0 | 0 | 0 |
T30 | 9007 | 0 | 0 | 0 |
T68 | 0 | 1 | 0 | 0 |
T69 | 0 | 5 | 0 | 0 |
T103 | 0 | 10 | 0 | 0 |
T104 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 281016631 | 5502 | 0 | 0 |
T1 | 146950 | 59 | 0 | 0 |
T2 | 0 | 89 | 0 | 0 |
T4 | 8417 | 0 | 0 | 0 |
T9 | 2343 | 9 | 0 | 0 |
T19 | 1533 | 0 | 0 | 0 |
T20 | 791 | 0 | 0 | 0 |
T25 | 0 | 10 | 0 | 0 |
T26 | 675 | 0 | 0 | 0 |
T27 | 3034 | 4 | 0 | 0 |
T28 | 749 | 1 | 0 | 0 |
T29 | 1095 | 0 | 0 | 0 |
T30 | 9007 | 0 | 0 | 0 |
T68 | 0 | 1 | 0 | 0 |
T69 | 0 | 4 | 0 | 0 |
T103 | 0 | 12 | 0 | 0 |
T104 | 0 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T9,T27 |
1 | 0 | Covered | T9,T27,T28 |
1 | 1 | Covered | T9,T27,T28 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 563294411 | 4961 | 0 | 0 |
g_div2.Div2Whole_A | 563294411 | 5737 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 563294411 | 4961 | 0 | 0 |
T1 | 295010 | 48 | 0 | 0 |
T2 | 0 | 80 | 0 | 0 |
T4 | 25042 | 0 | 0 | 0 |
T9 | 4367 | 8 | 0 | 0 |
T19 | 3146 | 0 | 0 | 0 |
T20 | 1687 | 0 | 0 | 0 |
T25 | 0 | 5 | 0 | 0 |
T26 | 1374 | 0 | 0 | 0 |
T27 | 5839 | 4 | 0 | 0 |
T28 | 1607 | 1 | 0 | 0 |
T29 | 2214 | 0 | 0 | 0 |
T30 | 18038 | 0 | 0 | 0 |
T68 | 0 | 1 | 0 | 0 |
T69 | 0 | 5 | 0 | 0 |
T103 | 0 | 10 | 0 | 0 |
T104 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 563294411 | 5737 | 0 | 0 |
T1 | 295010 | 74 | 0 | 0 |
T2 | 0 | 89 | 0 | 0 |
T4 | 25042 | 0 | 0 | 0 |
T9 | 4367 | 9 | 0 | 0 |
T19 | 3146 | 0 | 0 | 0 |
T20 | 1687 | 0 | 0 | 0 |
T25 | 0 | 11 | 0 | 0 |
T26 | 1374 | 0 | 0 | 0 |
T27 | 5839 | 4 | 0 | 0 |
T28 | 1607 | 1 | 0 | 0 |
T29 | 2214 | 0 | 0 | 0 |
T30 | 18038 | 0 | 0 | 0 |
T68 | 0 | 1 | 0 | 0 |
T69 | 0 | 5 | 0 | 0 |
T103 | 0 | 12 | 0 | 0 |
T104 | 0 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T7,T9,T27 |
1 | 0 | Covered | T9,T27,T28 |
1 | 1 | Covered | T9,T27,T28 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 281016631 | 4873 | 0 | 0 |
g_div4.Div4Whole_A | 281016631 | 5502 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 281016631 | 4873 | 0 | 0 |
T1 | 146950 | 48 | 0 | 0 |
T2 | 0 | 80 | 0 | 0 |
T4 | 8417 | 0 | 0 | 0 |
T9 | 2343 | 8 | 0 | 0 |
T19 | 1533 | 0 | 0 | 0 |
T20 | 791 | 0 | 0 | 0 |
T25 | 0 | 4 | 0 | 0 |
T26 | 675 | 0 | 0 | 0 |
T27 | 3034 | 4 | 0 | 0 |
T28 | 749 | 1 | 0 | 0 |
T29 | 1095 | 0 | 0 | 0 |
T30 | 9007 | 0 | 0 | 0 |
T68 | 0 | 1 | 0 | 0 |
T69 | 0 | 5 | 0 | 0 |
T103 | 0 | 10 | 0 | 0 |
T104 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 281016631 | 5502 | 0 | 0 |
T1 | 146950 | 59 | 0 | 0 |
T2 | 0 | 89 | 0 | 0 |
T4 | 8417 | 0 | 0 | 0 |
T9 | 2343 | 9 | 0 | 0 |
T19 | 1533 | 0 | 0 | 0 |
T20 | 791 | 0 | 0 | 0 |
T25 | 0 | 10 | 0 | 0 |
T26 | 675 | 0 | 0 | 0 |
T27 | 3034 | 4 | 0 | 0 |
T28 | 749 | 1 | 0 | 0 |
T29 | 1095 | 0 | 0 | 0 |
T30 | 9007 | 0 | 0 | 0 |
T68 | 0 | 1 | 0 | 0 |
T69 | 0 | 4 | 0 | 0 |
T103 | 0 | 12 | 0 | 0 |
T104 | 0 | 2 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |