Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T9,T27
10CoveredT9,T27,T28
11CoveredT9,T27,T28

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 563294411 4961 0 0
g_div2.Div2Whole_A 563294411 5737 0 0
g_div4.Div4Stepped_A 281016631 4873 0 0
g_div4.Div4Whole_A 281016631 5502 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 563294411 4961 0 0
T1 295010 48 0 0
T2 0 80 0 0
T4 25042 0 0 0
T9 4367 8 0 0
T19 3146 0 0 0
T20 1687 0 0 0
T25 0 5 0 0
T26 1374 0 0 0
T27 5839 4 0 0
T28 1607 1 0 0
T29 2214 0 0 0
T30 18038 0 0 0
T68 0 1 0 0
T69 0 5 0 0
T103 0 10 0 0
T104 0 3 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 563294411 5737 0 0
T1 295010 74 0 0
T2 0 89 0 0
T4 25042 0 0 0
T9 4367 9 0 0
T19 3146 0 0 0
T20 1687 0 0 0
T25 0 11 0 0
T26 1374 0 0 0
T27 5839 4 0 0
T28 1607 1 0 0
T29 2214 0 0 0
T30 18038 0 0 0
T68 0 1 0 0
T69 0 5 0 0
T103 0 12 0 0
T104 0 2 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 281016631 4873 0 0
T1 146950 48 0 0
T2 0 80 0 0
T4 8417 0 0 0
T9 2343 8 0 0
T19 1533 0 0 0
T20 791 0 0 0
T25 0 4 0 0
T26 675 0 0 0
T27 3034 4 0 0
T28 749 1 0 0
T29 1095 0 0 0
T30 9007 0 0 0
T68 0 1 0 0
T69 0 5 0 0
T103 0 10 0 0
T104 0 3 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 281016631 5502 0 0
T1 146950 59 0 0
T2 0 89 0 0
T4 8417 0 0 0
T9 2343 9 0 0
T19 1533 0 0 0
T20 791 0 0 0
T25 0 10 0 0
T26 675 0 0 0
T27 3034 4 0 0
T28 749 1 0 0
T29 1095 0 0 0
T30 9007 0 0 0
T68 0 1 0 0
T69 0 4 0 0
T103 0 12 0 0
T104 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T9,T27
10CoveredT9,T27,T28
11CoveredT9,T27,T28

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 563294411 4961 0 0
g_div2.Div2Whole_A 563294411 5737 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 563294411 4961 0 0
T1 295010 48 0 0
T2 0 80 0 0
T4 25042 0 0 0
T9 4367 8 0 0
T19 3146 0 0 0
T20 1687 0 0 0
T25 0 5 0 0
T26 1374 0 0 0
T27 5839 4 0 0
T28 1607 1 0 0
T29 2214 0 0 0
T30 18038 0 0 0
T68 0 1 0 0
T69 0 5 0 0
T103 0 10 0 0
T104 0 3 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 563294411 5737 0 0
T1 295010 74 0 0
T2 0 89 0 0
T4 25042 0 0 0
T9 4367 9 0 0
T19 3146 0 0 0
T20 1687 0 0 0
T25 0 11 0 0
T26 1374 0 0 0
T27 5839 4 0 0
T28 1607 1 0 0
T29 2214 0 0 0
T30 18038 0 0 0
T68 0 1 0 0
T69 0 5 0 0
T103 0 12 0 0
T104 0 2 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT7,T9,T27
10CoveredT9,T27,T28
11CoveredT9,T27,T28

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 281016631 4873 0 0
g_div4.Div4Whole_A 281016631 5502 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 281016631 4873 0 0
T1 146950 48 0 0
T2 0 80 0 0
T4 8417 0 0 0
T9 2343 8 0 0
T19 1533 0 0 0
T20 791 0 0 0
T25 0 4 0 0
T26 675 0 0 0
T27 3034 4 0 0
T28 749 1 0 0
T29 1095 0 0 0
T30 9007 0 0 0
T68 0 1 0 0
T69 0 5 0 0
T103 0 10 0 0
T104 0 3 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 281016631 5502 0 0
T1 146950 59 0 0
T2 0 89 0 0
T4 8417 0 0 0
T9 2343 9 0 0
T19 1533 0 0 0
T20 791 0 0 0
T25 0 10 0 0
T26 675 0 0 0
T27 3034 4 0 0
T28 749 1 0 0
T29 1095 0 0 0
T30 9007 0 0 0
T68 0 1 0 0
T69 0 4 0 0
T103 0 12 0 0
T104 0 2 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%