Module Definition
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Module : clkmgr_pwrmgr_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_pwrmgr_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_pwrmgr_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IoStatusFall_A 176571626 144 0 0
IoStatusRise_A 176571626 144 0 0
MainStatusFall_A 176571626 146 0 0
MainStatusRise_A 176571626 146 0 0
UsbStatusFall_A 176571626 149 0 0
UsbStatusRise_A 176571626 149 0 0


IoStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176571626 144 0 0
T1 338801 0 0 0
T4 12522 0 0 0
T8 1226 4 0 0
T9 2274 0 0 0
T19 3244 0 0 0
T26 1492 3 0 0
T27 1519 0 0 0
T28 1606 0 0 0
T29 1152 0 0 0
T30 1315 0 0 0
T40 0 1 0 0
T149 0 5 0 0
T150 0 4 0 0
T151 0 6 0 0
T152 0 3 0 0
T153 0 1 0 0
T154 0 3 0 0
T155 0 3 0 0

IoStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176571626 144 0 0
T1 338801 0 0 0
T4 12522 0 0 0
T8 1226 4 0 0
T9 2274 0 0 0
T19 3244 0 0 0
T26 1492 3 0 0
T27 1519 0 0 0
T28 1606 0 0 0
T29 1152 0 0 0
T30 1315 0 0 0
T40 0 1 0 0
T149 0 5 0 0
T150 0 4 0 0
T151 0 6 0 0
T152 0 3 0 0
T153 0 1 0 0
T154 0 3 0 0
T155 0 3 0 0

MainStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176571626 146 0 0
T1 338801 0 0 0
T4 12522 0 0 0
T8 1226 5 0 0
T9 2274 0 0 0
T19 3244 0 0 0
T26 1492 3 0 0
T27 1519 0 0 0
T28 1606 0 0 0
T29 1152 0 0 0
T30 1315 0 0 0
T40 0 1 0 0
T149 0 10 0 0
T150 0 4 0 0
T151 0 4 0 0
T152 0 2 0 0
T153 0 1 0 0
T154 0 3 0 0
T155 0 4 0 0

MainStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176571626 146 0 0
T1 338801 0 0 0
T4 12522 0 0 0
T8 1226 5 0 0
T9 2274 0 0 0
T19 3244 0 0 0
T26 1492 3 0 0
T27 1519 0 0 0
T28 1606 0 0 0
T29 1152 0 0 0
T30 1315 0 0 0
T40 0 1 0 0
T149 0 10 0 0
T150 0 4 0 0
T151 0 4 0 0
T152 0 2 0 0
T153 0 1 0 0
T154 0 3 0 0
T155 0 4 0 0

UsbStatusFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176571626 149 0 0
T1 338801 0 0 0
T4 12522 0 0 0
T8 1226 5 0 0
T9 2274 0 0 0
T19 3244 0 0 0
T26 1492 2 0 0
T27 1519 0 0 0
T28 1606 0 0 0
T29 1152 0 0 0
T30 1315 0 0 0
T40 0 1 0 0
T41 0 1 0 0
T149 0 3 0 0
T150 0 3 0 0
T151 0 5 0 0
T152 0 2 0 0
T154 0 4 0 0
T155 0 4 0 0

UsbStatusRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 176571626 149 0 0
T1 338801 0 0 0
T4 12522 0 0 0
T8 1226 5 0 0
T9 2274 0 0 0
T19 3244 0 0 0
T26 1492 2 0 0
T27 1519 0 0 0
T28 1606 0 0 0
T29 1152 0 0 0
T30 1315 0 0 0
T40 0 1 0 0
T41 0 1 0 0
T149 0 3 0 0
T150 0 3 0 0
T151 0 5 0 0
T152 0 2 0 0
T154 0 4 0 0
T155 0 4 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%