Assert Coverage for Module :
clkmgr_pwrmgr_sva_if
Assertion Details
IoStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
144 |
0 |
0 |
T1 |
338801 |
0 |
0 |
0 |
T4 |
12522 |
0 |
0 |
0 |
T8 |
1226 |
4 |
0 |
0 |
T9 |
2274 |
0 |
0 |
0 |
T19 |
3244 |
0 |
0 |
0 |
T26 |
1492 |
3 |
0 |
0 |
T27 |
1519 |
0 |
0 |
0 |
T28 |
1606 |
0 |
0 |
0 |
T29 |
1152 |
0 |
0 |
0 |
T30 |
1315 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T149 |
0 |
5 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
6 |
0 |
0 |
T152 |
0 |
3 |
0 |
0 |
T153 |
0 |
1 |
0 |
0 |
T154 |
0 |
3 |
0 |
0 |
T155 |
0 |
3 |
0 |
0 |
IoStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
144 |
0 |
0 |
T1 |
338801 |
0 |
0 |
0 |
T4 |
12522 |
0 |
0 |
0 |
T8 |
1226 |
4 |
0 |
0 |
T9 |
2274 |
0 |
0 |
0 |
T19 |
3244 |
0 |
0 |
0 |
T26 |
1492 |
3 |
0 |
0 |
T27 |
1519 |
0 |
0 |
0 |
T28 |
1606 |
0 |
0 |
0 |
T29 |
1152 |
0 |
0 |
0 |
T30 |
1315 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T149 |
0 |
5 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
6 |
0 |
0 |
T152 |
0 |
3 |
0 |
0 |
T153 |
0 |
1 |
0 |
0 |
T154 |
0 |
3 |
0 |
0 |
T155 |
0 |
3 |
0 |
0 |
MainStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
146 |
0 |
0 |
T1 |
338801 |
0 |
0 |
0 |
T4 |
12522 |
0 |
0 |
0 |
T8 |
1226 |
5 |
0 |
0 |
T9 |
2274 |
0 |
0 |
0 |
T19 |
3244 |
0 |
0 |
0 |
T26 |
1492 |
3 |
0 |
0 |
T27 |
1519 |
0 |
0 |
0 |
T28 |
1606 |
0 |
0 |
0 |
T29 |
1152 |
0 |
0 |
0 |
T30 |
1315 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T149 |
0 |
10 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T153 |
0 |
1 |
0 |
0 |
T154 |
0 |
3 |
0 |
0 |
T155 |
0 |
4 |
0 |
0 |
MainStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
146 |
0 |
0 |
T1 |
338801 |
0 |
0 |
0 |
T4 |
12522 |
0 |
0 |
0 |
T8 |
1226 |
5 |
0 |
0 |
T9 |
2274 |
0 |
0 |
0 |
T19 |
3244 |
0 |
0 |
0 |
T26 |
1492 |
3 |
0 |
0 |
T27 |
1519 |
0 |
0 |
0 |
T28 |
1606 |
0 |
0 |
0 |
T29 |
1152 |
0 |
0 |
0 |
T30 |
1315 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T149 |
0 |
10 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T153 |
0 |
1 |
0 |
0 |
T154 |
0 |
3 |
0 |
0 |
T155 |
0 |
4 |
0 |
0 |
UsbStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
149 |
0 |
0 |
T1 |
338801 |
0 |
0 |
0 |
T4 |
12522 |
0 |
0 |
0 |
T8 |
1226 |
5 |
0 |
0 |
T9 |
2274 |
0 |
0 |
0 |
T19 |
3244 |
0 |
0 |
0 |
T26 |
1492 |
2 |
0 |
0 |
T27 |
1519 |
0 |
0 |
0 |
T28 |
1606 |
0 |
0 |
0 |
T29 |
1152 |
0 |
0 |
0 |
T30 |
1315 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
T150 |
0 |
3 |
0 |
0 |
T151 |
0 |
5 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T154 |
0 |
4 |
0 |
0 |
T155 |
0 |
4 |
0 |
0 |
UsbStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
176571626 |
149 |
0 |
0 |
T1 |
338801 |
0 |
0 |
0 |
T4 |
12522 |
0 |
0 |
0 |
T8 |
1226 |
5 |
0 |
0 |
T9 |
2274 |
0 |
0 |
0 |
T19 |
3244 |
0 |
0 |
0 |
T26 |
1492 |
2 |
0 |
0 |
T27 |
1519 |
0 |
0 |
0 |
T28 |
1606 |
0 |
0 |
0 |
T29 |
1152 |
0 |
0 |
0 |
T30 |
1315 |
0 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T149 |
0 |
3 |
0 |
0 |
T150 |
0 |
3 |
0 |
0 |
T151 |
0 |
5 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T154 |
0 |
4 |
0 |
0 |
T155 |
0 |
4 |
0 |
0 |