Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	52224	0	0
CgEnOn_A	2147483647	42973	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52224	0	0
T1	6012984	382	0	0
T2	0	74	0	0
T4	252790	15	0	0
T7	78875	8	0	0
T8	56729	40	0	0
T9	47571	3	0	0
T19	13530	8	0	0
T20	0	1	0	0
T26	14654	30	0	0
T27	63208	3	0	0
T28	17047	3	0	0
T29	23754	27	0	0
T30	193851	4	0	0
T40	0	5	0	0
T108	0	5	0	0
T138	0	5	0	0
T149	0	25	0	0
T150	0	20	0	0
T151	0	30	0	0
T152	0	15	0	0
T153	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42973	0	0
T1	6012984	349	0	0
T2	0	324	0	0
T4	252790	0	0	0
T7	51232	5	0	0
T8	56729	37	0	0
T9	47571	0	0	0
T12	0	102	0	0
T19	20547	0	0	0
T20	0	2	0	0
T26	14654	27	0	0
T27	63208	0	0	0
T28	17047	0	0	0
T29	23754	24	0	0
T30	193851	1	0	0
T40	0	8	0	0
T67	0	9	0	0
T111	0	3	0	0
T133	0	3	0	0
T138	0	4	0	0
T149	0	25	0	0
T150	0	20	0	0
T151	0	30	0	0
T152	0	15	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	281016201	154	0	0
CgEnOn_A	281016201	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281016201	154	0	0
T1	146950	0	0	0
T2	0	1	0	0
T4	8416	0	0	0
T8	2421	4	0	0
T9	2343	0	0	0
T19	1533	0	0	0
T26	674	3	0	0
T27	3034	0	0	0
T28	749	0	0	0
T29	1095	0	0	0
T30	9006	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281016201	154	0	0
T1	146950	0	0	0
T2	0	1	0	0
T4	8416	0	0	0
T8	2421	4	0	0
T9	2343	0	0	0
T19	1533	0	0	0
T26	674	3	0	0
T27	3034	0	0	0
T28	749	0	0	0
T29	1095	0	0	0
T30	9006	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140507411	154	0	0
CgEnOn_A	140507411	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507411	154	0	0
T1	734740	0	0	0
T2	0	1	0	0
T4	4209	0	0	0
T8	1211	4	0	0
T9	1170	0	0	0
T19	766	0	0	0
T26	337	3	0	0
T27	1515	0	0	0
T28	374	0	0	0
T29	547	0	0	0
T30	4503	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507411	154	0	0
T1	734740	0	0	0
T2	0	1	0	0
T4	4209	0	0	0
T8	1211	4	0	0
T9	1170	0	0	0
T19	766	0	0	0
T26	337	3	0	0
T27	1515	0	0	0
T28	374	0	0	0
T29	547	0	0	0
T30	4503	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	563293994	154	0	0
CgEnOn_A	563293994	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563293994	154	0	0
T1	295010	0	0	0
T2	0	1	0	0
T4	25042	0	0	0
T8	4935	4	0	0
T9	4367	0	0	0
T19	3145	0	0	0
T26	1373	3	0	0
T27	5838	0	0	0
T28	1606	0	0	0
T29	2214	0	0	0
T30	18037	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563293994	145	0	0
T1	295010	0	0	0
T4	25042	0	0	0
T8	4935	4	0	0
T9	4367	0	0	0
T19	3145	0	0	0
T26	1373	3	0	0
T27	5838	0	0	0
T28	1606	0	0	0
T29	2214	0	0	0
T30	18037	0	0	0
T40	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	598170860	150	0	0
CgEnOn_A	598170860	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	150	0	0
T1	338512	0	0	0
T4	26086	0	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	3277	0	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	10	0	0
T150	0	4	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	147	0	0
T1	338512	0	0	0
T4	26086	0	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	3277	0	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	0	0	0
T40	0	1	0	0
T149	0	10	0	0
T150	0	4	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140507411	154	0	0
CgEnOn_A	140507411	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507411	154	0	0
T1	734740	0	0	0
T2	0	1	0	0
T4	4209	0	0	0
T8	1211	4	0	0
T9	1170	0	0	0
T19	766	0	0	0
T26	337	3	0	0
T27	1515	0	0	0
T28	374	0	0	0
T29	547	0	0	0
T30	4503	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507411	154	0	0
T1	734740	0	0	0
T2	0	1	0	0
T4	4209	0	0	0
T8	1211	4	0	0
T9	1170	0	0	0
T19	766	0	0	0
T26	337	3	0	0
T27	1515	0	0	0
T28	374	0	0	0
T29	547	0	0	0
T30	4503	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	598170860	150	0	0
CgEnOn_A	598170860	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	150	0	0
T1	338512	0	0	0
T4	26086	0	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	3277	0	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	10	0	0
T150	0	4	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	147	0	0
T1	338512	0	0	0
T4	26086	0	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	3277	0	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	0	0	0
T40	0	1	0	0
T149	0	10	0	0
T150	0	4	0	0
T151	0	4	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	3	0	0
T155	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140507411	154	0	0
CgEnOn_A	140507411	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507411	154	0	0
T1	734740	0	0	0
T2	0	1	0	0
T4	4209	0	0	0
T8	1211	4	0	0
T9	1170	0	0	0
T19	766	0	0	0
T26	337	3	0	0
T27	1515	0	0	0
T28	374	0	0	0
T29	547	0	0	0
T30	4503	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507411	154	0	0
T1	734740	0	0	0
T2	0	1	0	0
T4	4209	0	0	0
T8	1211	4	0	0
T9	1170	0	0	0
T19	766	0	0	0
T26	337	3	0	0
T27	1515	0	0	0
T28	374	0	0	0
T29	547	0	0	0
T30	4503	0	0	0
T40	0	1	0	0
T138	0	1	0	0
T149	0	5	0	0
T150	0	4	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T40
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	281016201	8221	0	0
CgEnOn_A	281016201	5919	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281016201	8221	0	0
T1	146950	109	0	0
T4	8416	5	0	0
T7	6135	1	0	0
T8	2421	5	0	0
T9	2343	1	0	0
T26	674	4	0	0
T27	3034	1	0	0
T28	749	1	0	0
T29	1095	9	0	0
T30	9006	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281016201	5919	0	0
T1	146950	98	0	0
T2	0	89	0	0
T4	8416	0	0	0
T8	2421	4	0	0
T9	2343	0	0	0
T12	0	52	0	0
T19	1533	0	0	0
T26	674	3	0	0
T27	3034	0	0	0
T28	749	0	0	0
T29	1095	8	0	0
T30	9006	0	0	0
T40	0	1	0	0
T67	0	3	0	0
T111	0	1	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T40
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140507411	8184	0	0
CgEnOn_A	140507411	5882	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507411	8184	0	0
T1	734740	116	0	0
T4	4209	5	0	0
T7	3067	1	0	0
T8	1211	5	0	0
T9	1170	1	0	0
T26	337	4	0	0
T27	1515	1	0	0
T28	374	1	0	0
T29	547	9	0	0
T30	4503	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140507411	5882	0	0
T1	734740	105	0	0
T2	0	82	0	0
T4	4209	0	0	0
T8	1211	4	0	0
T9	1170	0	0	0
T12	0	50	0	0
T19	766	0	0	0
T26	337	3	0	0
T27	1515	0	0	0
T28	374	0	0	0
T29	547	8	0	0
T30	4503	0	0	0
T40	0	1	0	0
T67	0	3	0	0
T111	0	1	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T40
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	563293994	8231	0	0
CgEnOn_A	563293994	5920	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563293994	8231	0	0
T1	295010	115	0	0
T4	25042	5	0	0
T7	12294	1	0	0
T8	4935	5	0	0
T9	4367	1	0	0
T26	1373	4	0	0
T27	5838	1	0	0
T28	1606	1	0	0
T29	2214	9	0	0
T30	18037	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563293994	5920	0	0
T1	295010	104	0	0
T2	0	80	0	0
T4	25042	0	0	0
T8	4935	4	0	0
T9	4367	0	0	0
T19	3145	0	0	0
T20	0	1	0	0
T26	1373	3	0	0
T27	5838	0	0	0
T28	1606	0	0	0
T29	2214	8	0	0
T30	18037	0	0	0
T40	0	1	0	0
T67	0	3	0	0
T111	0	1	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T41
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	287213419	8195	0	0
CgEnOn_A	287213419	5886	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	287213419	8195	0	0
T1	159032	110	0	0
T4	12522	5	0	0
T7	6147	1	0	0
T8	2703	6	0	0
T9	2183	1	0	0
T26	662	3	0	0
T27	2918	1	0	0
T28	803	1	0	0
T29	1106	8	0	0
T30	9019	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	287213419	5886	0	0
T1	159032	99	0	0
T2	0	79	0	0
T4	12522	0	0	0
T8	2703	5	0	0
T9	2183	0	0	0
T19	1573	0	0	0
T26	662	2	0	0
T27	2918	0	0	0
T28	803	0	0	0
T29	1106	7	0	0
T30	9019	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T67	0	2	0	0
T111	0	1	0	0
T133	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Covered	T7,T30,T1
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	598170860	4555	0	0
CgEnOn_A	598170860	4552	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	4555	0	0
T1	338512	42	0	0
T2	0	69	0	0
T4	26086	0	0	0
T7	12808	5	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	1	0	0
T108	0	5	0	0
T109	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	4552	0	0
T1	338512	42	0	0
T2	0	69	0	0
T4	26086	0	0	0
T7	12808	5	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	1	0	0
T108	0	5	0	0
T109	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Covered	T7,T30,T1
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	598170860	4569	0	0
CgEnOn_A	598170860	4566	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	4569	0	0
T1	338512	38	0	0
T2	0	60	0	0
T4	26086	0	0	0
T7	12808	6	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	2	0	0
T108	0	7	0	0
T109	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	4566	0	0
T1	338512	38	0	0
T2	0	60	0	0
T4	26086	0	0	0
T7	12808	6	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	2	0	0
T108	0	7	0	0
T109	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Covered	T7,T30,T1
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	598170860	4644	0	0
CgEnOn_A	598170860	4641	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	4644	0	0
T1	338512	45	0	0
T2	0	55	0	0
T4	26086	0	0	0
T7	12808	7	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	3	0	0
T108	0	5	0	0
T109	0	12	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	4641	0	0
T1	338512	45	0	0
T2	0	55	0	0
T4	26086	0	0	0
T7	12808	7	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	0	8	0	0
T20	0	1	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	3	0	0
T108	0	5	0	0
T109	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T4
1	0	Covered	T7,T30,T1
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	598170860	4555	0	0
CgEnOn_A	598170860	4552	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	4555	0	0
T1	338512	45	0	0
T2	0	53	0	0
T4	26086	0	0	0
T7	12808	6	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	0	10	0	0
T20	0	1	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	1	0	0
T108	0	6	0	0
T109	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	598170860	4552	0	0
T1	338512	45	0	0
T2	0	53	0	0
T4	26086	0	0	0
T7	12808	6	0	0
T8	5745	5	0	0
T9	4548	0	0	0
T19	0	10	0	0
T20	0	1	0	0
T26	1425	3	0	0
T27	6081	0	0	0
T28	1673	0	0	0
T29	2307	0	0	0
T30	18789	1	0	0
T108	0	6	0	0
T109	0	10	0	0