Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	680912	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4067233

1

T5

12

T4

11

T1

110670

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1166211	1			T5	10		T4	1		T1	29763
values[0x0]	1645006	1			T5	13		T4	10		T1	43531
values[0x1]	1936928	1			T5	8		T4	12		T1	52253

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	369810	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4378335

1

T5

17

T4

15

T1

118475

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17954	1			T1	452		T2	261		T3	678
valid_sources[0x01]	18550	1			T1	502		T2	235		T3	595
valid_sources[0x02]	18032	1			T1	470		T2	251		T3	672
valid_sources[0x03]	17830	1			T1	405		T2	214		T3	669
valid_sources[0x04]	17943	1			T1	438		T2	198		T18	1
valid_sources[0x05]	19019	1			T1	563		T2	237		T18	1
valid_sources[0x06]	18668	1			T1	504		T2	153		T3	711
valid_sources[0x07]	18874	1			T1	485		T2	232		T3	584
valid_sources[0x08]	20395	1			T1	536		T2	232		T3	651
valid_sources[0x09]	17184	1			T1	506		T2	259		T3	661
valid_sources[0x0a]	17424	1			T4	1		T1	541		T2	201
valid_sources[0x0b]	18719	1			T1	359		T2	222		T18	3
valid_sources[0x0c]	17965	1			T4	1		T1	443		T2	237
valid_sources[0x0d]	19073	1			T1	587		T2	237		T3	645
valid_sources[0x0e]	19103	1			T1	507		T2	251		T3	681
valid_sources[0x0f]	18564	1			T1	622		T2	211		T18	1
valid_sources[0x10]	19064	1			T1	481		T2	235		T3	774
valid_sources[0x11]	19142	1			T1	514		T2	293		T3	684
valid_sources[0x12]	18375	1			T1	449		T2	235		T3	652
valid_sources[0x13]	17922	1			T1	400		T2	270		T17	1
valid_sources[0x14]	18813	1			T1	555		T2	242		T3	709
valid_sources[0x15]	19088	1			T1	536		T2	288		T3	726
valid_sources[0x16]	18746	1			T1	531		T2	259		T3	712
valid_sources[0x17]	18330	1			T1	447		T2	247		T3	720
valid_sources[0x18]	20178	1			T4	1		T1	595		T2	258
valid_sources[0x19]	19278	1			T1	578		T2	169		T3	707
valid_sources[0x1a]	18074	1			T1	693		T2	219		T3	713
valid_sources[0x1b]	17995	1			T1	433		T2	226		T3	710
valid_sources[0x1c]	18287	1			T1	530		T2	226		T3	696
valid_sources[0x1d]	18838	1			T1	489		T14	5		T2	247
valid_sources[0x1e]	18094	1			T1	504		T2	260		T3	730
valid_sources[0x1f]	17672	1			T1	425		T2	223		T3	745
valid_sources[0x20]	18581	1			T1	539		T2	232		T3	716
valid_sources[0x21]	17245	1			T1	437		T2	272		T3	683
valid_sources[0x22]	18895	1			T1	387		T2	274		T3	751
valid_sources[0x23]	18735	1			T1	465		T2	295		T3	778
valid_sources[0x24]	17581	1			T1	479		T2	243		T3	668
valid_sources[0x25]	17387	1			T1	395		T2	213		T18	1
valid_sources[0x26]	18620	1			T1	516		T2	275		T3	673
valid_sources[0x27]	18190	1			T1	448		T2	236		T3	601
valid_sources[0x28]	18579	1			T1	439		T2	223		T18	1
valid_sources[0x29]	17300	1			T5	5		T1	436		T2	245
valid_sources[0x2a]	18426	1			T4	1		T1	508		T2	320
valid_sources[0x2b]	17423	1			T1	395		T2	216		T3	619
valid_sources[0x2c]	17888	1			T5	2		T1	526		T2	233
valid_sources[0x2d]	18247	1			T1	514		T2	236		T3	626
valid_sources[0x2e]	19341	1			T1	576		T2	220		T18	1
valid_sources[0x2f]	18570	1			T1	503		T2	265		T3	654
valid_sources[0x30]	17982	1			T1	522		T2	231		T3	620
valid_sources[0x31]	18604	1			T1	556		T16	15		T2	269
valid_sources[0x32]	17925	1			T1	414		T2	154		T18	2
valid_sources[0x33]	18854	1			T1	565		T15	19		T2	305
valid_sources[0x34]	19039	1			T1	449		T2	268		T3	687
valid_sources[0x35]	19257	1			T1	399		T2	265		T3	676
valid_sources[0x36]	18102	1			T5	2		T1	505		T2	224
valid_sources[0x37]	18811	1			T1	471		T2	233		T17	6
valid_sources[0x38]	18427	1			T1	489		T2	266		T3	751
valid_sources[0x39]	17555	1			T1	501		T2	269		T3	617
valid_sources[0x3a]	18348	1			T1	511		T2	251		T3	747
valid_sources[0x3b]	17883	1			T4	3		T1	567		T2	194
valid_sources[0x3c]	18385	1			T1	506		T2	236		T3	674
valid_sources[0x3d]	18646	1			T1	430		T2	233		T3	791
valid_sources[0x3e]	18503	1			T1	412		T2	218		T3	676
valid_sources[0x3f]	18678	1			T1	405		T2	183		T3	685
valid_sources[0x40]	18416	1			T1	445		T2	205		T3	649
valid_sources[0x41]	19608	1			T1	458		T2	214		T3	600
valid_sources[0x42]	17894	1			T1	418		T2	300		T3	585
valid_sources[0x43]	18379	1			T1	536		T2	247		T18	1
valid_sources[0x44]	18721	1			T1	421		T2	277		T3	780
valid_sources[0x45]	19131	1			T1	415		T2	233		T3	640
valid_sources[0x46]	17790	1			T1	516		T2	243		T3	666
valid_sources[0x47]	18223	1			T4	1		T1	498		T2	201
valid_sources[0x48]	18261	1			T1	509		T2	246		T3	676
valid_sources[0x49]	18937	1			T1	492		T2	303		T3	662
valid_sources[0x4a]	18199	1			T4	1		T1	490		T2	191
valid_sources[0x4b]	18996	1			T4	1		T1	554		T2	201
valid_sources[0x4c]	19411	1			T1	491		T2	249		T3	667
valid_sources[0x4d]	18564	1			T1	461		T2	244		T19	1
valid_sources[0x4e]	18733	1			T4	1		T1	365		T2	275
valid_sources[0x4f]	18409	1			T1	476		T2	243		T3	647
valid_sources[0x50]	19309	1			T1	450		T2	226		T3	695
valid_sources[0x51]	19336	1			T1	468		T2	219		T3	663
valid_sources[0x52]	18904	1			T1	561		T2	242		T3	694
valid_sources[0x53]	19648	1			T5	2		T1	539		T2	232
valid_sources[0x54]	18099	1			T1	393		T2	230		T3	650
valid_sources[0x55]	18116	1			T1	563		T2	266		T3	630
valid_sources[0x56]	18240	1			T1	450		T2	239		T3	751
valid_sources[0x57]	18264	1			T4	1		T1	650		T2	210
valid_sources[0x58]	18955	1			T1	402		T2	278		T3	630
valid_sources[0x59]	18671	1			T1	477		T2	241		T3	579
valid_sources[0x5a]	19603	1			T1	459		T2	211		T3	735
valid_sources[0x5b]	19067	1			T1	542		T2	198		T3	712
valid_sources[0x5c]	18955	1			T1	492		T16	6		T2	285
valid_sources[0x5d]	17872	1			T1	423		T2	222		T3	622
valid_sources[0x5e]	19344	1			T1	608		T2	248		T3	715
valid_sources[0x5f]	18124	1			T5	1		T1	592		T2	213
valid_sources[0x60]	19039	1			T5	1		T1	638		T2	264
valid_sources[0x61]	18479	1			T1	486		T2	333		T3	647
valid_sources[0x62]	18805	1			T1	570		T2	255		T3	654
valid_sources[0x63]	17994	1			T1	464		T2	243		T21	41
valid_sources[0x64]	19002	1			T4	1		T1	484		T2	201
valid_sources[0x65]	18721	1			T1	521		T2	205		T3	641
valid_sources[0x66]	19122	1			T1	439		T2	222		T3	634
valid_sources[0x67]	20194	1			T1	445		T2	189		T3	688
valid_sources[0x68]	18213	1			T1	549		T2	272		T3	664
valid_sources[0x69]	18810	1			T1	485		T2	249		T3	702
valid_sources[0x6a]	17780	1			T5	3		T4	1		T1	419
valid_sources[0x6b]	18577	1			T4	1		T1	523		T2	208
valid_sources[0x6c]	17547	1			T1	408		T2	241		T3	658
valid_sources[0x6d]	18784	1			T1	465		T2	238		T3	718
valid_sources[0x6e]	18596	1			T1	427		T2	254		T3	640
valid_sources[0x6f]	18148	1			T1	409		T2	235		T3	754
valid_sources[0x70]	18352	1			T1	504		T2	216		T3	661
valid_sources[0x71]	18260	1			T1	488		T2	238		T3	659
valid_sources[0x72]	18352	1			T1	463		T2	200		T18	1
valid_sources[0x73]	17844	1			T4	1		T1	424		T2	203
valid_sources[0x74]	18948	1			T1	416		T2	318		T3	687
valid_sources[0x75]	19105	1			T1	405		T2	243		T3	671
valid_sources[0x76]	18190	1			T1	447		T2	208		T3	706
valid_sources[0x77]	17552	1			T1	541		T2	248		T3	575
valid_sources[0x78]	17862	1			T1	520		T16	8		T2	264
valid_sources[0x79]	18075	1			T1	414		T2	158		T3	590
valid_sources[0x7a]	19126	1			T1	546		T16	5		T2	220
valid_sources[0x7b]	18855	1			T1	505		T2	214		T3	690
valid_sources[0x7c]	18463	1			T1	504		T2	275		T3	626
valid_sources[0x7d]	18788	1			T1	425		T2	219		T32	140
valid_sources[0x7e]	18234	1			T1	562		T2	257		T3	706
valid_sources[0x7f]	17608	1			T1	545		T2	248		T3	685
valid_sources[0x80]	18137	1			T1	489		T2	212		T3	637

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1026639

1

T5

4

T1

27431

T16

12

values[0x0]

all_enables

biggest_size

1544768

1

T5

6

T4

7

T1

41872

values[0x1]

all_enables

biggest_size

1495826

1

T5

2

T4

4

T1

41367