Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T2
0	1	Covered	T1,T15,T2
1	0	Covered	T5,T4,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T20,T33,T34
1	1	Covered	T5,T4,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1207219086	14787	0	0
GateOpen_A	1207219086	21594	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1207219086	14787	0	0
T1	1059008	126	0	0
T2	1854402	188	0	0
T3	0	491	0	0
T8	0	31	0	0
T14	3098	0	0	0
T15	9371	6	0	0
T16	5656	0	0	0
T17	3919	0	0	0
T18	4832	34	0	0
T19	3604	0	0	0
T20	9286	13	0	0
T21	4634	50	0	0
T33	0	13	0	0
T58	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1207219086	21594	0	0
T1	1059008	150	0	0
T2	1854402	200	0	0
T4	21446	4	0	0
T5	12987	4	0	0
T14	3098	4	0	0
T15	9371	6	0	0
T16	5656	0	0	0
T17	3919	0	0	0
T18	4832	34	0	0
T19	3604	4	0	0
T20	0	17	0	0
T21	0	54	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T2
0	1	Covered	T1,T15,T2
1	0	Covered	T5,T4,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T20,T33,T34
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	133273251	3530	0	0
GateOpen_A	133273251	5230	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133273251	3530	0	0
T1	116603	31	0	0
T2	204804	48	0	0
T3	0	125	0	0
T8	0	7	0	0
T14	327	0	0	0
T15	1028	1	0	0
T16	678	0	0	0
T17	428	0	0	0
T18	526	6	0	0
T19	394	0	0	0
T20	1020	3	0	0
T21	504	11	0	0
T33	0	3	0	0
T58	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133273251	5230	0	0
T1	116603	37	0	0
T2	204804	51	0	0
T4	2057	1	0	0
T5	1952	1	0	0
T14	327	1	0	0
T15	1028	1	0	0
T16	678	0	0	0
T17	428	0	0	0
T18	526	6	0	0
T19	394	1	0	0
T20	0	4	0	0
T21	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T2
0	1	Covered	T1,T15,T2
1	0	Covered	T5,T4,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T20,T33,T34
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	266547337	3729	0	0
GateOpen_A	266547337	5429	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266547337	3729	0	0
T1	233209	31	0	0
T2	409609	49	0	0
T3	0	122	0	0
T8	0	8	0	0
T14	653	0	0	0
T15	2056	1	0	0
T16	1357	0	0	0
T17	859	0	0	0
T18	1052	9	0	0
T19	788	0	0	0
T20	2039	3	0	0
T21	1008	13	0	0
T33	0	3	0	0
T58	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266547337	5429	0	0
T1	233209	37	0	0
T2	409609	52	0	0
T4	4113	1	0	0
T5	3903	1	0	0
T14	653	1	0	0
T15	2056	1	0	0
T16	1357	0	0	0
T17	859	0	0	0
T18	1052	9	0	0
T19	788	1	0	0
T20	0	4	0	0
T21	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T2
0	1	Covered	T1,T15,T2
1	0	Covered	T5,T4,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T20,T33,T34
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	534663301	3778	0	0
GateOpen_A	534663301	5480	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534663301	3778	0	0
T1	467990	32	0	0
T2	818966	44	0	0
T3	0	123	0	0
T8	0	8	0	0
T14	1412	0	0	0
T15	4191	2	0	0
T16	2414	0	0	0
T17	1755	0	0	0
T18	2169	9	0	0
T19	1614	0	0	0
T20	4116	3	0	0
T21	2081	13	0	0
T33	0	3	0	0
T58	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534663301	5480	0	0
T1	467990	38	0	0
T2	818966	47	0	0
T4	8264	1	0	0
T5	4755	1	0	0
T14	1412	1	0	0
T15	4191	2	0	0
T16	2414	0	0	0
T17	1755	0	0	0
T18	2169	9	0	0
T19	1614	1	0	0
T20	0	4	0	0
T21	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T2
0	1	Covered	T1,T15,T2
1	0	Covered	T5,T4,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T2
1	0	Covered	T20,T33,T34
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	272735197	3750	0	0
GateOpen_A	272735197	5455	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272735197	3750	0	0
T1	241206	32	0	0
T2	421023	47	0	0
T3	0	121	0	0
T8	0	8	0	0
T14	706	0	0	0
T15	2096	2	0	0
T16	1207	0	0	0
T17	877	0	0	0
T18	1085	10	0	0
T19	808	0	0	0
T20	2111	4	0	0
T21	1041	13	0	0
T33	0	4	0	0
T58	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272735197	5455	0	0
T1	241206	38	0	0
T2	421023	50	0	0
T4	7012	1	0	0
T5	2377	1	0	0
T14	706	1	0	0
T15	2096	2	0	0
T16	1207	0	0	0
T17	877	0	0	0
T18	1085	10	0	0
T19	808	1	0	0
T20	0	5	0	0
T21	0	14	0	0