Module Definition
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Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 845452750 77422 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 845452750 77422 0 0
T1 2475305 1714 0 0
T2 1167535 206 0 0
T3 0 2150 0 0
T7 0 61 0 0
T8 0 203 0 0
T9 0 1446 0 0
T10 0 40 0 0
T11 0 190 0 0
T12 0 198 0 0
T13 0 501 0 0
T14 7205 0 0 0
T15 5020 0 0 0
T16 12570 0 0 0
T17 9050 0 0 0
T18 5425 0 0 0
T19 7985 0 0 0
T20 5785 0 0 0
T21 10620 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 169090550 11578 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169090550 11578 0 0
T1 495061 252 0 0
T2 233507 35 0 0
T3 0 405 0 0
T7 0 9 0 0
T8 0 26 0 0
T9 0 214 0 0
T10 0 6 0 0
T11 0 24 0 0
T12 0 26 0 0
T13 0 65 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T21 2124 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 169090550 15499 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169090550 15499 0 0
T1 495061 349 0 0
T2 233507 41 0 0
T3 0 409 0 0
T7 0 12 0 0
T8 0 41 0 0
T9 0 288 0 0
T10 0 8 0 0
T11 0 36 0 0
T12 0 39 0 0
T13 0 100 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T21 2124 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 169090550 23438 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169090550 23438 0 0
T1 495061 562 0 0
T2 233507 57 0 0
T3 0 518 0 0
T7 0 19 0 0
T8 0 66 0 0
T9 0 446 0 0
T10 0 12 0 0
T11 0 65 0 0
T12 0 67 0 0
T13 0 162 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T21 2124 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 169090550 11367 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169090550 11367 0 0
T1 495061 212 0 0
T2 233507 31 0 0
T3 0 405 0 0
T7 0 9 0 0
T8 0 29 0 0
T9 0 209 0 0
T10 0 6 0 0
T11 0 27 0 0
T12 0 26 0 0
T13 0 72 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T21 2124 0 0 0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CtrlEnOn_A 169090550 15540 0 0


CtrlEnOn_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169090550 15540 0 0
T1 495061 339 0 0
T2 233507 42 0 0
T3 0 413 0 0
T7 0 12 0 0
T8 0 41 0 0
T9 0 289 0 0
T10 0 8 0 0
T11 0 38 0 0
T12 0 40 0 0
T13 0 102 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T21 2124 0 0 0

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