Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T4,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	169090550	166269784	0	0
AllClkBypReqTrue_A	169090550	133709	0	0
IoClkBypReqFalse_A	169090550	166183530	0	2412
IoClkBypReqTrue_A	169090550	215151	0	0
LcClkBypAckFalse_A	169090550	166277895	0	0
LcClkBypAckTrue_A	169090550	125598	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166269784	0	0
T1	495061	491412	0	0
T2	233507	233286	0	0
T4	7159	7089	0	0
T5	1287	1217	0	0
T14	1441	1205	0	0
T15	1004	971	0	0
T16	2514	1973	0	0
T17	1810	1587	0	0
T18	1085	1010	0	0
T19	1597	1422	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	133709	0	0
T1	495061	2328	0	0
T2	233507	673	0	0
T3	0	1595	0	0
T4	7159	0	0	0
T5	1287	40	0	0
T8	0	519	0	0
T9	0	1484	0	0
T14	1441	0	0	0
T15	1004	0	0	0
T16	2514	385	0	0
T17	1810	26	0	0
T18	1085	0	0	0
T19	1597	0	0	0
T80	0	26	0	0
T81	0	53	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166183530	0	2412
T1	495061	491266	0	3
T2	233507	233220	0	3
T4	7159	7087	0	3
T5	1287	1255	0	3
T14	1441	1203	0	3
T15	1004	969	0	3
T16	2514	1892	0	3
T17	1810	1534	0	3
T18	1085	1008	0	3
T19	1597	1420	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	215151	0	0
T1	495061	3763	0	0
T2	233507	1315	0	0
T3	0	2878	0	0
T8	0	698	0	0
T9	0	2154	0	0
T14	1441	0	0	0
T15	1004	0	0	0
T16	2514	464	0	0
T17	1810	77	0	0
T18	1085	0	0	0
T19	1597	0	0	0
T20	1157	0	0	0
T21	2124	0	0	0
T80	0	50	0	0
T81	0	130	0	0
T120	0	32	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	166277895	0	0
T1	495061	491453	0	0
T2	233507	233290	0	0
T4	7159	7089	0	0
T5	1287	1257	0	0
T14	1441	1205	0	0
T15	1004	971	0	0
T16	2514	2116	0	0
T17	1810	1562	0	0
T18	1085	1010	0	0
T19	1597	1422	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	125598	0	0
T1	495061	1922	0	0
T2	233507	627	0	0
T3	0	1662	0	0
T8	0	472	0	0
T9	0	1454	0	0
T14	1441	0	0	0
T15	1004	0	0	0
T16	2514	242	0	0
T17	1810	51	0	0
T18	1085	0	0	0
T19	1597	0	0	0
T20	1157	0	0	0
T21	2124	0	0	0
T80	0	44	0	0
T81	0	42	0	0
T120	0	29	0	0