Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16823	0	0
TransStop_A	2147483647	8527	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16823	0	0
T1	2014820	161	0	0
T2	3510868	158	0	0
T3	0	415	0	0
T8	0	35	0	0
T9	0	240	0	0
T11	0	179	0	0
T14	5884	0	0	0
T15	17464	0	0	0
T16	10060	0	0	0
T17	7312	0	0	0
T18	9036	0	0	0
T19	6724	2	0	0
T20	17940	0	0	0
T21	8668	0	0	0
T32	0	35	0	0
T58	0	4	0	0
T60	0	37	0	0
T121	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8527	0	0
T1	2014820	79	0	0
T2	3510868	87	0	0
T3	0	241	0	0
T8	0	18	0	0
T9	0	103	0	0
T11	0	104	0	0
T14	5884	0	0	0
T15	17464	0	0	0
T16	10060	0	0	0
T17	7312	0	0	0
T18	9036	0	0	0
T19	6724	2	0	0
T20	17940	0	0	0
T21	8668	0	0	0
T32	0	21	0	0
T58	0	4	0	0
T60	0	11	0	0
T121	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	567873598	4287	0	0
TransStop_A	567873598	2195	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873598	4287	0	0
T1	503705	39	0	0
T2	877717	36	0	0
T3	0	100	0	0
T8	0	7	0	0
T9	0	68	0	0
T11	0	45	0	0
T14	1471	0	0	0
T15	4366	0	0	0
T16	2515	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	0	0	0
T20	4485	0	0	0
T21	2167	0	0	0
T32	0	7	0	0
T58	0	1	0	0
T60	0	11	0	0
T121	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873598	2195	0	0
T1	503705	17	0	0
T2	877717	18	0	0
T3	0	57	0	0
T8	0	4	0	0
T9	0	31	0	0
T11	0	27	0	0
T14	1471	0	0	0
T15	4366	0	0	0
T16	2515	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	0	0	0
T20	4485	0	0	0
T21	2167	0	0	0
T32	0	5	0	0
T58	0	1	0	0
T60	0	3	0	0
T121	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	567873598	4202	0	0
TransStop_A	567873598	2134	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873598	4202	0	0
T1	503705	40	0	0
T2	877717	39	0	0
T3	0	106	0	0
T8	0	10	0	0
T9	0	53	0	0
T11	0	44	0	0
T14	1471	0	0	0
T15	4366	0	0	0
T16	2515	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	1	0	0
T20	4485	0	0	0
T21	2167	0	0	0
T32	0	8	0	0
T58	0	1	0	0
T60	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873598	2134	0	0
T1	503705	21	0	0
T2	877717	22	0	0
T3	0	63	0	0
T8	0	6	0	0
T9	0	24	0	0
T11	0	26	0	0
T14	1471	0	0	0
T15	4366	0	0	0
T16	2515	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	1	0	0
T20	4485	0	0	0
T21	2167	0	0	0
T32	0	5	0	0
T58	0	1	0	0
T60	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	567873598	4190	0	0
TransStop_A	567873598	2139	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873598	4190	0	0
T1	503705	37	0	0
T2	877717	36	0	0
T3	0	103	0	0
T8	0	11	0	0
T9	0	58	0	0
T11	0	40	0	0
T14	1471	0	0	0
T15	4366	0	0	0
T16	2515	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	1	0	0
T20	4485	0	0	0
T21	2167	0	0	0
T32	0	9	0	0
T58	0	1	0	0
T60	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873598	2139	0	0
T1	503705	19	0	0
T2	877717	22	0	0
T3	0	59	0	0
T8	0	6	0	0
T9	0	26	0	0
T11	0	19	0	0
T14	1471	0	0	0
T15	4366	0	0	0
T16	2515	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	1	0	0
T20	4485	0	0	0
T21	2167	0	0	0
T32	0	5	0	0
T58	0	1	0	0
T60	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	567873598	4144	0	0
TransStop_A	567873598	2059	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873598	4144	0	0
T1	503705	45	0	0
T2	877717	47	0	0
T3	0	106	0	0
T8	0	7	0	0
T9	0	61	0	0
T11	0	50	0	0
T14	1471	0	0	0
T15	4366	0	0	0
T16	2515	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	0	0	0
T20	4485	0	0	0
T21	2167	0	0	0
T32	0	11	0	0
T58	0	1	0	0
T60	0	10	0	0
T121	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873598	2059	0	0
T1	503705	22	0	0
T2	877717	25	0	0
T3	0	62	0	0
T8	0	2	0	0
T9	0	22	0	0
T11	0	32	0	0
T14	1471	0	0	0
T15	4366	0	0	0
T16	2515	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	0	0	0
T20	4485	0	0	0
T21	2167	0	0	0
T32	0	6	0	0
T58	0	1	0	0
T60	0	3	0	0
T121	0	3	0	0