Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	169090550	18530587	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	18530587	0	57
T1	495061	469086	0	0
T2	233507	15052	0	0
T3	0	517307	0	0
T7	0	6635	0	1
T8	0	25262	0	0
T9	0	133926	0	0
T10	0	3991	0	1
T11	0	26173	0	0
T12	0	24748	0	1
T13	0	61361	0	0
T14	1441	0	0	0
T15	1004	0	0	0
T16	2514	0	0	0
T17	1810	0	0	0
T18	1085	0	0	0
T19	1597	0	0	0
T20	1157	0	0	0
T21	2124	0	0	0
T55	0	0	0	1
T122	0	0	0	1
T123	0	0	0	1
T124	0	0	0	1
T125	0	0	0	1
T126	0	0	0	1
T127	0	0	0	1