Module Definition
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Module : clkmgr_lost_calib_regwen_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if 100.00 100.00



Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RegwenOff_A 169090550 18530587 0 57


RegwenOff_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 169090550 18530587 0 57
T1 495061 469086 0 0
T2 233507 15052 0 0
T3 0 517307 0 0
T7 0 6635 0 1
T8 0 25262 0 0
T9 0 133926 0 0
T10 0 3991 0 1
T11 0 26173 0 0
T12 0 24748 0 1
T13 0 61361 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T21 2124 0 0 0
T55 0 0 0 1
T122 0 0 0 1
T123 0 0 0 1
T124 0 0 0 1
T125 0 0 0 1
T126 0 0 0 1
T127 0 0 0 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%