Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	170057103	5993672	0	0
clk_enables_rd_A	170057103	35591	0	0
clk_hints_rd_A	170057103	31573	0	0
extclk_ctrl_rd_A	170057103	40632	0	0
extclk_ctrl_regwen_rd_A	170057103	29339	0	0
jitter_enable_rd_A	170057103	42983	0	0
jitter_regwen_rd_A	170057103	33312	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170057103	5993672	0	0
T1	495061	171116	0	0
T2	233507	85211	0	0
T3	0	222179	0	0
T9	0	92488	0	0
T14	1441	0	0	0
T15	1004	0	0	0
T16	2514	0	0	0
T17	1810	0	0	0
T18	1085	0	0	0
T19	1597	0	0	0
T20	1157	0	0	0
T21	2124	0	0	0
T23	0	180871	0	0
T74	0	24995	0	0
T75	0	158325	0	0
T76	0	55905	0	0
T77	0	133015	0	0
T78	0	57319	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170057103	35591	0	0
T22	134697	8	0	0
T23	364371	0	0	0
T24	118344	0	0	0
T74	499927	0	0	0
T76	0	2180	0	0
T98	0	5	0	0
T139	0	6	0	0
T140	0	10	0	0
T141	0	2866	0	0
T142	0	1	0	0
T143	0	13	0	0
T144	0	2931	0	0
T145	0	2718	0	0
T146	2035	0	0	0
T147	2135	0	0	0
T148	1802	0	0	0
T149	1994	0	0	0
T150	1645	0	0	0
T151	1397	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170057103	31573	0	0
T22	134697	2	0	0
T23	364371	0	0	0
T24	118344	0	0	0
T74	499927	0	0	0
T76	0	1742	0	0
T98	0	2	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2253	0	0
T142	0	18	0	0
T143	0	14	0	0
T144	0	2854	0	0
T146	2035	0	0	0
T147	2135	0	0	0
T148	1802	0	0	0
T149	1994	0	0	0
T150	1645	0	0	0
T151	1397	0	0	0
T152	0	7	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170057103	40632	0	0
T2	233507	0	0	0
T16	2514	24	0	0
T17	1810	0	0	0
T18	1085	0	0	0
T19	1597	0	0	0
T20	1157	0	0	0
T21	2124	0	0	0
T22	0	142	0	0
T32	3083	0	0	0
T76	0	2890	0	0
T79	944	0	0	0
T80	1314	0	0	0
T92	0	18	0	0
T93	0	54	0	0
T96	0	48	0	0
T146	0	74	0	0
T153	0	49	0	0
T154	0	10	0	0
T155	0	50	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170057103	29339	0	0
T50	0	52	0	0
T76	190390	1785	0	0
T96	40906	22	0	0
T97	2225	0	0	0
T98	2149	0	0	0
T141	0	2382	0	0
T144	0	2599	0	0
T156	0	34	0	0
T157	0	15	0	0
T158	0	10	0	0
T159	0	19	0	0
T160	0	30	0	0
T161	1163	0	0	0
T162	1677	0	0	0
T163	1991	0	0	0
T164	959	0	0	0
T165	2292	0	0	0
T166	1215	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170057103	42983	0	0
T22	134697	91	0	0
T23	364371	0	0	0
T24	118344	0	0	0
T74	499927	0	0	0
T76	0	2259	0	0
T98	0	135	0	0
T139	0	115	0	0
T140	0	224	0	0
T141	0	3815	0	0
T142	0	208	0	0
T143	0	411	0	0
T146	2035	0	0	0
T147	2135	0	0	0
T148	1802	0	0	0
T149	1994	0	0	0
T150	1645	0	0	0
T151	1397	0	0	0
T152	0	115	0	0
T167	0	64	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170057103	33312	0	0
T76	190390	2047	0	0
T77	268952	0	0	0
T139	2402	0	0	0
T141	0	2605	0	0
T144	0	3227	0	0
T145	0	2599	0	0
T162	1677	0	0	0
T163	1991	0	0	0
T164	959	0	0	0
T165	2292	0	0	0
T166	1215	0	0	0
T168	0	708	0	0
T169	0	3572	0	0
T170	0	1234	0	0
T171	0	5862	0	0
T172	0	4991	0	0
T173	0	4151	0	0
T174	2058	0	0	0
T175	1704	0	0	0