Module Definition
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Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.36 97.74 86.76 94.92 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 87.44 96.94 84.78 93.02 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1700571030 1451615 0 0
DstReqKnown_A 2147483647 2147483647 0 0
SrcAckBusyChk_A 1700571030 290025 0 0
SrcBusyKnown_A 1700571030 1672661960 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1700571030 1451615 0 0
T1 4950610 35096 0 0
T2 2335070 15045 0 0
T3 0 26804 0 0
T4 71590 102 0 0
T7 0 1256 0 0
T8 0 7123 0 0
T9 0 18876 0 0
T10 0 396 0 0
T14 14410 0 0 0
T15 10040 0 0 0
T16 25140 0 0 0
T17 18100 0 0 0
T18 10850 0 0 0
T19 15970 0 0 0
T20 11570 0 0 0
T25 0 2175 0 0
T26 0 2800 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 3125424 3105684 0 0
T2 5464238 5461976 0 0
T4 72106 71278 0 0
T5 35874 35228 0 0
T14 9136 7776 0 0
T15 27470 26702 0 0
T16 16338 15460 0 0
T17 11492 10404 0 0
T18 14178 13302 0 0
T19 10568 9468 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1700571030 290025 0 0
T1 4950610 4150 0 0
T2 2335070 4240 0 0
T3 0 10040 0 0
T4 71590 20 0 0
T7 0 240 0 0
T8 0 840 0 0
T9 0 3665 0 0
T10 0 120 0 0
T14 14410 0 0 0
T15 10040 0 0 0
T16 25140 0 0 0
T17 18100 0 0 0
T18 10850 0 0 0
T19 15970 0 0 0
T20 11570 0 0 0
T25 0 252 0 0
T26 0 360 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1700571030 1672661960 0 0
T1 4950610 4916460 0 0
T2 2335070 2333540 0 0
T4 71590 70900 0 0
T5 12870 12580 0 0
T14 14410 12060 0 0
T15 10040 9720 0 0
T16 25140 23590 0 0
T17 18100 16140 0 0
T18 10850 10110 0 0
T19 15970 14230 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 90927 0 0
DstReqKnown_A 537296508 532646324 0 0
SrcAckBusyChk_A 170057103 25944 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 90927 0 0
T1 495061 2481 0 0
T2 233507 1112 0 0
T3 0 2504 0 0
T4 7159 7 0 0
T7 0 88 0 0
T8 0 437 0 0
T9 0 1307 0 0
T10 0 29 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 110 0 0
T26 0 176 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 537296508 532646324 0 0
T1 467989 464575 0 0
T2 818966 818802 0 0
T4 8263 8129 0 0
T5 4754 4647 0 0
T14 1412 1181 0 0
T15 4191 4056 0 0
T16 2414 2266 0 0
T17 1755 1565 0 0
T18 2168 2020 0 0
T19 1614 1438 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 25944 0 0
T1 495061 410 0 0
T2 233507 421 0 0
T3 0 999 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 364 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 18 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 128473 0 0
DstReqKnown_A 267815403 266632624 0 0
SrcAckBusyChk_A 170057103 25944 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 128473 0 0
T1 495061 3500 0 0
T2 233507 1536 0 0
T3 0 2504 0 0
T4 7159 10 0 0
T7 0 125 0 0
T8 0 696 0 0
T9 0 1882 0 0
T10 0 42 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 158 0 0
T26 0 280 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 267815403 266632624 0 0
T1 233209 232415 0 0
T2 409609 409548 0 0
T4 4113 4065 0 0
T5 3902 3868 0 0
T14 653 591 0 0
T15 2056 2028 0 0
T16 1356 1315 0 0
T17 859 818 0 0
T18 1051 1010 0 0
T19 788 719 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 25944 0 0
T1 495061 410 0 0
T2 233507 421 0 0
T3 0 999 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 364 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 18 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 205333 0 0
DstReqKnown_A 133907073 133315794 0 0
SrcAckBusyChk_A 170057103 25944 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 205333 0 0
T1 495061 6001 0 0
T2 233507 2223 0 0
T3 0 3310 0 0
T4 7159 18 0 0
T7 0 202 0 0
T8 0 1215 0 0
T9 0 3023 0 0
T10 0 60 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 265 0 0
T26 0 484 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133907073 133315794 0 0
T1 116603 116206 0 0
T2 204804 204773 0 0
T4 2056 2032 0 0
T5 1951 1934 0 0
T14 326 295 0 0
T15 1028 1014 0 0
T16 678 657 0 0
T17 427 406 0 0
T18 526 505 0 0
T19 394 360 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 25944 0 0
T1 495061 410 0 0
T2 233507 421 0 0
T3 0 999 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 364 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 18 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 89035 0 0
DstReqKnown_A 570616641 565693952 0 0
SrcAckBusyChk_A 170057103 25944 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 89035 0 0
T1 495061 2023 0 0
T2 233507 1079 0 0
T3 0 2504 0 0
T4 7159 7 0 0
T7 0 85 0 0
T8 0 507 0 0
T9 0 1282 0 0
T10 0 29 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 90 0 0
T26 0 171 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 570616641 565693952 0 0
T1 503705 500148 0 0
T2 877717 877126 0 0
T4 14609 14468 0 0
T5 4953 4841 0 0
T14 1471 1230 0 0
T15 4365 4225 0 0
T16 2514 2359 0 0
T17 1828 1630 0 0
T18 2259 2105 0 0
T19 1681 1498 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 25944 0 0
T1 495061 410 0 0
T2 233507 421 0 0
T3 0 999 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 364 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 18 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 126387 0 0
DstReqKnown_A 274051634 271682590 0 0
SrcAckBusyChk_A 170057103 25445 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 126387 0 0
T1 495061 3317 0 0
T2 233507 1526 0 0
T3 0 2504 0 0
T4 7159 11 0 0
T7 0 126 0 0
T8 0 698 0 0
T9 0 1892 0 0
T10 0 41 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 86 0 0
T26 0 280 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 274051634 271682590 0 0
T1 241206 239498 0 0
T2 421023 420739 0 0
T4 7012 6945 0 0
T5 2377 2324 0 0
T14 706 591 0 0
T15 2095 2028 0 0
T16 1207 1133 0 0
T17 877 783 0 0
T18 1085 1011 0 0
T19 807 719 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 25445 0 0
T1 495061 410 0 0
T2 233507 421 0 0
T3 0 999 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 364 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 9 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 113965 0 0
DstReqKnown_A 537296508 532646324 0 0
SrcAckBusyChk_A 170057103 32149 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 113965 0 0
T1 495061 2540 0 0
T2 233507 1136 0 0
T3 0 2527 0 0
T4 7159 7 0 0
T7 0 88 0 0
T8 0 436 0 0
T9 0 1325 0 0
T10 0 29 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 214 0 0
T26 0 178 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 537296508 532646324 0 0
T1 467989 464575 0 0
T2 818966 818802 0 0
T4 8263 8129 0 0
T5 4754 4647 0 0
T14 1412 1181 0 0
T15 4191 4056 0 0
T16 2414 2266 0 0
T17 1755 1565 0 0
T18 2168 2020 0 0
T19 1614 1438 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 32149 0 0
T1 495061 420 0 0
T2 233507 427 0 0
T3 0 1009 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 369 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 36 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 162707 0 0
DstReqKnown_A 267815403 266632624 0 0
SrcAckBusyChk_A 170057103 32301 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 162707 0 0
T1 495061 3603 0 0
T2 233507 1550 0 0
T3 0 2527 0 0
T4 7159 10 0 0
T7 0 127 0 0
T8 0 702 0 0
T9 0 1909 0 0
T10 0 40 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 301 0 0
T26 0 284 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 267815403 266632624 0 0
T1 233209 232415 0 0
T2 409609 409548 0 0
T4 4113 4065 0 0
T5 3902 3868 0 0
T14 653 591 0 0
T15 2056 2028 0 0
T16 1356 1315 0 0
T17 859 818 0 0
T18 1051 1010 0 0
T19 788 719 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 32301 0 0
T1 495061 420 0 0
T2 233507 427 0 0
T3 0 1009 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 369 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 36 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 261381 0 0
DstReqKnown_A 133907073 133315794 0 0
SrcAckBusyChk_A 170057103 32251 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 261381 0 0
T1 495061 6153 0 0
T2 233507 2235 0 0
T3 0 3370 0 0
T4 7159 15 0 0
T7 0 203 0 0
T8 0 1233 0 0
T9 0 3044 0 0
T10 0 58 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 533 0 0
T26 0 497 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 133907073 133315794 0 0
T1 116603 116206 0 0
T2 204804 204773 0 0
T4 2056 2032 0 0
T5 1951 1934 0 0
T14 326 295 0 0
T15 1028 1014 0 0
T16 678 657 0 0
T17 427 406 0 0
T18 526 505 0 0
T19 394 360 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 32251 0 0
T1 495061 420 0 0
T2 233507 427 0 0
T3 0 1009 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 369 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 36 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 111813 0 0
DstReqKnown_A 570616641 565693952 0 0
SrcAckBusyChk_A 170057103 32224 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 111813 0 0
T1 495061 2087 0 0
T2 233507 1092 0 0
T3 0 2527 0 0
T4 7159 7 0 0
T7 0 86 0 0
T8 0 506 0 0
T9 0 1303 0 0
T10 0 28 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 177 0 0
T26 0 173 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 570616641 565693952 0 0
T1 503705 500148 0 0
T2 877717 877126 0 0
T4 14609 14468 0 0
T5 4953 4841 0 0
T14 1471 1230 0 0
T15 4365 4225 0 0
T16 2514 2359 0 0
T17 1828 1630 0 0
T18 2259 2105 0 0
T19 1681 1498 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 32224 0 0
T1 495061 420 0 0
T2 233507 427 0 0
T3 0 1009 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 369 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 36 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT5,T4,T1
01CoveredT1,T2,T3
10CoveredT4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT5,T4,T1
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT5,T4,T1
01Unreachable
10CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT4,T1,T2
11CoveredT4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT5,T4,T1
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T4,T1
0 1 - Covered T4,T1,T2
0 0 1 Covered T4,T1,T2
0 0 0 Covered T5,T4,T1


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 170057103 161594 0 0
DstReqKnown_A 274051634 271682590 0 0
SrcAckBusyChk_A 170057103 31879 0 0
SrcBusyKnown_A 170057103 167266196 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 161594 0 0
T1 495061 3391 0 0
T2 233507 1556 0 0
T3 0 2527 0 0
T4 7159 10 0 0
T7 0 126 0 0
T8 0 693 0 0
T9 0 1909 0 0
T10 0 40 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 241 0 0
T26 0 277 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 274051634 271682590 0 0
T1 241206 239498 0 0
T2 421023 420739 0 0
T4 7012 6945 0 0
T5 2377 2324 0 0
T14 706 591 0 0
T15 2095 2028 0 0
T16 1207 1133 0 0
T17 877 783 0 0
T18 1085 1011 0 0
T19 807 719 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 31879 0 0
T1 495061 420 0 0
T2 233507 427 0 0
T3 0 1009 0 0
T4 7159 2 0 0
T7 0 24 0 0
T8 0 84 0 0
T9 0 369 0 0
T10 0 12 0 0
T14 1441 0 0 0
T15 1004 0 0 0
T16 2514 0 0 0
T17 1810 0 0 0
T18 1085 0 0 0
T19 1597 0 0 0
T20 1157 0 0 0
T25 0 27 0 0
T26 0 36 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170057103 167266196 0 0
T1 495061 491646 0 0
T2 233507 233354 0 0
T4 7159 7090 0 0
T5 1287 1258 0 0
T14 1441 1206 0 0
T15 1004 972 0 0
T16 2514 2359 0 0
T17 1810 1614 0 0
T18 1085 1011 0 0
T19 1597 1423 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%