Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T15
1	0	Covered	T5,T1,T16
1	1	Covered	T5,T1,T16

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	534663301	4673	0	0
g_div2.Div2Whole_A	534663301	5526	0	0
g_div4.Div4Stepped_A	266547337	4583	0	0
g_div4.Div4Whole_A	266547337	5232	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534663301	4673	0	0
T1	467990	62	0	0
T2	818966	26	0	0
T3	0	89	0	0
T4	8264	0	0	0
T5	4755	2	0	0
T8	0	17	0	0
T9	0	49	0	0
T14	1412	0	0	0
T15	4191	0	0	0
T16	2414	7	0	0
T17	1755	1	0	0
T18	2169	0	0	0
T19	1614	0	0	0
T80	0	2	0	0
T81	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534663301	5526	0	0
T1	467990	86	0	0
T2	818966	28	0	0
T3	0	92	0	0
T4	8264	0	0	0
T5	4755	1	0	0
T8	0	22	0	0
T9	0	55	0	0
T14	1412	0	0	0
T15	4191	0	0	0
T16	2414	8	0	0
T17	1755	4	0	0
T18	2169	0	0	0
T19	1614	0	0	0
T80	0	2	0	0
T81	0	3	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266547337	4583	0	0
T1	233209	62	0	0
T2	409609	26	0	0
T3	0	89	0	0
T4	4113	0	0	0
T5	3903	1	0	0
T8	0	16	0	0
T9	0	49	0	0
T14	653	0	0	0
T15	2056	0	0	0
T16	1357	7	0	0
T17	859	1	0	0
T18	1052	0	0	0
T19	788	0	0	0
T80	0	2	0	0
T81	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266547337	5232	0	0
T1	233209	76	0	0
T2	409609	28	0	0
T3	0	91	0	0
T4	4113	0	0	0
T5	3903	1	0	0
T8	0	12	0	0
T9	0	55	0	0
T14	653	0	0	0
T15	2056	0	0	0
T16	1357	8	0	0
T17	859	4	0	0
T18	1052	0	0	0
T19	788	0	0	0
T80	0	2	0	0
T81	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T15
1	0	Covered	T5,T1,T16
1	1	Covered	T5,T1,T16

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	534663301	4673	0	0
g_div2.Div2Whole_A	534663301	5526	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534663301	4673	0	0
T1	467990	62	0	0
T2	818966	26	0	0
T3	0	89	0	0
T4	8264	0	0	0
T5	4755	2	0	0
T8	0	17	0	0
T9	0	49	0	0
T14	1412	0	0	0
T15	4191	0	0	0
T16	2414	7	0	0
T17	1755	1	0	0
T18	2169	0	0	0
T19	1614	0	0	0
T80	0	2	0	0
T81	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534663301	5526	0	0
T1	467990	86	0	0
T2	818966	28	0	0
T3	0	92	0	0
T4	8264	0	0	0
T5	4755	1	0	0
T8	0	22	0	0
T9	0	55	0	0
T14	1412	0	0	0
T15	4191	0	0	0
T16	2414	8	0	0
T17	1755	4	0	0
T18	2169	0	0	0
T19	1614	0	0	0
T80	0	2	0	0
T81	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T15
1	0	Covered	T5,T1,T16
1	1	Covered	T5,T1,T16

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	266547337	4583	0	0
g_div4.Div4Whole_A	266547337	5232	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266547337	4583	0	0
T1	233209	62	0	0
T2	409609	26	0	0
T3	0	89	0	0
T4	4113	0	0	0
T5	3903	1	0	0
T8	0	16	0	0
T9	0	49	0	0
T14	653	0	0	0
T15	2056	0	0	0
T16	1357	7	0	0
T17	859	1	0	0
T18	1052	0	0	0
T19	788	0	0	0
T80	0	2	0	0
T81	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266547337	5232	0	0
T1	233209	76	0	0
T2	409609	28	0	0
T3	0	91	0	0
T4	4113	0	0	0
T5	3903	1	0	0
T8	0	12	0	0
T9	0	55	0	0
T14	653	0	0	0
T15	2056	0	0	0
T16	1357	8	0	0
T17	859	4	0	0
T18	1052	0	0	0
T19	788	0	0	0
T80	0	2	0	0
T81	0	3	0	0