Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	169090550	147	0	0
IoStatusRise_A	169090550	147	0	0
MainStatusFall_A	169090550	144	0	0
MainStatusRise_A	169090550	144	0	0
UsbStatusFall_A	169090550	146	0	0
UsbStatusRise_A	169090550	146	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	147	0	0
T3	456435	0	0	0
T7	68986	0	0	0
T20	1157	3	0	0
T21	2124	0	0	0
T25	42270	0	0	0
T32	3083	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	7976	0	0	0
T79	944	0	0	0
T80	1314	0	0	0
T81	926	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0
T180	0	5	0	0
T181	0	2	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	147	0	0
T3	456435	0	0	0
T7	68986	0	0	0
T20	1157	3	0	0
T21	2124	0	0	0
T25	42270	0	0	0
T32	3083	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	7976	0	0	0
T79	944	0	0	0
T80	1314	0	0	0
T81	926	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0
T180	0	5	0	0
T181	0	2	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	144	0	0
T3	456435	0	0	0
T7	68986	0	0	0
T20	1157	4	0	0
T21	2124	0	0	0
T25	42270	0	0	0
T32	3083	0	0	0
T33	0	2	0	0
T34	0	7	0	0
T35	7976	0	0	0
T79	944	0	0	0
T80	1314	0	0	0
T81	926	0	0	0
T148	0	3	0	0
T177	0	3	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	6	0	0
T181	0	3	0	0
T182	0	2	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	144	0	0
T3	456435	0	0	0
T7	68986	0	0	0
T20	1157	4	0	0
T21	2124	0	0	0
T25	42270	0	0	0
T32	3083	0	0	0
T33	0	2	0	0
T34	0	7	0	0
T35	7976	0	0	0
T79	944	0	0	0
T80	1314	0	0	0
T81	926	0	0	0
T148	0	3	0	0
T177	0	3	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	6	0	0
T181	0	3	0	0
T182	0	2	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	146	0	0
T3	456435	0	0	0
T7	68986	0	0	0
T20	1157	4	0	0
T21	2124	0	0	0
T25	42270	0	0	0
T32	3083	0	0	0
T33	0	4	0	0
T34	0	6	0	0
T35	7976	0	0	0
T79	944	0	0	0
T80	1314	0	0	0
T81	926	0	0	0
T148	0	4	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	0	4	0	0
T181	0	2	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169090550	146	0	0
T3	456435	0	0	0
T7	68986	0	0	0
T20	1157	4	0	0
T21	2124	0	0	0
T25	42270	0	0	0
T32	3083	0	0	0
T33	0	4	0	0
T34	0	6	0	0
T35	7976	0	0	0
T79	944	0	0	0
T80	1314	0	0	0
T81	926	0	0	0
T148	0	4	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	0	4	0	0
T181	0	2	0	0