Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T5,T4,T1
1	1	Covered	T5,T4,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51521	0	0
CgEnOn_A	2147483647	41909	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51521	0	0
T1	3073827	245	0	0
T2	5365270	266	0	0
T3	1880796	0	0	0
T4	21444	3	0	0
T5	12984	3	0	0
T7	585506	0	0	0
T14	8981	3	0	0
T15	26830	24	0	0
T16	15711	3	0	0
T17	11230	3	0	0
T18	13866	38	0	0
T19	10327	3	0	0
T20	36122	19	0	0
T21	17596	0	0	0
T23	0	5	0	0
T25	154859	0	0	0
T32	55603	7	0	0
T33	0	17	0	0
T34	0	20	0	0
T35	133363	0	0	0
T76	0	5	0	0
T79	7745	0	0	0
T80	11380	0	0	0
T81	78338	0	0	0
T148	0	25	0	0
T176	0	5	0	0
T177	0	10	0	0
T178	0	5	0	0
T179	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41909	0	0
T1	3073827	212	0	0
T2	5365270	248	0	0
T3	1880796	663	0	0
T7	585506	0	0	0
T8	0	38	0	0
T14	8981	0	0	0
T15	26830	21	0	0
T16	15711	0	0	0
T17	11230	0	0	0
T18	13866	35	0	0
T19	10327	0	0	0
T20	45406	28	0	0
T21	22228	45	0	0
T23	0	5	0	0
T25	154859	0	0	0
T32	55603	7	0	0
T33	0	17	0	0
T34	0	20	0	0
T35	133363	0	0	0
T58	0	4	0	0
T76	0	4	0	0
T79	7745	5	0	0
T80	11380	0	0	0
T81	78338	0	0	0
T148	0	25	0	0
T176	0	5	0	0
T177	0	10	0	0
T178	0	5	0	0
T179	0	10	0	0
T180	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Unreachable
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	266546921	157	0	0
CgEnOn_A	266546921	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266546921	157	0	0
T3	216050	0	0	0
T7	67515	0	0	0
T20	2039	3	0	0
T21	1007	0	0	0
T23	0	1	0	0
T25	9808	0	0	0
T32	6373	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	13994	0	0	0
T76	0	1	0	0
T79	861	0	0	0
T80	1314	0	0	0
T81	9390	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266546921	157	0	0
T3	216050	0	0	0
T7	67515	0	0	0
T20	2039	3	0	0
T21	1007	0	0	0
T23	0	1	0	0
T25	9808	0	0	0
T32	6373	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	13994	0	0	0
T76	0	1	0	0
T79	861	0	0	0
T80	1314	0	0	0
T81	9390	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Unreachable
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133272841	157	0	0
CgEnOn_A	133272841	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	157	0	0
T3	108025	0	0	0
T7	33757	0	0	0
T20	1019	3	0	0
T21	504	0	0	0
T23	0	1	0	0
T25	4905	0	0	0
T32	3186	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	6998	0	0	0
T76	0	1	0	0
T79	430	0	0	0
T80	656	0	0	0
T81	4695	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	157	0	0
T3	108025	0	0	0
T7	33757	0	0	0
T20	1019	3	0	0
T21	504	0	0	0
T23	0	1	0	0
T25	4905	0	0	0
T32	3186	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	6998	0	0	0
T76	0	1	0	0
T79	430	0	0	0
T80	656	0	0	0
T81	4695	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Unreachable
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	534662876	157	0	0
CgEnOn_A	534662876	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	157	0	0
T3	432001	0	0	0
T7	135150	0	0	0
T20	4116	3	0	0
T21	2081	0	0	0
T23	0	1	0	0
T25	42270	0	0	0
T32	12866	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	31905	0	0	0
T76	0	1	0	0
T79	1814	0	0	0
T80	2626	0	0	0
T81	17793	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	151	0	0
T3	432001	0	0	0
T7	135150	0	0	0
T20	4116	3	0	0
T21	2081	0	0	0
T23	0	1	0	0
T25	42270	0	0	0
T32	12866	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	31905	0	0	0
T79	1814	0	0	0
T80	2626	0	0	0
T81	17793	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0
T180	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Unreachable
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	567873163	145	0	0
CgEnOn_A	567873163	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	145	0	0
T3	454335	0	0	0
T7	140785	0	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T25	44033	0	0	0
T32	13403	0	0	0
T33	0	2	0	0
T34	0	7	0	0
T35	33235	0	0	0
T79	1890	0	0	0
T80	2736	0	0	0
T81	18535	0	0	0
T148	0	3	0	0
T177	0	3	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	6	0	0
T181	0	3	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	144	0	0
T3	454335	0	0	0
T7	140785	0	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T25	44033	0	0	0
T32	13403	0	0	0
T33	0	2	0	0
T34	0	7	0	0
T35	33235	0	0	0
T79	1890	0	0	0
T80	2736	0	0	0
T81	18535	0	0	0
T148	0	3	0	0
T177	0	3	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	6	0	0
T181	0	3	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Unreachable
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133272841	157	0	0
CgEnOn_A	133272841	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	157	0	0
T3	108025	0	0	0
T7	33757	0	0	0
T20	1019	3	0	0
T21	504	0	0	0
T23	0	1	0	0
T25	4905	0	0	0
T32	3186	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	6998	0	0	0
T76	0	1	0	0
T79	430	0	0	0
T80	656	0	0	0
T81	4695	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	157	0	0
T3	108025	0	0	0
T7	33757	0	0	0
T20	1019	3	0	0
T21	504	0	0	0
T23	0	1	0	0
T25	4905	0	0	0
T32	3186	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	6998	0	0	0
T76	0	1	0	0
T79	430	0	0	0
T80	656	0	0	0
T81	4695	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Unreachable
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	567873163	145	0	0
CgEnOn_A	567873163	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	145	0	0
T3	454335	0	0	0
T7	140785	0	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T25	44033	0	0	0
T32	13403	0	0	0
T33	0	2	0	0
T34	0	7	0	0
T35	33235	0	0	0
T79	1890	0	0	0
T80	2736	0	0	0
T81	18535	0	0	0
T148	0	3	0	0
T177	0	3	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	6	0	0
T181	0	3	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	144	0	0
T3	454335	0	0	0
T7	140785	0	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T25	44033	0	0	0
T32	13403	0	0	0
T33	0	2	0	0
T34	0	7	0	0
T35	33235	0	0	0
T79	1890	0	0	0
T80	2736	0	0	0
T81	18535	0	0	0
T148	0	3	0	0
T177	0	3	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	6	0	0
T181	0	3	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Unreachable
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133272841	157	0	0
CgEnOn_A	133272841	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	157	0	0
T3	108025	0	0	0
T7	33757	0	0	0
T20	1019	3	0	0
T21	504	0	0	0
T23	0	1	0	0
T25	4905	0	0	0
T32	3186	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	6998	0	0	0
T76	0	1	0	0
T79	430	0	0	0
T80	656	0	0	0
T81	4695	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	157	0	0
T3	108025	0	0	0
T7	33757	0	0	0
T20	1019	3	0	0
T21	504	0	0	0
T23	0	1	0	0
T25	4905	0	0	0
T32	3186	0	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	6998	0	0	0
T76	0	1	0	0
T79	430	0	0	0
T80	656	0	0	0
T81	4695	0	0	0
T148	0	5	0	0
T176	0	1	0	0
T177	0	2	0	0
T178	0	1	0	0
T179	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T34
1	0	Covered	T5,T4,T1
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	266546921	8256	0	0
CgEnOn_A	266546921	5860	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266546921	8256	0	0
T1	233209	66	0	0
T2	409609	77	0	0
T4	4113	1	0	0
T5	3902	1	0	0
T14	653	1	0	0
T15	2056	9	0	0
T16	1356	1	0	0
T17	859	1	0	0
T18	1051	13	0	0
T19	788	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266546921	5860	0	0
T1	233209	55	0	0
T2	409609	71	0	0
T3	0	190	0	0
T8	0	10	0	0
T14	653	0	0	0
T15	2056	8	0	0
T16	1356	0	0	0
T17	859	0	0	0
T18	1051	12	0	0
T19	788	0	0	0
T20	2039	3	0	0
T21	1007	15	0	0
T58	0	1	0	0
T79	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T34
1	0	Covered	T5,T4,T1
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133272841	8232	0	0
CgEnOn_A	133272841	5836	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	8232	0	0
T1	116603	70	0	0
T2	204804	78	0	0
T4	2056	1	0	0
T5	1951	1	0	0
T14	326	1	0	0
T15	1028	7	0	0
T16	678	1	0	0
T17	427	1	0	0
T18	526	13	0	0
T19	394	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133272841	5836	0	0
T1	116603	59	0	0
T2	204804	72	0	0
T3	0	186	0	0
T8	0	10	0	0
T14	326	0	0	0
T15	1028	6	0	0
T16	678	0	0	0
T17	427	0	0	0
T18	526	12	0	0
T19	394	0	0	0
T20	1019	3	0	0
T21	504	14	0	0
T58	0	1	0	0
T79	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T34
1	0	Covered	T5,T4,T1
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	534662876	8299	0	0
CgEnOn_A	534662876	5897	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	8299	0	0
T1	467989	70	0	0
T2	818966	75	0	0
T4	8263	1	0	0
T5	4754	1	0	0
T14	1412	1	0	0
T15	4191	8	0	0
T16	2414	1	0	0
T17	1755	1	0	0
T18	2168	12	0	0
T19	1614	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534662876	5897	0	0
T1	467989	59	0	0
T2	818966	69	0	0
T3	0	187	0	0
T8	0	11	0	0
T14	1412	0	0	0
T15	4191	7	0	0
T16	2414	0	0	0
T17	1755	0	0	0
T18	2168	11	0	0
T19	1614	0	0	0
T20	4116	3	0	0
T21	2081	16	0	0
T58	0	1	0	0
T79	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T33,T34
1	0	Covered	T5,T4,T1
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	272734796	8256	0	0
CgEnOn_A	272734796	5850	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272734796	8256	0	0
T1	241206	70	0	0
T2	421023	82	0	0
T4	7012	1	0	0
T5	2377	1	0	0
T14	706	1	0	0
T15	2095	8	0	0
T16	1207	1	0	0
T17	877	1	0	0
T18	1085	14	0	0
T19	807	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272734796	5850	0	0
T1	241206	59	0	0
T2	421023	76	0	0
T3	0	186	0	0
T8	0	10	0	0
T14	706	0	0	0
T15	2095	7	0	0
T16	1207	0	0	0
T17	877	0	0	0
T18	1085	13	0	0
T19	807	0	0	0
T20	2110	4	0	0
T21	1040	15	0	0
T58	0	1	0	0
T79	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T2,T32
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	567873163	4432	0	0
CgEnOn_A	567873163	4431	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	4432	0	0
T1	503705	39	0	0
T2	877717	36	0	0
T3	0	100	0	0
T8	0	7	0	0
T9	0	68	0	0
T14	1471	0	0	0
T15	4365	0	0	0
T16	2514	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	0	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T32	0	7	0	0
T33	0	2	0	0
T58	0	1	0	0
T60	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	4431	0	0
T1	503705	39	0	0
T2	877717	36	0	0
T3	0	100	0	0
T8	0	7	0	0
T9	0	68	0	0
T14	1471	0	0	0
T15	4365	0	0	0
T16	2514	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	0	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T32	0	7	0	0
T33	0	2	0	0
T58	0	1	0	0
T60	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T2,T19
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	567873163	4347	0	0
CgEnOn_A	567873163	4346	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	4347	0	0
T1	503705	40	0	0
T2	877717	39	0	0
T3	0	106	0	0
T8	0	10	0	0
T14	1471	0	0	0
T15	4365	0	0	0
T16	2514	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	1	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T32	0	8	0	0
T33	0	2	0	0
T58	0	1	0	0
T60	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	4346	0	0
T1	503705	40	0	0
T2	877717	39	0	0
T3	0	106	0	0
T8	0	10	0	0
T14	1471	0	0	0
T15	4365	0	0	0
T16	2514	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	1	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T32	0	8	0	0
T33	0	2	0	0
T58	0	1	0	0
T60	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T2,T19
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	567873163	4335	0	0
CgEnOn_A	567873163	4334	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	4335	0	0
T1	503705	37	0	0
T2	877717	36	0	0
T3	0	103	0	0
T8	0	11	0	0
T14	1471	0	0	0
T15	4365	0	0	0
T16	2514	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	1	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T32	0	9	0	0
T33	0	2	0	0
T58	0	1	0	0
T60	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	4334	0	0
T1	503705	37	0	0
T2	877717	36	0	0
T3	0	103	0	0
T8	0	11	0	0
T14	1471	0	0	0
T15	4365	0	0	0
T16	2514	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	1	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T32	0	9	0	0
T33	0	2	0	0
T58	0	1	0	0
T60	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T2,T32
1	1	Covered	T5,T4,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	567873163	4289	0	0
CgEnOn_A	567873163	4288	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	4289	0	0
T1	503705	45	0	0
T2	877717	47	0	0
T3	0	106	0	0
T8	0	7	0	0
T9	0	61	0	0
T14	1471	0	0	0
T15	4365	0	0	0
T16	2514	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	0	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T32	0	11	0	0
T33	0	2	0	0
T58	0	1	0	0
T60	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	567873163	4288	0	0
T1	503705	45	0	0
T2	877717	47	0	0
T3	0	106	0	0
T8	0	7	0	0
T9	0	61	0	0
T14	1471	0	0	0
T15	4365	0	0	0
T16	2514	0	0	0
T17	1828	0	0	0
T18	2259	0	0	0
T19	1681	0	0	0
T20	4485	4	0	0
T21	2166	0	0	0
T32	0	11	0	0
T33	0	2	0	0
T58	0	1	0	0
T60	0	10	0	0