Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	633534	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3677958

1

T5

179

T6

124

T4

425

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1055584	1			T5	16		T6	11		T4	480
values[0x0]	1497004	1			T5	166		T6	114		T4	236
values[0x1]	1758904	1			T5	171		T6	118		T4	224

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	347983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3963509

1

T5

240

T6

161

T4

545

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15512	1			T4	1		T1	218		T2	135
valid_sources[0x01]	16566	1			T4	6		T1	232		T16	1
valid_sources[0x02]	16998	1			T4	3		T1	218		T2	140
valid_sources[0x03]	16288	1			T4	6		T1	194		T2	147
valid_sources[0x04]	15790	1			T4	4		T1	209		T2	124
valid_sources[0x05]	17079	1			T4	2		T1	197		T2	124
valid_sources[0x06]	16551	1			T4	2		T1	222		T2	154
valid_sources[0x07]	16281	1			T6	6		T4	2		T1	164
valid_sources[0x08]	16499	1			T4	1		T24	1		T1	226
valid_sources[0x09]	18015	1			T4	6		T1	212		T2	154
valid_sources[0x0a]	18541	1			T4	5		T1	230		T2	151
valid_sources[0x0b]	17033	1			T4	3		T26	1		T1	212
valid_sources[0x0c]	16535	1			T4	1		T1	219		T2	146
valid_sources[0x0d]	18088	1			T4	1		T27	2		T1	213
valid_sources[0x0e]	17172	1			T1	209		T2	142		T177	3
valid_sources[0x0f]	16455	1			T4	4		T1	235		T2	147
valid_sources[0x10]	17691	1			T4	5		T1	222		T2	141
valid_sources[0x11]	16815	1			T4	6		T1	213		T2	151
valid_sources[0x12]	17252	1			T4	5		T26	1		T1	231
valid_sources[0x13]	16594	1			T1	206		T2	168		T110	2
valid_sources[0x14]	16764	1			T4	8		T1	199		T2	151
valid_sources[0x15]	17567	1			T4	6		T26	1		T1	216
valid_sources[0x16]	15657	1			T4	3		T27	1		T1	188
valid_sources[0x17]	16694	1			T26	1		T1	209		T2	140
valid_sources[0x18]	16755	1			T4	8		T26	1		T1	215
valid_sources[0x19]	17524	1			T4	7		T27	1		T1	226
valid_sources[0x1a]	16053	1			T4	7		T1	209		T2	152
valid_sources[0x1b]	17291	1			T4	3		T1	206		T2	192
valid_sources[0x1c]	17625	1			T4	2		T1	181		T2	159
valid_sources[0x1d]	17276	1			T4	5		T1	223		T2	153
valid_sources[0x1e]	16850	1			T4	3		T1	248		T2	140
valid_sources[0x1f]	15935	1			T4	5		T1	215		T2	141
valid_sources[0x20]	17487	1			T6	1		T4	6		T27	1
valid_sources[0x21]	17708	1			T4	2		T1	206		T2	169
valid_sources[0x22]	16942	1			T4	2		T1	239		T2	154
valid_sources[0x23]	16425	1			T4	1		T1	211		T2	166
valid_sources[0x24]	17618	1			T4	9		T27	2		T1	196
valid_sources[0x25]	15873	1			T4	3		T1	227		T2	143
valid_sources[0x26]	16882	1			T4	2		T27	1		T1	192
valid_sources[0x27]	16632	1			T4	7		T1	223		T2	135
valid_sources[0x28]	17422	1			T4	3		T1	230		T2	127
valid_sources[0x29]	16988	1			T4	4		T1	209		T2	141
valid_sources[0x2a]	15561	1			T4	5		T1	227		T2	144
valid_sources[0x2b]	16824	1			T4	1		T24	1		T1	220
valid_sources[0x2c]	15416	1			T4	5		T1	219		T2	126
valid_sources[0x2d]	16879	1			T4	1		T1	220		T2	139
valid_sources[0x2e]	15728	1			T4	7		T24	1		T1	197
valid_sources[0x2f]	16706	1			T4	4		T27	1		T1	220
valid_sources[0x30]	17047	1			T4	9		T26	1		T1	228
valid_sources[0x31]	17615	1			T4	2		T1	214		T2	188
valid_sources[0x32]	16574	1			T4	3		T26	1		T1	220
valid_sources[0x33]	17126	1			T4	6		T26	1		T1	206
valid_sources[0x34]	19587	1			T4	2		T27	1		T1	208
valid_sources[0x35]	17064	1			T26	1		T1	214		T2	163
valid_sources[0x36]	17271	1			T4	12		T1	213		T2	162
valid_sources[0x37]	16041	1			T4	6		T1	222		T2	159
valid_sources[0x38]	17000	1			T4	5		T1	232		T2	142
valid_sources[0x39]	15061	1			T4	11		T1	196		T2	181
valid_sources[0x3a]	15482	1			T4	1		T1	205		T2	129
valid_sources[0x3b]	16798	1			T4	3		T1	208		T2	175
valid_sources[0x3c]	16153	1			T4	7		T24	1		T27	1
valid_sources[0x3d]	17356	1			T4	1		T1	195		T2	147
valid_sources[0x3e]	16487	1			T4	5		T26	1		T1	228
valid_sources[0x3f]	16322	1			T4	3		T1	219		T2	156
valid_sources[0x40]	16573	1			T26	3		T1	205		T2	158
valid_sources[0x41]	17704	1			T6	8		T4	3		T26	1
valid_sources[0x42]	16742	1			T24	1		T26	1		T27	1
valid_sources[0x43]	16543	1			T4	4		T1	213		T2	132
valid_sources[0x44]	16174	1			T4	1		T1	208		T2	150
valid_sources[0x45]	16498	1			T4	3		T26	1		T1	210
valid_sources[0x46]	17133	1			T6	3		T4	4		T26	1
valid_sources[0x47]	16540	1			T4	6		T1	193		T2	140
valid_sources[0x48]	15910	1			T4	5		T1	211		T2	137
valid_sources[0x49]	17584	1			T4	1		T1	216		T2	181
valid_sources[0x4a]	17044	1			T4	4		T26	1		T1	202
valid_sources[0x4b]	17354	1			T4	10		T26	2		T1	236
valid_sources[0x4c]	17313	1			T6	20		T4	5		T26	2
valid_sources[0x4d]	16791	1			T4	1		T25	4		T1	225
valid_sources[0x4e]	16187	1			T4	7		T27	1		T1	227
valid_sources[0x4f]	17389	1			T4	9		T1	232		T2	151
valid_sources[0x50]	16990	1			T4	4		T1	200		T2	129
valid_sources[0x51]	16973	1			T4	3		T1	215		T2	156
valid_sources[0x52]	15463	1			T4	1		T26	2		T1	208
valid_sources[0x53]	17492	1			T4	7		T1	205		T2	135
valid_sources[0x54]	18487	1			T6	4		T4	1		T1	240
valid_sources[0x55]	16539	1			T24	1		T1	234		T2	145
valid_sources[0x56]	16923	1			T4	4		T1	215		T2	141
valid_sources[0x57]	15912	1			T4	2		T1	225		T2	129
valid_sources[0x58]	17862	1			T4	1		T24	1		T1	220
valid_sources[0x59]	19126	1			T4	5		T1	209		T2	165
valid_sources[0x5a]	15249	1			T4	4		T1	211		T2	129
valid_sources[0x5b]	17517	1			T4	6		T26	2		T1	194
valid_sources[0x5c]	16814	1			T4	2		T1	225		T2	151
valid_sources[0x5d]	17108	1			T6	10		T4	5		T1	221
valid_sources[0x5e]	16041	1			T4	2		T1	221		T2	134
valid_sources[0x5f]	16199	1			T4	7		T24	1		T1	202
valid_sources[0x60]	16610	1			T4	1		T24	1		T1	240
valid_sources[0x61]	16512	1			T4	6		T1	219		T2	137
valid_sources[0x62]	17636	1			T1	235		T2	141		T20	1
valid_sources[0x63]	16749	1			T4	1		T1	213		T2	148
valid_sources[0x64]	16317	1			T4	6		T24	1		T1	214
valid_sources[0x65]	17430	1			T4	7		T1	207		T2	157
valid_sources[0x66]	16344	1			T1	210		T2	166		T78	1
valid_sources[0x67]	16948	1			T4	1		T1	244		T2	160
valid_sources[0x68]	15121	1			T4	5		T1	243		T2	182
valid_sources[0x69]	17118	1			T4	1		T1	192		T2	141
valid_sources[0x6a]	18410	1			T4	3		T1	220		T2	145
valid_sources[0x6b]	16719	1			T1	208		T2	174		T78	1
valid_sources[0x6c]	17016	1			T6	19		T4	3		T1	234
valid_sources[0x6d]	17353	1			T4	5		T26	1		T1	226
valid_sources[0x6e]	16134	1			T4	4		T1	224		T2	142
valid_sources[0x6f]	15640	1			T4	4		T1	204		T2	167
valid_sources[0x70]	16083	1			T1	211		T2	135		T9	2
valid_sources[0x71]	16348	1			T4	1		T24	1		T26	1
valid_sources[0x72]	16522	1			T4	3		T26	1		T1	216
valid_sources[0x73]	17650	1			T4	5		T1	184		T2	166
valid_sources[0x74]	16328	1			T4	4		T24	1		T1	199
valid_sources[0x75]	18131	1			T4	5		T26	1		T1	197
valid_sources[0x76]	18114	1			T4	8		T27	1		T1	242
valid_sources[0x77]	17136	1			T4	2		T1	234		T2	168
valid_sources[0x78]	17843	1			T4	4		T24	1		T1	216
valid_sources[0x79]	16570	1			T4	5		T26	1		T1	205
valid_sources[0x7a]	16494	1			T4	6		T1	224		T2	166
valid_sources[0x7b]	17476	1			T4	5		T26	1		T1	232
valid_sources[0x7c]	15172	1			T4	3		T1	197		T2	167
valid_sources[0x7d]	17528	1			T4	4		T1	220		T2	154
valid_sources[0x7e]	16450	1			T4	4		T27	1		T1	249
valid_sources[0x7f]	17804	1			T4	7		T26	1		T27	1
valid_sources[0x80]	16630	1			T4	2		T27	1		T1	221

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

924813

1

T5

9

T6

4

T4

228

values[0x0]

all_enables

biggest_size

1401622

1

T5

108

T6

77

T4

117

values[0x1]

all_enables

biggest_size

1351523

1

T5

62

T6

43

T4

80