SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
92.86 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[clkmgr_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 11877894 | 0 | T5 | 353 | T6 | 243 | T4 | 940 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 11877680 | 1 | T5 | 353 | T6 | 243 | T4 | 940 | ||||
values[1] | 24 | 1 | T97 | 2 | T173 | 1 | T174 | 3 | ||||
values[2] | 4 | 1 | T98 | 1 | T103 | 1 | T104 | 1 | ||||
values[3] | 95 | 1 | T96 | 3 | T97 | 7 | T98 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 11877695 | 1 | T5 | 353 | T6 | 243 | T4 | 940 | ||||
values[1] | 22 | 1 | T97 | 3 | T173 | 2 | T175 | 1 | ||||
values[2] | 5 | 1 | T174 | 1 | T106 | 1 | T176 | 1 | ||||
values[3] | 97 | 1 | T96 | 3 | T97 | 9 | T98 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 11877594 | 1 | T5 | 353 | T6 | 243 | T4 | 940 | ||||
auto[TlIntgErrCmd] | 101 | 1 | T96 | 4 | T97 | 4 | T98 | 6 | ||||
auto[TlIntgErrData] | 86 | 1 | T96 | 2 | T97 | 8 | T98 | 2 | ||||
auto[TlIntgErrBoth] | 113 | 1 | T96 | 4 | T97 | 8 | T98 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |