SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 325015538 | 320015514 | 0 | 0 |
gen_flops.OutputDelay_A | 325015538 | 320001580 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T16 | 2 | 2 | 0 | 0 |
T24 | 2 | 2 | 0 | 0 |
T25 | 2 | 2 | 0 | 0 |
T26 | 2 | 2 | 0 | 0 |
T27 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 325015538 | 320015514 | 0 | 0 |
T1 | 473722 | 473402 | 0 | 0 |
T2 | 282396 | 282342 | 0 | 0 |
T4 | 236964 | 11190 | 0 | 0 |
T5 | 186852 | 186648 | 0 | 0 |
T6 | 67656 | 67614 | 0 | 0 |
T16 | 2726 | 2668 | 0 | 0 |
T24 | 3138 | 2726 | 0 | 0 |
T25 | 1400 | 1346 | 0 | 0 |
T26 | 2736 | 2700 | 0 | 0 |
T27 | 3226 | 3160 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 325015538 | 320001580 | 0 | 4830 |
T1 | 473722 | 473398 | 0 | 6 |
T2 | 282396 | 282338 | 0 | 6 |
T4 | 236964 | 11064 | 0 | 6 |
T5 | 186852 | 186642 | 0 | 6 |
T6 | 67656 | 67608 | 0 | 6 |
T16 | 2726 | 2662 | 0 | 6 |
T24 | 3138 | 2720 | 0 | 6 |
T25 | 1400 | 1340 | 0 | 6 |
T26 | 2736 | 2694 | 0 | 6 |
T27 | 3226 | 3154 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 162507769 | 160007757 | 0 | 0 |
gen_flops.OutputDelay_A | 162507769 | 160000790 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 162507769 | 160007757 | 0 | 0 |
T1 | 236861 | 236701 | 0 | 0 |
T2 | 141198 | 141171 | 0 | 0 |
T4 | 118482 | 5595 | 0 | 0 |
T5 | 93426 | 93324 | 0 | 0 |
T6 | 33828 | 33807 | 0 | 0 |
T16 | 1363 | 1334 | 0 | 0 |
T24 | 1569 | 1363 | 0 | 0 |
T25 | 700 | 673 | 0 | 0 |
T26 | 1368 | 1350 | 0 | 0 |
T27 | 1613 | 1580 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 162507769 | 160000790 | 0 | 2415 |
T1 | 236861 | 236699 | 0 | 3 |
T2 | 141198 | 141169 | 0 | 3 |
T4 | 118482 | 5532 | 0 | 3 |
T5 | 93426 | 93321 | 0 | 3 |
T6 | 33828 | 33804 | 0 | 3 |
T16 | 1363 | 1331 | 0 | 3 |
T24 | 1569 | 1360 | 0 | 3 |
T25 | 700 | 670 | 0 | 3 |
T26 | 1368 | 1347 | 0 | 3 |
T27 | 1613 | 1577 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 162507769 | 160007757 | 0 | 0 |
gen_flops.OutputDelay_A | 162507769 | 160000790 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T24 | 1 | 1 | 0 | 0 |
T25 | 1 | 1 | 0 | 0 |
T26 | 1 | 1 | 0 | 0 |
T27 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 162507769 | 160007757 | 0 | 0 |
T1 | 236861 | 236701 | 0 | 0 |
T2 | 141198 | 141171 | 0 | 0 |
T4 | 118482 | 5595 | 0 | 0 |
T5 | 93426 | 93324 | 0 | 0 |
T6 | 33828 | 33807 | 0 | 0 |
T16 | 1363 | 1334 | 0 | 0 |
T24 | 1569 | 1363 | 0 | 0 |
T25 | 700 | 673 | 0 | 0 |
T26 | 1368 | 1350 | 0 | 0 |
T27 | 1613 | 1580 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 162507769 | 160000790 | 0 | 2415 |
T1 | 236861 | 236699 | 0 | 3 |
T2 | 141198 | 141169 | 0 | 3 |
T4 | 118482 | 5532 | 0 | 3 |
T5 | 93426 | 93321 | 0 | 3 |
T6 | 33828 | 33804 | 0 | 3 |
T16 | 1363 | 1331 | 0 | 3 |
T24 | 1569 | 1360 | 0 | 3 |
T25 | 700 | 670 | 0 | 3 |
T26 | 1368 | 1347 | 0 | 3 |
T27 | 1613 | 1577 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |