Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	639215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3800805

1

T1

831

T5

13

T4

106

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1094747	1			T1	303		T5	13		T4	10
values[0x0]	1537174	1			T1	787		T5	11		T4	108
values[0x1]	1808099	1			T1	711		T5	16		T4	103

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	348381	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4091639

1

T1

1051

T5

20

T4

136

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16602	1			T1	3		T3	338		T10	2
valid_sources[0x01]	17805	1			T1	12		T3	338		T10	2
valid_sources[0x02]	17657	1			T1	7		T5	1		T3	350
valid_sources[0x03]	16739	1			T5	1		T3	365		T10	4
valid_sources[0x04]	18289	1			T1	5		T3	330		T18	2
valid_sources[0x05]	17347	1			T1	6		T5	1		T3	355
valid_sources[0x06]	17287	1			T1	10		T3	326		T10	5
valid_sources[0x07]	17061	1			T1	9		T2	1		T3	312
valid_sources[0x08]	18031	1			T1	4		T2	3		T3	350
valid_sources[0x09]	17536	1			T1	3		T2	3		T3	355
valid_sources[0x0a]	16235	1			T1	15		T5	1		T3	347
valid_sources[0x0b]	17207	1			T1	8		T2	2		T3	352
valid_sources[0x0c]	17431	1			T1	10		T3	373		T10	2
valid_sources[0x0d]	17987	1			T1	5		T3	389		T10	3
valid_sources[0x0e]	17450	1			T1	7		T5	1		T3	373
valid_sources[0x0f]	16034	1			T1	6		T3	332		T10	3
valid_sources[0x10]	18554	1			T1	4		T16	1		T3	365
valid_sources[0x11]	17450	1			T1	8		T2	1		T3	357
valid_sources[0x12]	17728	1			T1	4		T2	2		T3	380
valid_sources[0x13]	16278	1			T1	4		T3	361		T10	1
valid_sources[0x14]	16936	1			T1	4		T3	346		T10	1
valid_sources[0x15]	17186	1			T1	6		T3	362		T10	1
valid_sources[0x16]	16588	1			T1	8		T3	294		T18	1
valid_sources[0x17]	18099	1			T1	16		T3	330		T9	43
valid_sources[0x18]	17422	1			T1	3		T5	1		T3	316
valid_sources[0x19]	18754	1			T1	7		T3	393		T18	1
valid_sources[0x1a]	15754	1			T1	10		T3	341		T10	5
valid_sources[0x1b]	16719	1			T1	11		T3	341		T10	3
valid_sources[0x1c]	16947	1			T1	11		T5	1		T3	371
valid_sources[0x1d]	17774	1			T1	7		T3	403		T18	2
valid_sources[0x1e]	18047	1			T1	9		T3	345		T10	5
valid_sources[0x1f]	16217	1			T1	6		T2	4		T3	370
valid_sources[0x20]	17314	1			T1	7		T5	1		T3	388
valid_sources[0x21]	17611	1			T1	6		T3	357		T11	5
valid_sources[0x22]	17806	1			T1	7		T2	4		T3	346
valid_sources[0x23]	18265	1			T1	6		T5	2		T2	1
valid_sources[0x24]	16290	1			T1	7		T16	1		T3	353
valid_sources[0x25]	17172	1			T1	4		T5	1		T3	356
valid_sources[0x26]	17324	1			T1	9		T3	404		T10	4
valid_sources[0x27]	19121	1			T1	8		T2	5		T3	330
valid_sources[0x28]	18361	1			T1	9		T3	356		T18	2
valid_sources[0x29]	17549	1			T1	5		T3	347		T10	2
valid_sources[0x2a]	20072	1			T1	6		T2	1		T3	398
valid_sources[0x2b]	16442	1			T1	4		T5	1		T3	343
valid_sources[0x2c]	16263	1			T1	5		T2	2		T3	351
valid_sources[0x2d]	17915	1			T1	6		T3	365		T10	1
valid_sources[0x2e]	16683	1			T1	9		T2	2		T3	312
valid_sources[0x2f]	18372	1			T1	5		T5	1		T2	9
valid_sources[0x30]	17790	1			T1	13		T3	361		T10	4
valid_sources[0x31]	16606	1			T1	11		T16	1		T3	324
valid_sources[0x32]	17524	1			T1	5		T2	4		T3	343
valid_sources[0x33]	17419	1			T1	6		T3	325		T18	1
valid_sources[0x34]	17787	1			T1	7		T5	1		T3	333
valid_sources[0x35]	15876	1			T1	9		T2	3		T3	363
valid_sources[0x36]	17471	1			T1	10		T3	362		T10	2
valid_sources[0x37]	17618	1			T1	13		T2	5		T3	399
valid_sources[0x38]	16933	1			T1	14		T2	1		T3	415
valid_sources[0x39]	18114	1			T1	12		T3	346		T10	2
valid_sources[0x3a]	18309	1			T1	6		T2	2		T3	379
valid_sources[0x3b]	16694	1			T1	9		T2	1		T3	323
valid_sources[0x3c]	16470	1			T1	8		T3	327		T10	9
valid_sources[0x3d]	17832	1			T1	11		T3	364		T9	10
valid_sources[0x3e]	17486	1			T1	10		T3	358		T11	2
valid_sources[0x3f]	17659	1			T1	7		T3	306		T10	4
valid_sources[0x40]	17610	1			T1	5		T2	9		T3	368
valid_sources[0x41]	16158	1			T1	4		T16	1		T3	366
valid_sources[0x42]	16032	1			T1	11		T3	329		T10	8
valid_sources[0x43]	16692	1			T1	8		T3	341		T10	2
valid_sources[0x44]	17773	1			T1	1		T3	357		T18	1
valid_sources[0x45]	17266	1			T1	8		T16	1		T3	374
valid_sources[0x46]	15695	1			T3	407		T18	1		T11	9
valid_sources[0x47]	17816	1			T1	10		T3	375		T10	4
valid_sources[0x48]	16547	1			T1	7		T2	4		T3	324
valid_sources[0x49]	16524	1			T1	9		T3	351		T18	1
valid_sources[0x4a]	17679	1			T1	5		T2	3		T3	356
valid_sources[0x4b]	17821	1			T1	9		T2	5		T16	1
valid_sources[0x4c]	17886	1			T1	2		T3	375		T10	2
valid_sources[0x4d]	17935	1			T1	5		T5	1		T3	345
valid_sources[0x4e]	16381	1			T1	8		T5	1		T3	345
valid_sources[0x4f]	17687	1			T1	2		T2	1		T3	406
valid_sources[0x50]	16917	1			T1	6		T2	1		T3	373
valid_sources[0x51]	17617	1			T1	6		T3	361		T10	3
valid_sources[0x52]	16233	1			T1	8		T3	381		T18	1
valid_sources[0x53]	17591	1			T1	9		T3	336		T10	2
valid_sources[0x54]	17174	1			T1	14		T2	9		T3	328
valid_sources[0x55]	16753	1			T1	7		T3	374		T10	1
valid_sources[0x56]	17379	1			T1	5		T16	1		T3	363
valid_sources[0x57]	16701	1			T1	5		T3	308		T10	5
valid_sources[0x58]	17115	1			T1	8		T3	378		T10	1
valid_sources[0x59]	17069	1			T1	5		T3	319		T11	9
valid_sources[0x5a]	17499	1			T1	12		T3	312		T10	1
valid_sources[0x5b]	16953	1			T1	5		T3	314		T18	1
valid_sources[0x5c]	16668	1			T1	9		T3	331		T10	2
valid_sources[0x5d]	18133	1			T1	6		T3	360		T10	5
valid_sources[0x5e]	18082	1			T1	10		T3	367		T18	1
valid_sources[0x5f]	18034	1			T1	6		T3	350		T11	6
valid_sources[0x60]	16643	1			T1	4		T3	402		T10	1
valid_sources[0x61]	18839	1			T1	9		T3	364		T10	3
valid_sources[0x62]	16666	1			T1	2		T5	1		T2	6
valid_sources[0x63]	17174	1			T1	5		T3	350		T10	1
valid_sources[0x64]	17591	1			T1	8		T16	1		T3	389
valid_sources[0x65]	17260	1			T1	2		T3	331		T70	1
valid_sources[0x66]	16662	1			T1	12		T2	4		T3	340
valid_sources[0x67]	18286	1			T1	15		T2	1		T3	371
valid_sources[0x68]	17565	1			T1	6		T3	397		T10	1
valid_sources[0x69]	16502	1			T1	4		T3	365		T10	2
valid_sources[0x6a]	17118	1			T1	10		T2	1		T3	365
valid_sources[0x6b]	18434	1			T1	7		T3	385		T10	2
valid_sources[0x6c]	16654	1			T1	3		T3	364		T11	5
valid_sources[0x6d]	17690	1			T1	9		T3	400		T18	3
valid_sources[0x6e]	17576	1			T1	12		T3	386		T10	2
valid_sources[0x6f]	18024	1			T1	9		T3	379		T10	1
valid_sources[0x70]	16332	1			T3	370		T10	4		T11	5
valid_sources[0x71]	16730	1			T1	6		T5	1		T3	360
valid_sources[0x72]	17593	1			T1	8		T3	326		T9	1
valid_sources[0x73]	18506	1			T1	6		T2	1		T3	369
valid_sources[0x74]	16970	1			T1	9		T5	1		T2	6
valid_sources[0x75]	16121	1			T1	3		T3	391		T10	1
valid_sources[0x76]	18404	1			T1	5		T2	5		T3	333
valid_sources[0x77]	16911	1			T1	6		T3	361		T18	2
valid_sources[0x78]	16608	1			T1	5		T3	316		T10	2
valid_sources[0x79]	17542	1			T1	13		T2	1		T3	392
valid_sources[0x7a]	18298	1			T1	9		T3	335		T18	1
valid_sources[0x7b]	17802	1			T1	14		T3	350		T10	1
valid_sources[0x7c]	15085	1			T1	3		T2	7		T3	374
valid_sources[0x7d]	17549	1			T1	10		T3	345		T10	3
valid_sources[0x7e]	17236	1			T1	4		T2	3		T3	397
valid_sources[0x7f]	18153	1			T1	4		T5	1		T16	1
valid_sources[0x80]	18832	1			T1	7		T2	1		T3	378

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

962252

1

T1

145

T5

6

T4

4

values[0x0]

all_enables

biggest_size

1443423

1

T1

459

T5

4

T4

64

values[0x1]

all_enables

biggest_size

1395130

1

T1

227

T5

3

T4

38