Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
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Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

17 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
lockable_field_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.extclk_ctrl.sel 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_shadowed.hi 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_shadowed.lo 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_shadowed.hi 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_shadowed.lo 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_shadowed.hi 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_shadowed.lo 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_shadowed.hi 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_shadowed.lo 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_shadowed.hi 100.00 1 100 1 64 64
lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_shadowed.lo 100.00 1 100 1 64 64




Group Instance : lockable_field_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.extclk_ctrl.hi_speed_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.extclk_ctrl.sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.extclk_ctrl.sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.extclk_ctrl.sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_shadowed.hi
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_shadowed.hi

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_shadowed.hi
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_shadowed.lo
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_shadowed.lo

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div2_meas_ctrl_shadowed.lo
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_shadowed.hi
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_shadowed.hi

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_shadowed.hi
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_shadowed.lo
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_shadowed.lo

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_div4_meas_ctrl_shadowed.lo
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_shadowed.hi
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_shadowed.hi

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_shadowed.hi
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_shadowed.lo
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_shadowed.lo

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.io_meas_ctrl_shadowed.lo
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_shadowed.hi
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_shadowed.hi

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_shadowed.hi
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_shadowed.lo
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_shadowed.lo

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.main_meas_ctrl_shadowed.lo
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_en.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_shadowed.hi
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_shadowed.hi

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_shadowed.hi
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_shadowed.lo
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_shadowed.lo

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_clkmgr_reg_block.usb_meas_ctrl_shadowed.lo
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 178 1 T76 5 T78 4 T180 7
auto[1] 8250 1 T1 26 T5 13 T16 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 193 1 T76 5 T103 2 T181 3
auto[1] 8291 1 T1 26 T5 13 T16 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 197 1 T76 6 T103 2 T78 2
auto[1] 1824 1 T1 3 T2 2 T3 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 665 1 T76 6 T103 3 T78 2
auto[1] 1092 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 614 1 T76 6 T103 3 T78 2
auto[1] 1053 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 196 1 T76 4 T103 2 T78 2
auto[1] 1822 1 T1 3 T2 2 T3 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 723 1 T76 6 T103 3 T78 2
auto[1] 1016 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 675 1 T76 6 T103 3 T78 2
auto[1] 984 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 221 1 T76 6 T103 3 T78 2
auto[1] 1827 1 T1 3 T2 2 T3 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 729 1 T76 6 T103 3 T78 2
auto[1] 1039 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 669 1 T76 6 T103 3 T78 2
auto[1] 999 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 215 1 T76 3 T103 3 T78 2
auto[1] 1816 1 T1 3 T2 2 T3 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 705 1 T76 6 T103 3 T78 2
auto[1] 1016 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 643 1 T76 6 T103 3 T78 2
auto[1] 978 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 201 1 T76 3 T103 2 T78 2
auto[1] 1815 1 T1 3 T2 2 T3 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 656 1 T76 6 T103 3 T78 2
auto[1] 1081 1 T76 6 T78 4 T181 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 601 1 T76 6 T103 3 T78 2
auto[1] 1045 1 T76 6 T78 4 T181 4

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