Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T18
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1271959662	14619	0	0
GateOpen_A	1271959662	21023	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271959662	14619	0	0
T1	1548027	72	0	0
T2	328723	0	0	0
T3	2243852	15	0	0
T4	206768	0	0	0
T5	4562	0	0	0
T9	458731	0	0	0
T10	584991	0	0	0
T12	0	425	0	0
T13	0	94	0	0
T14	0	300	0	0
T16	13577	0	0	0
T17	2952	0	0	0
T18	14453	4	0	0
T72	0	3	0	0
T153	0	15	0	0
T174	0	8	0	0
T175	0	4	0	0
T176	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1271959662	21023	0	0
T1	1548027	92	0	0
T2	328723	0	0	0
T3	2243852	23	0	0
T4	206768	0	0	0
T5	4562	4	0	0
T9	458731	4	0	0
T10	584991	8	0	0
T11	0	8	0	0
T16	13577	4	0	0
T17	2952	4	0	0
T18	14453	8	0	0
T70	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T18
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	140567641	3425	0	0
GateOpen_A	140567641	5025	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567641	3425	0	0
T1	173197	16	0	0
T2	36514	0	0	0
T3	249055	4	0	0
T4	21681	0	0	0
T5	503	0	0	0
T9	50950	0	0	0
T10	64956	0	0	0
T12	0	103	0	0
T13	0	20	0	0
T14	0	71	0	0
T16	1573	0	0	0
T17	319	0	0	0
T18	1586	1	0	0
T153	0	3	0	0
T174	0	2	0	0
T175	0	1	0	0
T176	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567641	5025	0	0
T1	173197	21	0	0
T2	36514	0	0	0
T3	249055	6	0	0
T4	21681	0	0	0
T5	503	1	0	0
T9	50950	1	0	0
T10	64956	2	0	0
T11	0	2	0	0
T16	1573	1	0	0
T17	319	1	0	0
T18	1586	2	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T18
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	281136032	3704	0	0
GateOpen_A	281136032	5304	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281136032	3704	0	0
T1	346396	19	0	0
T2	73027	0	0	0
T3	498111	4	0	0
T4	43362	0	0	0
T5	1007	0	0	0
T9	101899	0	0	0
T10	129911	0	0	0
T12	0	102	0	0
T13	0	27	0	0
T14	0	74	0	0
T16	3146	0	0	0
T17	639	0	0	0
T18	3172	1	0	0
T72	0	1	0	0
T153	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281136032	5304	0	0
T1	346396	24	0	0
T2	73027	0	0	0
T3	498111	6	0	0
T4	43362	0	0	0
T5	1007	1	0	0
T9	101899	1	0	0
T10	129911	2	0	0
T11	0	2	0	0
T16	3146	1	0	0
T17	639	1	0	0
T18	3172	2	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T18
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	563724158	3760	0	0
GateOpen_A	563724158	5362	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563724158	3760	0	0
T1	691371	19	0	0
T2	146119	0	0	0
T3	996431	4	0	0
T4	86803	0	0	0
T5	2035	0	0	0
T9	203918	0	0	0
T10	260079	0	0	0
T12	0	112	0	0
T13	0	24	0	0
T14	0	75	0	0
T16	5905	0	0	0
T17	1329	0	0	0
T18	6463	1	0	0
T72	0	1	0	0
T153	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563724158	5362	0	0
T1	691371	24	0	0
T2	146119	0	0	0
T3	996431	6	0	0
T4	86803	0	0	0
T5	2035	1	0	0
T9	203918	1	0	0
T10	260079	2	0	0
T11	0	2	0	0
T16	5905	1	0	0
T17	1329	1	0	0
T18	6463	2	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T18
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T5,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	286531831	3730	0	0
GateOpen_A	286531831	5332	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286531831	3730	0	0
T1	337063	18	0	0
T2	73063	0	0	0
T3	500255	3	0	0
T4	54922	0	0	0
T5	1017	0	0	0
T9	101964	0	0	0
T10	130045	0	0	0
T12	0	108	0	0
T13	0	23	0	0
T14	0	80	0	0
T16	2953	0	0	0
T17	665	0	0	0
T18	3232	1	0	0
T72	0	1	0	0
T153	0	4	0	0
T174	0	2	0	0
T175	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286531831	5332	0	0
T1	337063	23	0	0
T2	73063	0	0	0
T3	500255	5	0	0
T4	54922	0	0	0
T5	1017	1	0	0
T9	101964	1	0	0
T10	130045	2	0	0
T11	0	2	0	0
T16	2953	1	0	0
T17	665	1	0	0
T18	3232	2	0	0
T70	0	1	0	0