Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	835717555	73417	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	835717555	73417	0	0
T1	975245	106	0	0
T2	365315	62	0	0
T3	1304225	172	0	0
T4	151700	0	0	0
T5	10170	0	0	0
T9	509820	206	0	0
T10	1341075	304	0	0
T11	0	263	0	0
T12	0	1035	0	0
T13	0	678	0	0
T14	0	702	0	0
T15	0	151	0	0
T16	7685	0	0	0
T17	6920	0	0	0
T18	8410	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167143511	10794	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	10794	0	0
T1	195049	18	0	0
T2	73063	9	0	0
T3	260845	27	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	29	0	0
T10	268215	40	0	0
T11	0	43	0	0
T12	0	170	0	0
T13	0	89	0	0
T14	0	113	0	0
T15	0	24	0	0
T16	1537	0	0	0
T17	1384	0	0	0
T18	1682	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167143511	14711	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	14711	0	0
T1	195049	21	0	0
T2	73063	12	0	0
T3	260845	34	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	40	0	0
T10	268215	62	0	0
T11	0	53	0	0
T12	0	210	0	0
T13	0	136	0	0
T14	0	143	0	0
T15	0	30	0	0
T16	1537	0	0	0
T17	1384	0	0	0
T18	1682	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167143511	22534	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	22534	0	0
T1	195049	29	0	0
T2	73063	18	0	0
T3	260845	49	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	62	0	0
T10	268215	99	0	0
T11	0	74	0	0
T12	0	275	0	0
T13	0	230	0	0
T14	0	192	0	0
T15	0	43	0	0
T16	1537	0	0	0
T17	1384	0	0	0
T18	1682	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167143511	10611	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	10611	0	0
T1	195049	17	0	0
T2	73063	9	0	0
T3	260845	26	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	29	0	0
T10	268215	40	0	0
T11	0	41	0	0
T12	0	170	0	0
T13	0	86	0	0
T14	0	111	0	0
T15	0	24	0	0
T16	1537	0	0	0
T17	1384	0	0	0
T18	1682	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167143511	14767	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	14767	0	0
T1	195049	21	0	0
T2	73063	14	0	0
T3	260845	36	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	46	0	0
T10	268215	63	0	0
T11	0	52	0	0
T12	0	210	0	0
T13	0	137	0	0
T14	0	143	0	0
T15	0	30	0	0
T16	1537	0	0	0
T17	1384	0	0	0
T18	1682	0	0	0