Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T3 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T9 |
28 |
28 |
0 |
0 |
T10 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
11397891 |
11381493 |
0 |
0 |
T2 |
2867631 |
2865495 |
0 |
0 |
T3 |
7827375 |
7824081 |
0 |
0 |
T4 |
1802107 |
1799829 |
0 |
0 |
T5 |
54140 |
50793 |
0 |
0 |
T9 |
4001930 |
3998077 |
0 |
0 |
T10 |
7038393 |
7026409 |
0 |
0 |
T16 |
96355 |
93658 |
0 |
0 |
T17 |
36112 |
31720 |
0 |
0 |
T18 |
105051 |
102125 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1002861066 |
988509624 |
0 |
14490 |
T1 |
1170294 |
1168338 |
0 |
18 |
T2 |
438378 |
438000 |
0 |
18 |
T3 |
1565070 |
1564254 |
0 |
18 |
T4 |
182040 |
181782 |
0 |
18 |
T5 |
12204 |
11376 |
0 |
18 |
T9 |
611784 |
611118 |
0 |
18 |
T10 |
1609290 |
1606290 |
0 |
18 |
T16 |
9222 |
8910 |
0 |
18 |
T17 |
8304 |
7182 |
0 |
18 |
T18 |
10092 |
9762 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
3938273 |
3931434 |
0 |
21 |
T2 |
901093 |
900327 |
0 |
21 |
T3 |
1933793 |
1932787 |
0 |
21 |
T4 |
629162 |
628222 |
0 |
21 |
T5 |
14578 |
13592 |
0 |
21 |
T9 |
1257529 |
1256167 |
0 |
21 |
T10 |
1880204 |
1876694 |
0 |
21 |
T16 |
33582 |
32482 |
0 |
21 |
T17 |
9633 |
8332 |
0 |
21 |
T18 |
36755 |
35583 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
200374 |
0 |
0 |
T1 |
3938273 |
807 |
0 |
0 |
T2 |
901093 |
4 |
0 |
0 |
T3 |
1933793 |
539 |
0 |
0 |
T4 |
629162 |
4 |
0 |
0 |
T5 |
14578 |
106 |
0 |
0 |
T9 |
1257529 |
4 |
0 |
0 |
T10 |
1880204 |
111 |
0 |
0 |
T12 |
0 |
1418 |
0 |
0 |
T13 |
0 |
163 |
0 |
0 |
T14 |
0 |
280 |
0 |
0 |
T16 |
33582 |
115 |
0 |
0 |
T17 |
9633 |
33 |
0 |
0 |
T18 |
36755 |
20 |
0 |
0 |
T70 |
0 |
54 |
0 |
0 |
T71 |
0 |
70 |
0 |
0 |
T104 |
0 |
146 |
0 |
0 |
T116 |
0 |
4 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
6289324 |
6281409 |
0 |
0 |
T2 |
1528160 |
1527129 |
0 |
0 |
T3 |
4328512 |
4327023 |
0 |
0 |
T4 |
990905 |
989786 |
0 |
0 |
T5 |
27358 |
25786 |
0 |
0 |
T9 |
2132617 |
2130753 |
0 |
0 |
T10 |
3548899 |
3543308 |
0 |
0 |
T16 |
53551 |
52227 |
0 |
0 |
T17 |
18175 |
16167 |
0 |
0 |
T18 |
58204 |
56741 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T16 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T16 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T16 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T16 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T16 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563723717 |
559466355 |
0 |
0 |
T1 |
691371 |
690196 |
0 |
0 |
T2 |
146119 |
145998 |
0 |
0 |
T3 |
996431 |
995914 |
0 |
0 |
T4 |
86802 |
86639 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
203917 |
203700 |
0 |
0 |
T10 |
260078 |
259601 |
0 |
0 |
T16 |
5904 |
5715 |
0 |
0 |
T17 |
1329 |
1153 |
0 |
0 |
T18 |
6463 |
6260 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563723717 |
559459569 |
0 |
2415 |
T1 |
691371 |
690172 |
0 |
3 |
T2 |
146119 |
145995 |
0 |
3 |
T3 |
996431 |
995913 |
0 |
3 |
T4 |
86802 |
86636 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
203917 |
203697 |
0 |
3 |
T10 |
260078 |
259592 |
0 |
3 |
T16 |
5904 |
5712 |
0 |
3 |
T17 |
1329 |
1150 |
0 |
3 |
T18 |
6463 |
6257 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563723717 |
27213 |
0 |
0 |
T1 |
691371 |
87 |
0 |
0 |
T2 |
146119 |
0 |
0 |
0 |
T3 |
996431 |
54 |
0 |
0 |
T4 |
86802 |
0 |
0 |
0 |
T5 |
2034 |
27 |
0 |
0 |
T9 |
203917 |
0 |
0 |
0 |
T10 |
260078 |
0 |
0 |
0 |
T12 |
0 |
594 |
0 |
0 |
T13 |
0 |
60 |
0 |
0 |
T16 |
5904 |
32 |
0 |
0 |
T17 |
1329 |
8 |
0 |
0 |
T18 |
6463 |
0 |
0 |
0 |
T70 |
0 |
27 |
0 |
0 |
T71 |
0 |
38 |
0 |
0 |
T104 |
0 |
48 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T16,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T16,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T16,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T16,T3 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T3 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T16,T3 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164751604 |
0 |
2415 |
T1 |
195049 |
194723 |
0 |
3 |
T2 |
73063 |
73000 |
0 |
3 |
T3 |
260845 |
260709 |
0 |
3 |
T4 |
30340 |
30297 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
101964 |
101853 |
0 |
3 |
T10 |
268215 |
267715 |
0 |
3 |
T16 |
1537 |
1485 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
1682 |
1627 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
16759 |
0 |
0 |
T1 |
195049 |
48 |
0 |
0 |
T2 |
73063 |
0 |
0 |
0 |
T3 |
260845 |
31 |
0 |
0 |
T4 |
30340 |
0 |
0 |
0 |
T5 |
2034 |
0 |
0 |
0 |
T9 |
101964 |
0 |
0 |
0 |
T10 |
268215 |
0 |
0 |
0 |
T12 |
0 |
394 |
0 |
0 |
T13 |
0 |
47 |
0 |
0 |
T14 |
0 |
280 |
0 |
0 |
T16 |
1537 |
27 |
0 |
0 |
T17 |
1384 |
3 |
0 |
0 |
T18 |
1682 |
0 |
0 |
0 |
T70 |
0 |
3 |
0 |
0 |
T104 |
0 |
59 |
0 |
0 |
T116 |
0 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T16 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T16 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T16 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T16 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T16 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T16 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164751604 |
0 |
2415 |
T1 |
195049 |
194723 |
0 |
3 |
T2 |
73063 |
73000 |
0 |
3 |
T3 |
260845 |
260709 |
0 |
3 |
T4 |
30340 |
30297 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
101964 |
101853 |
0 |
3 |
T10 |
268215 |
267715 |
0 |
3 |
T16 |
1537 |
1485 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
1682 |
1627 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
19147 |
0 |
0 |
T1 |
195049 |
77 |
0 |
0 |
T2 |
73063 |
0 |
0 |
0 |
T3 |
260845 |
35 |
0 |
0 |
T4 |
30340 |
0 |
0 |
0 |
T5 |
2034 |
28 |
0 |
0 |
T9 |
101964 |
0 |
0 |
0 |
T10 |
268215 |
0 |
0 |
0 |
T12 |
0 |
430 |
0 |
0 |
T13 |
0 |
56 |
0 |
0 |
T16 |
1537 |
8 |
0 |
0 |
T17 |
1384 |
4 |
0 |
0 |
T18 |
1682 |
0 |
0 |
0 |
T70 |
0 |
24 |
0 |
0 |
T71 |
0 |
32 |
0 |
0 |
T104 |
0 |
39 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
594695424 |
0 |
0 |
T1 |
714201 |
713707 |
0 |
0 |
T2 |
152212 |
152144 |
0 |
0 |
T3 |
103918 |
103887 |
0 |
0 |
T4 |
120420 |
120337 |
0 |
0 |
T5 |
2119 |
2036 |
0 |
0 |
T9 |
212421 |
212294 |
0 |
0 |
T10 |
270924 |
270654 |
0 |
0 |
T16 |
6151 |
6053 |
0 |
0 |
T17 |
1384 |
1315 |
0 |
0 |
T18 |
6732 |
6606 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
594695424 |
0 |
0 |
T1 |
714201 |
713707 |
0 |
0 |
T2 |
152212 |
152144 |
0 |
0 |
T3 |
103918 |
103887 |
0 |
0 |
T4 |
120420 |
120337 |
0 |
0 |
T5 |
2119 |
2036 |
0 |
0 |
T9 |
212421 |
212294 |
0 |
0 |
T10 |
270924 |
270654 |
0 |
0 |
T16 |
6151 |
6053 |
0 |
0 |
T17 |
1384 |
1315 |
0 |
0 |
T18 |
6732 |
6606 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563723717 |
561649076 |
0 |
0 |
T1 |
691371 |
690893 |
0 |
0 |
T2 |
146119 |
146053 |
0 |
0 |
T3 |
996431 |
996139 |
0 |
0 |
T4 |
86802 |
86722 |
0 |
0 |
T5 |
2034 |
1954 |
0 |
0 |
T9 |
203917 |
203796 |
0 |
0 |
T10 |
260078 |
259820 |
0 |
0 |
T16 |
5904 |
5811 |
0 |
0 |
T17 |
1329 |
1263 |
0 |
0 |
T18 |
6463 |
6342 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
563723717 |
561649076 |
0 |
0 |
T1 |
691371 |
690893 |
0 |
0 |
T2 |
146119 |
146053 |
0 |
0 |
T3 |
996431 |
996139 |
0 |
0 |
T4 |
86802 |
86722 |
0 |
0 |
T5 |
2034 |
1954 |
0 |
0 |
T9 |
203917 |
203796 |
0 |
0 |
T10 |
260078 |
259820 |
0 |
0 |
T16 |
5904 |
5811 |
0 |
0 |
T17 |
1329 |
1263 |
0 |
0 |
T18 |
6463 |
6342 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
281135629 |
281135629 |
0 |
0 |
T1 |
346396 |
346396 |
0 |
0 |
T2 |
73027 |
73027 |
0 |
0 |
T3 |
498111 |
498111 |
0 |
0 |
T4 |
43361 |
43361 |
0 |
0 |
T5 |
1006 |
1006 |
0 |
0 |
T9 |
101898 |
101898 |
0 |
0 |
T10 |
129911 |
129911 |
0 |
0 |
T16 |
3146 |
3146 |
0 |
0 |
T17 |
639 |
639 |
0 |
0 |
T18 |
3171 |
3171 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
281135629 |
281135629 |
0 |
0 |
T1 |
346396 |
346396 |
0 |
0 |
T2 |
73027 |
73027 |
0 |
0 |
T3 |
498111 |
498111 |
0 |
0 |
T4 |
43361 |
43361 |
0 |
0 |
T5 |
1006 |
1006 |
0 |
0 |
T9 |
101898 |
101898 |
0 |
0 |
T10 |
129911 |
129911 |
0 |
0 |
T16 |
3146 |
3146 |
0 |
0 |
T17 |
639 |
639 |
0 |
0 |
T18 |
3171 |
3171 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
140567247 |
140567247 |
0 |
0 |
T1 |
173196 |
173196 |
0 |
0 |
T2 |
36513 |
36513 |
0 |
0 |
T3 |
249055 |
249055 |
0 |
0 |
T4 |
21681 |
21681 |
0 |
0 |
T5 |
502 |
502 |
0 |
0 |
T9 |
50949 |
50949 |
0 |
0 |
T10 |
64955 |
64955 |
0 |
0 |
T16 |
1572 |
1572 |
0 |
0 |
T17 |
319 |
319 |
0 |
0 |
T18 |
1586 |
1586 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
140567247 |
140567247 |
0 |
0 |
T1 |
173196 |
173196 |
0 |
0 |
T2 |
36513 |
36513 |
0 |
0 |
T3 |
249055 |
249055 |
0 |
0 |
T4 |
21681 |
21681 |
0 |
0 |
T5 |
502 |
502 |
0 |
0 |
T9 |
50949 |
50949 |
0 |
0 |
T10 |
64955 |
64955 |
0 |
0 |
T16 |
1572 |
1572 |
0 |
0 |
T17 |
319 |
319 |
0 |
0 |
T18 |
1586 |
1586 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
286531413 |
285487715 |
0 |
0 |
T1 |
337062 |
336823 |
0 |
0 |
T2 |
73063 |
73030 |
0 |
0 |
T3 |
500255 |
500109 |
0 |
0 |
T4 |
54921 |
54881 |
0 |
0 |
T5 |
1017 |
978 |
0 |
0 |
T9 |
101964 |
101904 |
0 |
0 |
T10 |
130045 |
129916 |
0 |
0 |
T16 |
2952 |
2905 |
0 |
0 |
T17 |
664 |
631 |
0 |
0 |
T18 |
3232 |
3172 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
286531413 |
285487715 |
0 |
0 |
T1 |
337062 |
336823 |
0 |
0 |
T2 |
73063 |
73030 |
0 |
0 |
T3 |
500255 |
500109 |
0 |
0 |
T4 |
54921 |
54881 |
0 |
0 |
T5 |
1017 |
978 |
0 |
0 |
T9 |
101964 |
101904 |
0 |
0 |
T10 |
130045 |
129916 |
0 |
0 |
T16 |
2952 |
2905 |
0 |
0 |
T17 |
664 |
631 |
0 |
0 |
T18 |
3232 |
3172 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164751604 |
0 |
2415 |
T1 |
195049 |
194723 |
0 |
3 |
T2 |
73063 |
73000 |
0 |
3 |
T3 |
260845 |
260709 |
0 |
3 |
T4 |
30340 |
30297 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
101964 |
101853 |
0 |
3 |
T10 |
268215 |
267715 |
0 |
3 |
T16 |
1537 |
1485 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
1682 |
1627 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164751604 |
0 |
2415 |
T1 |
195049 |
194723 |
0 |
3 |
T2 |
73063 |
73000 |
0 |
3 |
T3 |
260845 |
260709 |
0 |
3 |
T4 |
30340 |
30297 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
101964 |
101853 |
0 |
3 |
T10 |
268215 |
267715 |
0 |
3 |
T16 |
1537 |
1485 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
1682 |
1627 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164751604 |
0 |
2415 |
T1 |
195049 |
194723 |
0 |
3 |
T2 |
73063 |
73000 |
0 |
3 |
T3 |
260845 |
260709 |
0 |
3 |
T4 |
30340 |
30297 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
101964 |
101853 |
0 |
3 |
T10 |
268215 |
267715 |
0 |
3 |
T16 |
1537 |
1485 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
1682 |
1627 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164751604 |
0 |
2415 |
T1 |
195049 |
194723 |
0 |
3 |
T2 |
73063 |
73000 |
0 |
3 |
T3 |
260845 |
260709 |
0 |
3 |
T4 |
30340 |
30297 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
101964 |
101853 |
0 |
3 |
T10 |
268215 |
267715 |
0 |
3 |
T16 |
1537 |
1485 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
1682 |
1627 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164751604 |
0 |
2415 |
T1 |
195049 |
194723 |
0 |
3 |
T2 |
73063 |
73000 |
0 |
3 |
T3 |
260845 |
260709 |
0 |
3 |
T4 |
30340 |
30297 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
101964 |
101853 |
0 |
3 |
T10 |
268215 |
267715 |
0 |
3 |
T16 |
1537 |
1485 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
1682 |
1627 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164751604 |
0 |
2415 |
T1 |
195049 |
194723 |
0 |
3 |
T2 |
73063 |
73000 |
0 |
3 |
T3 |
260845 |
260709 |
0 |
3 |
T4 |
30340 |
30297 |
0 |
3 |
T5 |
2034 |
1896 |
0 |
3 |
T9 |
101964 |
101853 |
0 |
3 |
T10 |
268215 |
267715 |
0 |
3 |
T16 |
1537 |
1485 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
1682 |
1627 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
164758517 |
0 |
0 |
T1 |
195049 |
194747 |
0 |
0 |
T2 |
73063 |
73003 |
0 |
0 |
T3 |
260845 |
260711 |
0 |
0 |
T4 |
30340 |
30300 |
0 |
0 |
T5 |
2034 |
1899 |
0 |
0 |
T9 |
101964 |
101856 |
0 |
0 |
T10 |
268215 |
267724 |
0 |
0 |
T16 |
1537 |
1488 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
1682 |
1630 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592400119 |
0 |
2415 |
T1 |
714201 |
712954 |
0 |
3 |
T2 |
152212 |
152083 |
0 |
3 |
T3 |
103918 |
103864 |
0 |
3 |
T4 |
120420 |
120248 |
0 |
3 |
T5 |
2119 |
1976 |
0 |
3 |
T9 |
212421 |
212191 |
0 |
3 |
T10 |
270924 |
270418 |
0 |
3 |
T16 |
6151 |
5950 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
6732 |
6518 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
34115 |
0 |
0 |
T1 |
714201 |
137 |
0 |
0 |
T2 |
152212 |
1 |
0 |
0 |
T3 |
103918 |
112 |
0 |
0 |
T4 |
120420 |
1 |
0 |
0 |
T5 |
2119 |
8 |
0 |
0 |
T9 |
212421 |
1 |
0 |
0 |
T10 |
270924 |
18 |
0 |
0 |
T16 |
6151 |
15 |
0 |
0 |
T17 |
1384 |
5 |
0 |
0 |
T18 |
6732 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592400119 |
0 |
2415 |
T1 |
714201 |
712954 |
0 |
3 |
T2 |
152212 |
152083 |
0 |
3 |
T3 |
103918 |
103864 |
0 |
3 |
T4 |
120420 |
120248 |
0 |
3 |
T5 |
2119 |
1976 |
0 |
3 |
T9 |
212421 |
212191 |
0 |
3 |
T10 |
270924 |
270418 |
0 |
3 |
T16 |
6151 |
5950 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
6732 |
6518 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
34309 |
0 |
0 |
T1 |
714201 |
139 |
0 |
0 |
T2 |
152212 |
1 |
0 |
0 |
T3 |
103918 |
109 |
0 |
0 |
T4 |
120420 |
1 |
0 |
0 |
T5 |
2119 |
17 |
0 |
0 |
T9 |
212421 |
1 |
0 |
0 |
T10 |
270924 |
30 |
0 |
0 |
T16 |
6151 |
13 |
0 |
0 |
T17 |
1384 |
3 |
0 |
0 |
T18 |
6732 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592400119 |
0 |
2415 |
T1 |
714201 |
712954 |
0 |
3 |
T2 |
152212 |
152083 |
0 |
3 |
T3 |
103918 |
103864 |
0 |
3 |
T4 |
120420 |
120248 |
0 |
3 |
T5 |
2119 |
1976 |
0 |
3 |
T9 |
212421 |
212191 |
0 |
3 |
T10 |
270924 |
270418 |
0 |
3 |
T16 |
6151 |
5950 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
6732 |
6518 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
34451 |
0 |
0 |
T1 |
714201 |
171 |
0 |
0 |
T2 |
152212 |
1 |
0 |
0 |
T3 |
103918 |
90 |
0 |
0 |
T4 |
120420 |
1 |
0 |
0 |
T5 |
2119 |
14 |
0 |
0 |
T9 |
212421 |
1 |
0 |
0 |
T10 |
270924 |
26 |
0 |
0 |
T16 |
6151 |
9 |
0 |
0 |
T17 |
1384 |
5 |
0 |
0 |
T18 |
6732 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T5,T4 |
1 | Covered | T1,T5,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T4 |
0 |
Covered |
T1,T5,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592400119 |
0 |
2415 |
T1 |
714201 |
712954 |
0 |
3 |
T2 |
152212 |
152083 |
0 |
3 |
T3 |
103918 |
103864 |
0 |
3 |
T4 |
120420 |
120248 |
0 |
3 |
T5 |
2119 |
1976 |
0 |
3 |
T9 |
212421 |
212191 |
0 |
3 |
T10 |
270924 |
270418 |
0 |
3 |
T16 |
6151 |
5950 |
0 |
3 |
T17 |
1384 |
1197 |
0 |
3 |
T18 |
6732 |
6518 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
34380 |
0 |
0 |
T1 |
714201 |
148 |
0 |
0 |
T2 |
152212 |
1 |
0 |
0 |
T3 |
103918 |
108 |
0 |
0 |
T4 |
120420 |
1 |
0 |
0 |
T5 |
2119 |
12 |
0 |
0 |
T9 |
212421 |
1 |
0 |
0 |
T10 |
270924 |
37 |
0 |
0 |
T16 |
6151 |
11 |
0 |
0 |
T17 |
1384 |
5 |
0 |
0 |
T18 |
6732 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
596868204 |
592406939 |
0 |
0 |
T1 |
714201 |
712978 |
0 |
0 |
T2 |
152212 |
152086 |
0 |
0 |
T3 |
103918 |
103864 |
0 |
0 |
T4 |
120420 |
120251 |
0 |
0 |
T5 |
2119 |
1979 |
0 |
0 |
T9 |
212421 |
212194 |
0 |
0 |
T10 |
270924 |
270427 |
0 |
0 |
T16 |
6151 |
5953 |
0 |
0 |
T17 |
1384 |
1200 |
0 |
0 |
T18 |
6732 |
6521 |
0 |
0 |