Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T4
0	1	Unreachable
1	0	Covered	T1,T3,T10

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	167143511	164629052	0	0
AllClkBypReqTrue_A	167143511	127203	0	0
IoClkBypReqFalse_A	167143511	164549980	0	2415
IoClkBypReqTrue_A	167143511	201751	0	0
LcClkBypAckFalse_A	167143511	164638074	0	0
LcClkBypAckTrue_A	167143511	118181	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	164629052	0	0
T1	195049	194197	0	0
T2	73063	73002	0	0
T3	260845	260691	0	0
T4	30340	30299	0	0
T5	2034	1821	0	0
T9	101964	101855	0	0
T10	268215	267721	0	0
T16	1537	1487	0	0
T17	1384	1195	0	0
T18	1682	1629	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	127203	0	0
T1	195049	542	0	0
T2	73063	0	0	0
T3	260845	192	0	0
T4	30340	0	0	0
T5	2034	77	0	0
T9	101964	0	0	0
T10	268215	0	0	0
T12	0	2070	0	0
T13	0	511	0	0
T14	0	1405	0	0
T16	1537	0	0	0
T17	1384	4	0	0
T18	1682	0	0	0
T70	0	140	0	0
T71	0	152	0	0
T104	0	186	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	164549980	0	2415
T1	195049	194138	0	3
T2	73063	73000	0	3
T3	260845	260678	0	3
T4	30340	30297	0	3
T5	2034	1896	0	3
T9	101964	101853	0	3
T10	268215	267715	0	3
T16	1537	1219	0	3
T17	1384	1173	0	3
T18	1682	1627	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	201751	0	0
T1	195049	585	0	0
T2	73063	0	0	0
T3	260845	312	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	0	0	0
T10	268215	0	0	0
T12	0	3491	0	0
T13	0	672	0	0
T14	0	2441	0	0
T16	1537	266	0	0
T17	1384	24	0	0
T18	1682	0	0	0
T70	0	29	0	0
T104	0	414	0	0
T116	0	85	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	164638074	0	0
T1	195049	194348	0	0
T2	73063	73002	0	0
T3	260845	260692	0	0
T4	30340	30299	0	0
T5	2034	1898	0	0
T9	101964	101855	0	0
T10	268215	267721	0	0
T16	1537	1380	0	0
T17	1384	1199	0	0
T18	1682	1629	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167143511	118181	0	0
T1	195049	391	0	0
T2	73063	0	0	0
T3	260845	180	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	0	0	0
T10	268215	0	0	0
T12	0	2008	0	0
T13	0	366	0	0
T14	0	1412	0	0
T16	1537	107	0	0
T17	1384	0	0	0
T18	1682	0	0	0
T70	0	26	0	0
T104	0	221	0	0
T116	0	60	0	0
T117	0	47	0	0