Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16698	0	0
TransStop_A	2147483647	8566	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16698	0	0
T1	2856804	80	0	0
T2	608848	0	0	0
T3	415672	58	0	0
T4	481684	0	0	0
T5	8476	0	0	0
T9	849688	0	0	0
T10	1083700	32	0	0
T11	0	61	0	0
T12	0	309	0	0
T13	0	215	0	0
T14	0	448	0	0
T16	24608	0	0	0
T17	5540	0	0	0
T18	26932	4	0	0
T72	0	4	0	0
T118	0	21	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8566	0	0
T1	2856804	36	0	0
T2	608848	0	0	0
T3	415672	22	0	0
T4	481684	0	0	0
T5	8476	0	0	0
T9	849688	0	0	0
T10	1083700	12	0	0
T11	0	44	0	0
T12	0	147	0	0
T13	0	107	0	0
T14	0	248	0	0
T16	24608	0	0	0
T17	5540	0	0	0
T18	26932	4	0	0
T72	0	4	0	0
T118	0	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	596868624	4197	0	0
TransStop_A	596868624	2129	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868624	4197	0	0
T1	714201	22	0	0
T2	152212	0	0	0
T3	103918	13	0	0
T4	120421	0	0	0
T5	2119	0	0	0
T9	212422	0	0	0
T10	270925	7	0	0
T11	0	19	0	0
T12	0	77	0	0
T13	0	47	0	0
T14	0	113	0	0
T16	6152	0	0	0
T17	1385	0	0	0
T18	6733	1	0	0
T72	0	1	0	0
T118	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868624	2129	0	0
T1	714201	14	0	0
T2	152212	0	0	0
T3	103918	5	0	0
T4	120421	0	0	0
T5	2119	0	0	0
T9	212422	0	0	0
T10	270925	2	0	0
T11	0	13	0	0
T12	0	34	0	0
T13	0	20	0	0
T14	0	55	0	0
T16	6152	0	0	0
T17	1385	0	0	0
T18	6733	1	0	0
T72	0	1	0	0
T118	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	596868624	4050	0	0
TransStop_A	596868624	2050	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868624	4050	0	0
T1	714201	25	0	0
T2	152212	0	0	0
T3	103918	14	0	0
T4	120421	0	0	0
T5	2119	0	0	0
T9	212422	0	0	0
T10	270925	7	0	0
T11	0	11	0	0
T12	0	71	0	0
T13	0	51	0	0
T14	0	117	0	0
T16	6152	0	0	0
T17	1385	0	0	0
T18	6733	1	0	0
T72	0	1	0	0
T118	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868624	2050	0	0
T1	714201	9	0	0
T2	152212	0	0	0
T3	103918	6	0	0
T4	120421	0	0	0
T5	2119	0	0	0
T9	212422	0	0	0
T10	270925	3	0	0
T11	0	8	0	0
T12	0	33	0	0
T13	0	23	0	0
T14	0	65	0	0
T16	6152	0	0	0
T17	1385	0	0	0
T18	6733	1	0	0
T72	0	1	0	0
T118	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	596868624	4211	0	0
TransStop_A	596868624	2173	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868624	4211	0	0
T1	714201	16	0	0
T2	152212	0	0	0
T3	103918	15	0	0
T4	120421	0	0	0
T5	2119	0	0	0
T9	212422	0	0	0
T10	270925	8	0	0
T11	0	17	0	0
T12	0	81	0	0
T13	0	59	0	0
T14	0	105	0	0
T16	6152	0	0	0
T17	1385	0	0	0
T18	6733	1	0	0
T72	0	1	0	0
T118	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868624	2173	0	0
T1	714201	5	0	0
T2	152212	0	0	0
T3	103918	6	0	0
T4	120421	0	0	0
T5	2119	0	0	0
T9	212422	0	0	0
T10	270925	3	0	0
T11	0	12	0	0
T12	0	40	0	0
T13	0	30	0	0
T14	0	59	0	0
T16	6152	0	0	0
T17	1385	0	0	0
T18	6733	1	0	0
T72	0	1	0	0
T118	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	596868624	4240	0	0
TransStop_A	596868624	2214	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868624	4240	0	0
T1	714201	17	0	0
T2	152212	0	0	0
T3	103918	16	0	0
T4	120421	0	0	0
T5	2119	0	0	0
T9	212422	0	0	0
T10	270925	10	0	0
T11	0	14	0	0
T12	0	80	0	0
T13	0	58	0	0
T14	0	113	0	0
T16	6152	0	0	0
T17	1385	0	0	0
T18	6733	1	0	0
T72	0	1	0	0
T118	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868624	2214	0	0
T1	714201	8	0	0
T2	152212	0	0	0
T3	103918	5	0	0
T4	120421	0	0	0
T5	2119	0	0	0
T9	212422	0	0	0
T10	270925	4	0	0
T11	0	11	0	0
T12	0	40	0	0
T13	0	34	0	0
T14	0	69	0	0
T16	6152	0	0	0
T17	1385	0	0	0
T18	6733	1	0	0
T72	0	1	0	0
T118	0	2	0	0