Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T5,T4
10CoveredT1,T5,T16 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T5,T16
11CoveredT1,T5,T16 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T5,T16
10CoveredT1,T5,T4
11CoveredT1,T5,T4
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 702527959 702525544 0 0
selKnown1 1691171151 1691168736 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 702527959 702525544 0 0
T1 865040 865037 0 0
T2 182567 182564 0 0
T3 1245235 1245234 0 0
T4 108403 108400 0 0
T5 2485 2482 0 0
T9 254745 254742 0 0
T10 324777 324774 0 0
T16 7624 7621 0 0
T17 1590 1587 0 0
T18 7928 7925 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1691171151 1691168736 0 0
T1 2074113 2074110 0 0
T2 438357 438354 0 0
T3 2989293 2989293 0 0
T4 260406 260403 0 0
T5 6102 6099 0 0
T9 611751 611748 0 0
T10 780234 780231 0 0
T16 17712 17709 0 0
T17 3987 3984 0 0
T18 19389 19386 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T5,T4
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T4
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T5,T4
11CoveredT1,T5,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 281135629 281134824 0 0
selKnown1 563723717 563722912 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 281135629 281134824 0 0
T1 346396 346395 0 0
T2 73027 73026 0 0
T3 498111 498110 0 0
T4 43361 43360 0 0
T5 1006 1005 0 0
T9 101898 101897 0 0
T10 129911 129910 0 0
T16 3146 3145 0 0
T17 639 638 0 0
T18 3171 3170 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 563723717 563722912 0 0
T1 691371 691370 0 0
T2 146119 146118 0 0
T3 996431 996431 0 0
T4 86802 86801 0 0
T5 2034 2033 0 0
T9 203917 203916 0 0
T10 260078 260077 0 0
T16 5904 5903 0 0
T17 1329 1328 0 0
T18 6463 6462 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T5,T4
10CoveredT1,T5,T16 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T5,T16
11CoveredT1,T5,T16 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T5,T16
10CoveredT1,T5,T4
11CoveredT1,T5,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 280825083 280824278 0 0
selKnown1 563723717 563722912 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 280825083 280824278 0 0
T1 345448 345447 0 0
T2 73027 73026 0 0
T3 498069 498069 0 0
T4 43361 43360 0 0
T5 977 976 0 0
T9 101898 101897 0 0
T10 129911 129910 0 0
T16 2906 2905 0 0
T17 632 631 0 0
T18 3171 3170 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 563723717 563722912 0 0
T1 691371 691370 0 0
T2 146119 146118 0 0
T3 996431 996431 0 0
T4 86802 86801 0 0
T5 2034 2033 0 0
T9 203917 203916 0 0
T10 260078 260077 0 0
T16 5904 5903 0 0
T17 1329 1328 0 0
T18 6463 6462 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T5,T4
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T4
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T5,T4
11CoveredT1,T5,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 140567247 140566442 0 0
selKnown1 563723717 563722912 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 140567247 140566442 0 0
T1 173196 173195 0 0
T2 36513 36512 0 0
T3 249055 249055 0 0
T4 21681 21680 0 0
T5 502 501 0 0
T9 50949 50948 0 0
T10 64955 64954 0 0
T16 1572 1571 0 0
T17 319 318 0 0
T18 1586 1585 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 563723717 563722912 0 0
T1 691371 691370 0 0
T2 146119 146118 0 0
T3 996431 996431 0 0
T4 86802 86801 0 0
T5 2034 2033 0 0
T9 203917 203916 0 0
T10 260078 260077 0 0
T16 5904 5903 0 0
T17 1329 1328 0 0
T18 6463 6462 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%