Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	168103192	5625910	0	0
clk_enables_rd_A	168103192	40091	0	0
clk_hints_rd_A	168103192	36902	0	0
extclk_ctrl_rd_A	168103192	45893	0	0
extclk_ctrl_regwen_rd_A	168103192	34206	0	0
jitter_enable_rd_A	168103192	49723	0	0
jitter_regwen_rd_A	168103192	38507	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168103192	5625910	0	0
T3	260845	125652	0	0
T9	101964	0	0	0
T10	268215	0	0	0
T11	144483	0	0	0
T12	0	142407	0	0
T13	0	60404	0	0
T14	0	154442	0	0
T17	1384	0	0	0
T18	1682	0	0	0
T19	20994	0	0	0
T22	0	86046	0	0
T65	0	111883	0	0
T66	0	137518	0	0
T67	0	113072	0	0
T68	0	174968	0	0
T69	0	10422	0	0
T70	1825	0	0	0
T71	1868	0	0	0
T72	2122	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168103192	40091	0	0
T9	101964	0	0	0
T10	268215	0	0	0
T11	144483	0	0	0
T13	0	1202	0	0
T18	1682	6	0	0
T19	20994	0	0	0
T20	188120	0	0	0
T66	0	5029	0	0
T68	0	3883	0	0
T70	1825	0	0	0
T71	1868	0	0	0
T72	2122	0	0	0
T77	0	6	0	0
T104	2430	0	0	0
T139	0	1273	0	0
T140	0	1057	0	0
T141	0	1	0	0
T142	0	10	0	0
T143	0	5	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168103192	36902	0	0
T1	195049	9	0	0
T2	73063	0	0	0
T3	260845	0	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	0	0	0
T10	268215	0	0	0
T13	0	1202	0	0
T16	1537	0	0	0
T17	1384	0	0	0
T18	1682	1	0	0
T66	0	4859	0	0
T68	0	3186	0	0
T77	0	7	0	0
T139	0	1091	0	0
T140	0	866	0	0
T141	0	4	0	0
T144	0	7	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168103192	45893	0	0
T1	195049	54	0	0
T2	73063	0	0	0
T3	260845	0	0	0
T4	30340	0	0	0
T5	2034	21	0	0
T9	101964	0	0	0
T10	268215	0	0	0
T13	0	1204	0	0
T16	1537	0	0	0
T17	1384	0	0	0
T18	1682	0	0	0
T71	0	38	0	0
T74	0	21	0	0
T90	0	48	0	0
T145	0	4	0	0
T146	0	26	0	0
T147	0	6	0	0
T148	0	22	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168103192	34206	0	0
T13	202177	885	0	0
T14	309726	0	0	0
T15	63142	0	0	0
T21	17405	0	0	0
T25	1118	0	0	0
T66	0	4608	0	0
T68	0	3183	0	0
T78	0	15	0	0
T116	1629	0	0	0
T117	1239	0	0	0
T118	1713	0	0	0
T139	0	1192	0	0
T140	0	1027	0	0
T149	0	49	0	0
T150	0	19	0	0
T151	0	49	0	0
T152	0	34	0	0
T153	547	0	0	0
T154	2241	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168103192	49723	0	0
T1	195049	72	0	0
T2	73063	0	0	0
T3	260845	0	0	0
T4	30340	0	0	0
T5	2034	0	0	0
T9	101964	0	0	0
T10	268215	0	0	0
T13	0	1325	0	0
T16	1537	0	0	0
T17	1384	0	0	0
T18	1682	133	0	0
T66	0	6092	0	0
T68	0	3585	0	0
T77	0	132	0	0
T139	0	1689	0	0
T140	0	929	0	0
T141	0	144	0	0
T144	0	51	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168103192	38507	0	0
T13	202177	1231	0	0
T14	309726	0	0	0
T15	63142	0	0	0
T21	17405	0	0	0
T25	1118	0	0	0
T66	0	5334	0	0
T68	0	3296	0	0
T116	1629	0	0	0
T117	1239	0	0	0
T118	1713	0	0	0
T139	0	1304	0	0
T140	0	1062	0	0
T153	547	0	0	0
T154	2241	0	0	0
T155	0	2391	0	0
T156	0	4083	0	0
T157	0	1851	0	0
T158	0	2569	0	0
T159	0	1165	0	0