Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T16
1	1	Covered	T1,T5,T16

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	563724158	4354	0	0
g_div2.Div2Whole_A	563724158	5154	0	0
g_div4.Div4Stepped_A	281136032	4259	0	0
g_div4.Div4Whole_A	281136032	4964	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563724158	4354	0	0
T1	691371	15	0	0
T2	146119	0	0	0
T3	996431	8	0	0
T4	86803	0	0	0
T5	2035	1	0	0
T9	203918	0	0	0
T10	260079	0	0	0
T12	0	100	0	0
T13	0	9	0	0
T14	0	78	0	0
T16	5905	7	0	0
T17	1329	0	0	0
T18	6463	0	0	0
T70	0	1	0	0
T71	0	6	0	0
T104	0	11	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563724158	5154	0	0
T1	691371	15	0	0
T2	146119	0	0	0
T3	996431	8	0	0
T4	86803	0	0	0
T5	2035	4	0	0
T9	203918	0	0	0
T10	260079	0	0	0
T12	0	111	0	0
T13	0	12	0	0
T16	5905	7	0	0
T17	1329	1	0	0
T18	6463	0	0	0
T70	0	6	0	0
T71	0	6	0	0
T104	0	11	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281136032	4259	0	0
T1	346396	15	0	0
T2	73027	0	0	0
T3	498111	8	0	0
T4	43362	0	0	0
T5	1007	1	0	0
T9	101899	0	0	0
T10	129911	0	0	0
T12	0	99	0	0
T13	0	9	0	0
T14	0	78	0	0
T16	3146	7	0	0
T17	639	0	0	0
T18	3172	0	0	0
T70	0	1	0	0
T71	0	6	0	0
T104	0	11	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281136032	4964	0	0
T1	346396	15	0	0
T2	73027	0	0	0
T3	498111	8	0	0
T4	43362	0	0	0
T5	1007	4	0	0
T9	101899	0	0	0
T10	129911	0	0	0
T12	0	110	0	0
T13	0	12	0	0
T14	0	95	0	0
T16	3146	7	0	0
T17	639	0	0	0
T18	3172	0	0	0
T70	0	6	0	0
T71	0	6	0	0
T104	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T16
1	1	Covered	T1,T5,T16

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	563724158	4354	0	0
g_div2.Div2Whole_A	563724158	5154	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563724158	4354	0	0
T1	691371	15	0	0
T2	146119	0	0	0
T3	996431	8	0	0
T4	86803	0	0	0
T5	2035	1	0	0
T9	203918	0	0	0
T10	260079	0	0	0
T12	0	100	0	0
T13	0	9	0	0
T14	0	78	0	0
T16	5905	7	0	0
T17	1329	0	0	0
T18	6463	0	0	0
T70	0	1	0	0
T71	0	6	0	0
T104	0	11	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563724158	5154	0	0
T1	691371	15	0	0
T2	146119	0	0	0
T3	996431	8	0	0
T4	86803	0	0	0
T5	2035	4	0	0
T9	203918	0	0	0
T10	260079	0	0	0
T12	0	111	0	0
T13	0	12	0	0
T16	5905	7	0	0
T17	1329	1	0	0
T18	6463	0	0	0
T70	0	6	0	0
T71	0	6	0	0
T104	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T4
1	0	Covered	T1,T5,T16
1	1	Covered	T1,T5,T16

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	281136032	4259	0	0
g_div4.Div4Whole_A	281136032	4964	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281136032	4259	0	0
T1	346396	15	0	0
T2	73027	0	0	0
T3	498111	8	0	0
T4	43362	0	0	0
T5	1007	1	0	0
T9	101899	0	0	0
T10	129911	0	0	0
T12	0	99	0	0
T13	0	9	0	0
T14	0	78	0	0
T16	3146	7	0	0
T17	639	0	0	0
T18	3172	0	0	0
T70	0	1	0	0
T71	0	6	0	0
T104	0	11	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281136032	4964	0	0
T1	346396	15	0	0
T2	73027	0	0	0
T3	498111	8	0	0
T4	43362	0	0	0
T5	1007	4	0	0
T9	101899	0	0	0
T10	129911	0	0	0
T12	0	110	0	0
T13	0	12	0	0
T14	0	95	0	0
T16	3146	7	0	0
T17	639	0	0	0
T18	3172	0	0	0
T70	0	6	0	0
T71	0	6	0	0
T104	0	10	0	0