Assert Coverage for Module :
clkmgr_pwrmgr_sva_if
Assertion Details
IoStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
154 |
0 |
0 |
T29 |
1229 |
3 |
0 |
0 |
T30 |
946 |
4 |
0 |
0 |
T31 |
1180 |
4 |
0 |
0 |
T65 |
325426 |
0 |
0 |
0 |
T75 |
219743 |
0 |
0 |
0 |
T76 |
25336 |
0 |
0 |
0 |
T91 |
43492 |
0 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T161 |
0 |
4 |
0 |
0 |
T162 |
0 |
6 |
0 |
0 |
T163 |
0 |
2 |
0 |
0 |
T164 |
0 |
4 |
0 |
0 |
T165 |
0 |
3 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
2068 |
0 |
0 |
0 |
T168 |
1610 |
0 |
0 |
0 |
T169 |
75033 |
0 |
0 |
0 |
IoStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
154 |
0 |
0 |
T29 |
1229 |
3 |
0 |
0 |
T30 |
946 |
4 |
0 |
0 |
T31 |
1180 |
4 |
0 |
0 |
T65 |
325426 |
0 |
0 |
0 |
T75 |
219743 |
0 |
0 |
0 |
T76 |
25336 |
0 |
0 |
0 |
T91 |
43492 |
0 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T161 |
0 |
4 |
0 |
0 |
T162 |
0 |
6 |
0 |
0 |
T163 |
0 |
2 |
0 |
0 |
T164 |
0 |
4 |
0 |
0 |
T165 |
0 |
3 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
2068 |
0 |
0 |
0 |
T168 |
1610 |
0 |
0 |
0 |
T169 |
75033 |
0 |
0 |
0 |
MainStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
147 |
0 |
0 |
T29 |
1229 |
5 |
0 |
0 |
T30 |
946 |
4 |
0 |
0 |
T31 |
1180 |
2 |
0 |
0 |
T65 |
325426 |
0 |
0 |
0 |
T75 |
219743 |
0 |
0 |
0 |
T76 |
25336 |
0 |
0 |
0 |
T91 |
43492 |
0 |
0 |
0 |
T160 |
0 |
3 |
0 |
0 |
T161 |
0 |
3 |
0 |
0 |
T162 |
0 |
5 |
0 |
0 |
T163 |
0 |
1 |
0 |
0 |
T164 |
0 |
3 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T167 |
2068 |
0 |
0 |
0 |
T168 |
1610 |
0 |
0 |
0 |
T169 |
75033 |
0 |
0 |
0 |
T170 |
0 |
5 |
0 |
0 |
MainStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
147 |
0 |
0 |
T29 |
1229 |
5 |
0 |
0 |
T30 |
946 |
4 |
0 |
0 |
T31 |
1180 |
2 |
0 |
0 |
T65 |
325426 |
0 |
0 |
0 |
T75 |
219743 |
0 |
0 |
0 |
T76 |
25336 |
0 |
0 |
0 |
T91 |
43492 |
0 |
0 |
0 |
T160 |
0 |
3 |
0 |
0 |
T161 |
0 |
3 |
0 |
0 |
T162 |
0 |
5 |
0 |
0 |
T163 |
0 |
1 |
0 |
0 |
T164 |
0 |
3 |
0 |
0 |
T165 |
0 |
1 |
0 |
0 |
T167 |
2068 |
0 |
0 |
0 |
T168 |
1610 |
0 |
0 |
0 |
T169 |
75033 |
0 |
0 |
0 |
T170 |
0 |
5 |
0 |
0 |
UsbStatusFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
142 |
0 |
0 |
T29 |
1229 |
4 |
0 |
0 |
T30 |
946 |
3 |
0 |
0 |
T31 |
1180 |
3 |
0 |
0 |
T65 |
325426 |
0 |
0 |
0 |
T75 |
219743 |
0 |
0 |
0 |
T76 |
25336 |
0 |
0 |
0 |
T91 |
43492 |
0 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T161 |
0 |
2 |
0 |
0 |
T162 |
0 |
4 |
0 |
0 |
T163 |
0 |
1 |
0 |
0 |
T164 |
0 |
4 |
0 |
0 |
T165 |
0 |
2 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
2068 |
0 |
0 |
0 |
T168 |
1610 |
0 |
0 |
0 |
T169 |
75033 |
0 |
0 |
0 |
UsbStatusRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167143511 |
142 |
0 |
0 |
T29 |
1229 |
4 |
0 |
0 |
T30 |
946 |
3 |
0 |
0 |
T31 |
1180 |
3 |
0 |
0 |
T65 |
325426 |
0 |
0 |
0 |
T75 |
219743 |
0 |
0 |
0 |
T76 |
25336 |
0 |
0 |
0 |
T91 |
43492 |
0 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T161 |
0 |
2 |
0 |
0 |
T162 |
0 |
4 |
0 |
0 |
T163 |
0 |
1 |
0 |
0 |
T164 |
0 |
4 |
0 |
0 |
T165 |
0 |
2 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
2068 |
0 |
0 |
0 |
T168 |
1610 |
0 |
0 |
0 |
T169 |
75033 |
0 |
0 |
0 |