Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50149	0	0
CgEnOn_A	2147483647	41103	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50149	0	0
T1	2639365	144	0	0
T2	560083	3	0	0
T3	1951433	57	0	0
T4	392684	3	0	0
T5	7780	3	0	0
T9	781606	3	0	0
T10	996792	16	0	0
T11	0	19	0	0
T16	22924	3	0	0
T17	5055	3	0	0
T18	24684	7	0	0
T22	2334998	5	0	0
T29	2257	15	0	0
T30	0	20	0	0
T31	0	20	0	0
T73	1071871	0	0	0
T74	5097	0	0	0
T86	3114	0	0	0
T87	99973	0	0	0
T88	4453	0	0	0
T89	23092	0	0	0
T160	0	25	0	0
T161	0	20	0	0
T162	0	30	0	0
T163	0	10	0	0
T164	0	20	0	0
T165	0	15	0	0
T171	3500	0	0	0
T172	2742	0	0	0
T173	46612	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41103	0	0
T1	519592	65	0	0
T2	109540	0	0	0
T3	747166	18	0	0
T4	65042	0	0	0
T5	1508	0	0	0
T9	152847	0	0	0
T10	194866	0	0	0
T12	0	309	0	0
T13	0	78	0	0
T14	0	237	0	0
T16	4718	0	0	0
T17	958	0	0	0
T18	4757	2	0	0
T22	2160994	2	0	0
T29	2153	6	0	0
T30	0	8	0	0
T31	0	8	0	0
T72	0	1	0	0
T73	595649	0	0	0
T74	2899	0	0	0
T86	1670	0	0	0
T87	55489	0	0	0
T88	2470	0	0	0
T89	13290	0	0	0
T153	0	9	0	0
T160	0	10	0	0
T161	0	8	0	0
T162	0	12	0	0
T163	0	4	0	0
T164	0	8	0	0
T165	0	6	0	0
T171	1961	0	0	0
T172	1484	0	0	0
T173	26761	0	0	0
T174	0	9	0	0
T175	0	2	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	281135629	159	0	0
CgEnOn_A	281135629	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281135629	159	0	0
T22	864400	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	238262	0	0	0
T74	1159	0	0	0
T86	668	0	0	0
T87	22195	0	0	0
T88	988	0	0	0
T89	5316	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	785	0	0	0
T172	593	0	0	0
T173	10705	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281135629	159	0	0
T22	864400	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	238262	0	0	0
T74	1159	0	0	0
T86	668	0	0	0
T87	22195	0	0	0
T88	988	0	0	0
T89	5316	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	785	0	0	0
T172	593	0	0	0
T173	10705	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140567247	159	0	0
CgEnOn_A	140567247	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567247	159	0	0
T22	432198	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	119129	0	0	0
T74	580	0	0	0
T86	334	0	0	0
T87	11098	0	0	0
T88	494	0	0	0
T89	2658	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	392	0	0	0
T172	297	0	0	0
T173	5352	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567247	159	0	0
T22	432198	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	119129	0	0	0
T74	580	0	0	0
T86	334	0	0	0
T87	11098	0	0	0
T88	494	0	0	0
T89	2658	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	392	0	0	0
T172	297	0	0	0
T173	5352	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	563723717	159	0	0
CgEnOn_A	563723717	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563723717	159	0	0
T22	174004	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	476222	0	0	0
T74	2198	0	0	0
T86	1444	0	0	0
T87	44484	0	0	0
T88	1983	0	0	0
T89	9802	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	1539	0	0	0
T172	1258	0	0	0
T173	19851	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563723717	155	0	0
T29	2153	3	0	0
T30	3323	4	0	0
T31	4517	4	0	0
T65	607433	0	0	0
T75	215249	0	0	0
T76	93548	0	0	0
T91	66224	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T166	0	1	0	0
T167	1986	0	0	0
T168	25781	0	0	0
T169	480206	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	596868204	148	0	0
CgEnOn_A	596868204	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	148	0	0
T29	2257	5	0	0
T30	3342	4	0	0
T31	4635	2	0	0
T65	644852	0	0	0
T75	224225	0	0	0
T76	97449	0	0	0
T91	80987	0	0	0
T160	0	3	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T167	2068	0	0	0
T168	26857	0	0	0
T169	500231	0	0	0
T170	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	147	0	0
T29	2257	5	0	0
T30	3342	4	0	0
T31	4635	2	0	0
T65	644852	0	0	0
T75	224225	0	0	0
T76	97449	0	0	0
T91	80987	0	0	0
T160	0	3	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T167	2068	0	0	0
T168	26857	0	0	0
T169	500231	0	0	0
T170	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140567247	159	0	0
CgEnOn_A	140567247	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567247	159	0	0
T22	432198	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	119129	0	0	0
T74	580	0	0	0
T86	334	0	0	0
T87	11098	0	0	0
T88	494	0	0	0
T89	2658	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	392	0	0	0
T172	297	0	0	0
T173	5352	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567247	159	0	0
T22	432198	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	119129	0	0	0
T74	580	0	0	0
T86	334	0	0	0
T87	11098	0	0	0
T88	494	0	0	0
T89	2658	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	392	0	0	0
T172	297	0	0	0
T173	5352	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	596868204	148	0	0
CgEnOn_A	596868204	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	148	0	0
T29	2257	5	0	0
T30	3342	4	0	0
T31	4635	2	0	0
T65	644852	0	0	0
T75	224225	0	0	0
T76	97449	0	0	0
T91	80987	0	0	0
T160	0	3	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T167	2068	0	0	0
T168	26857	0	0	0
T169	500231	0	0	0
T170	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	147	0	0
T29	2257	5	0	0
T30	3342	4	0	0
T31	4635	2	0	0
T65	644852	0	0	0
T75	224225	0	0	0
T76	97449	0	0	0
T91	80987	0	0	0
T160	0	3	0	0
T161	0	3	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	1	0	0
T167	2068	0	0	0
T168	26857	0	0	0
T169	500231	0	0	0
T170	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140567247	159	0	0
CgEnOn_A	140567247	159	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567247	159	0	0
T22	432198	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	119129	0	0	0
T74	580	0	0	0
T86	334	0	0	0
T87	11098	0	0	0
T88	494	0	0	0
T89	2658	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	392	0	0	0
T172	297	0	0	0
T173	5352	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567247	159	0	0
T22	432198	1	0	0
T29	0	3	0	0
T30	0	4	0	0
T31	0	4	0	0
T73	119129	0	0	0
T74	580	0	0	0
T86	334	0	0	0
T87	11098	0	0	0
T88	494	0	0	0
T89	2658	0	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	6	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	0	3	0	0
T171	392	0	0	0
T172	297	0	0	0
T173	5352	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	281135629	7958	0	0
CgEnOn_A	281135629	5701	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281135629	7958	0	0
T1	346396	39	0	0
T2	73027	1	0	0
T3	498111	15	0	0
T4	43361	1	0	0
T5	1006	1	0	0
T9	101898	1	0	0
T10	129911	3	0	0
T16	3146	1	0	0
T17	639	1	0	0
T18	3171	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	281135629	5701	0	0
T1	346396	31	0	0
T2	73027	0	0	0
T3	498111	9	0	0
T4	43361	0	0	0
T5	1006	0	0	0
T9	101898	0	0	0
T10	129911	0	0	0
T12	0	155	0	0
T13	0	41	0	0
T14	0	120	0	0
T16	3146	0	0	0
T17	639	0	0	0
T18	3171	1	0	0
T72	0	1	0	0
T153	0	5	0	0
T174	0	5	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	140567247	7895	0	0
CgEnOn_A	140567247	5638	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567247	7895	0	0
T1	173196	42	0	0
T2	36513	1	0	0
T3	249055	15	0	0
T4	21681	1	0	0
T5	502	1	0	0
T9	50949	1	0	0
T10	64955	3	0	0
T16	1572	1	0	0
T17	319	1	0	0
T18	1586	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	140567247	5638	0	0
T1	173196	34	0	0
T2	36513	0	0	0
T3	249055	9	0	0
T4	21681	0	0	0
T5	502	0	0	0
T9	50949	0	0	0
T10	64955	0	0	0
T12	0	154	0	0
T13	0	37	0	0
T14	0	117	0	0
T16	1572	0	0	0
T17	319	0	0	0
T18	1586	1	0	0
T153	0	4	0	0
T174	0	4	0	0
T175	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	563723717	7991	0	0
CgEnOn_A	563723717	5730	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563723717	7991	0	0
T1	691371	41	0	0
T2	146119	1	0	0
T3	996431	14	0	0
T4	86802	1	0	0
T5	2034	1	0	0
T9	203917	1	0	0
T10	260078	3	0	0
T16	5904	1	0	0
T17	1329	1	0	0
T18	6463	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	563723717	5730	0	0
T1	691371	33	0	0
T2	146119	0	0	0
T3	996431	8	0	0
T4	86802	0	0	0
T5	2034	0	0	0
T9	203917	0	0	0
T10	260078	0	0	0
T12	0	160	0	0
T13	0	40	0	0
T14	0	120	0	0
T16	5904	0	0	0
T17	1329	0	0	0
T18	6463	1	0	0
T72	0	1	0	0
T153	0	5	0	0
T174	0	4	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	286531413	7924	0	0
CgEnOn_A	286531413	5663	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286531413	7924	0	0
T1	337062	39	0	0
T2	73063	1	0	0
T3	500255	13	0	0
T4	54921	1	0	0
T5	1017	1	0	0
T9	101964	1	0	0
T10	130045	3	0	0
T16	2952	1	0	0
T17	664	1	0	0
T18	3232	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	286531413	5663	0	0
T1	337062	31	0	0
T2	73063	0	0	0
T3	500255	7	0	0
T4	54921	0	0	0
T5	1017	0	0	0
T9	101964	0	0	0
T10	130045	0	0	0
T12	0	160	0	0
T13	0	38	0	0
T14	0	122	0	0
T16	2952	0	0	0
T17	664	0	0	0
T18	3232	1	0	0
T72	0	1	0	0
T153	0	4	0	0
T174	0	3	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T3,T18
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	596868204	4345	0	0
CgEnOn_A	596868204	4344	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	4345	0	0
T1	714201	22	0	0
T2	152212	0	0	0
T3	103918	13	0	0
T4	120420	0	0	0
T5	2119	0	0	0
T9	212421	0	0	0
T10	270924	7	0	0
T11	0	19	0	0
T12	0	77	0	0
T13	0	47	0	0
T14	0	113	0	0
T16	6151	0	0	0
T17	1384	0	0	0
T18	6732	1	0	0
T72	0	1	0	0
T118	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	4344	0	0
T1	714201	22	0	0
T2	152212	0	0	0
T3	103918	13	0	0
T4	120420	0	0	0
T5	2119	0	0	0
T9	212421	0	0	0
T10	270924	7	0	0
T11	0	19	0	0
T12	0	77	0	0
T13	0	47	0	0
T14	0	113	0	0
T16	6151	0	0	0
T17	1384	0	0	0
T18	6732	1	0	0
T72	0	1	0	0
T118	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T3,T18
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	596868204	4198	0	0
CgEnOn_A	596868204	4197	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	4198	0	0
T1	714201	25	0	0
T2	152212	0	0	0
T3	103918	14	0	0
T4	120420	0	0	0
T5	2119	0	0	0
T9	212421	0	0	0
T10	270924	7	0	0
T11	0	11	0	0
T12	0	71	0	0
T13	0	51	0	0
T14	0	117	0	0
T16	6151	0	0	0
T17	1384	0	0	0
T18	6732	1	0	0
T72	0	1	0	0
T118	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	4197	0	0
T1	714201	25	0	0
T2	152212	0	0	0
T3	103918	14	0	0
T4	120420	0	0	0
T5	2119	0	0	0
T9	212421	0	0	0
T10	270924	7	0	0
T11	0	11	0	0
T12	0	71	0	0
T13	0	51	0	0
T14	0	117	0	0
T16	6151	0	0	0
T17	1384	0	0	0
T18	6732	1	0	0
T72	0	1	0	0
T118	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T3,T18
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	596868204	4359	0	0
CgEnOn_A	596868204	4358	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	4359	0	0
T1	714201	16	0	0
T2	152212	0	0	0
T3	103918	15	0	0
T4	120420	0	0	0
T5	2119	0	0	0
T9	212421	0	0	0
T10	270924	8	0	0
T11	0	17	0	0
T12	0	81	0	0
T13	0	59	0	0
T14	0	105	0	0
T16	6151	0	0	0
T17	1384	0	0	0
T18	6732	1	0	0
T72	0	1	0	0
T118	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	4358	0	0
T1	714201	16	0	0
T2	152212	0	0	0
T3	103918	15	0	0
T4	120420	0	0	0
T5	2119	0	0	0
T9	212421	0	0	0
T10	270924	8	0	0
T11	0	17	0	0
T12	0	81	0	0
T13	0	59	0	0
T14	0	105	0	0
T16	6151	0	0	0
T17	1384	0	0	0
T18	6732	1	0	0
T72	0	1	0	0
T118	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T3,T18
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	596868204	4388	0	0
CgEnOn_A	596868204	4387	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	4388	0	0
T1	714201	17	0	0
T2	152212	0	0	0
T3	103918	16	0	0
T4	120420	0	0	0
T5	2119	0	0	0
T9	212421	0	0	0
T10	270924	10	0	0
T11	0	14	0	0
T12	0	80	0	0
T13	0	58	0	0
T14	0	113	0	0
T16	6151	0	0	0
T17	1384	0	0	0
T18	6732	1	0	0
T72	0	1	0	0
T118	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596868204	4387	0	0
T1	714201	17	0	0
T2	152212	0	0	0
T3	103918	16	0	0
T4	120420	0	0	0
T5	2119	0	0	0
T9	212421	0	0	0
T10	270924	10	0	0
T11	0	14	0	0
T12	0	80	0	0
T13	0	58	0	0
T14	0	113	0	0
T16	6151	0	0	0
T17	1384	0	0	0
T18	6732	1	0	0
T72	0	1	0	0
T118	0	5	0	0