Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	622765	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3687830

1

T6

162

T7

34

T26

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1057512	1			T6	15		T7	20		T26	18
values[0x0]	1494086	1			T6	157		T7	18		T26	17
values[0x1]	1758997	1			T6	159		T7	23		T26	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3972097

1

T6

217

T7

34

T26

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16273	1			T6	2		T26	1		T44	1
valid_sources[0x01]	16508	1			T25	1		T3	240		T11	5
valid_sources[0x02]	15562	1			T6	1		T1	20		T20	56
valid_sources[0x03]	17886	1			T88	20		T1	23		T3	211
valid_sources[0x04]	15422	1			T6	2		T128	5		T4	3
valid_sources[0x05]	16223	1			T7	1		T1	6		T3	244
valid_sources[0x06]	15723	1			T1	8		T21	1		T3	263
valid_sources[0x07]	16163	1			T6	2		T26	3		T41	1
valid_sources[0x08]	16936	1			T6	1		T1	29		T21	1
valid_sources[0x09]	18713	1			T7	1		T1	4		T3	233
valid_sources[0x0a]	16104	1			T6	1		T46	1		T1	5
valid_sources[0x0b]	16833	1			T6	2		T7	1		T21	1
valid_sources[0x0c]	17892	1			T6	1		T46	1		T1	3
valid_sources[0x0d]	15978	1			T6	2		T4	4		T91	3
valid_sources[0x0e]	17745	1			T6	2		T7	1		T4	4
valid_sources[0x0f]	16426	1			T129	2		T87	2		T1	34
valid_sources[0x10]	17270	1			T6	2		T128	1		T1	9
valid_sources[0x11]	15544	1			T6	2		T7	1		T35	7
valid_sources[0x12]	17442	1			T6	1		T46	1		T1	1
valid_sources[0x13]	16251	1			T43	1		T41	1		T129	2
valid_sources[0x14]	18214	1			T6	2		T1	5		T22	15
valid_sources[0x15]	17336	1			T6	1		T45	6		T1	18
valid_sources[0x16]	16800	1			T6	1		T7	1		T1	1
valid_sources[0x17]	16498	1			T6	2		T128	1		T4	2
valid_sources[0x18]	16237	1			T6	2		T7	1		T46	3
valid_sources[0x19]	16558	1			T26	2		T41	3		T129	1
valid_sources[0x1a]	16095	1			T7	1		T26	1		T1	4
valid_sources[0x1b]	16939	1			T6	1		T26	2		T1	10
valid_sources[0x1c]	17039	1			T46	9		T1	7		T25	3
valid_sources[0x1d]	15414	1			T6	5		T1	17		T25	2
valid_sources[0x1e]	16553	1			T128	4		T129	2		T46	4
valid_sources[0x1f]	17426	1			T7	1		T128	3		T46	1
valid_sources[0x20]	17443	1			T6	1		T1	13		T3	273
valid_sources[0x21]	16786	1			T6	3		T36	2		T1	28
valid_sources[0x22]	17008	1			T6	1		T7	1		T3	219
valid_sources[0x23]	17546	1			T6	3		T43	1		T41	2
valid_sources[0x24]	18033	1			T1	5		T21	2		T3	235
valid_sources[0x25]	16599	1			T6	3		T128	1		T87	5
valid_sources[0x26]	16433	1			T6	3		T45	20		T4	5
valid_sources[0x27]	18112	1			T6	1		T1	25		T3	234
valid_sources[0x28]	15784	1			T6	3		T36	1		T1	11
valid_sources[0x29]	16375	1			T6	2		T1	25		T22	3
valid_sources[0x2a]	16795	1			T6	1		T1	5		T3	207
valid_sources[0x2b]	16319	1			T6	1		T7	1		T4	1
valid_sources[0x2c]	17476	1			T7	1		T44	8		T1	28
valid_sources[0x2d]	16686	1			T6	1		T1	8		T22	5
valid_sources[0x2e]	16568	1			T6	1		T7	1		T21	1
valid_sources[0x2f]	18179	1			T7	1		T128	1		T36	2
valid_sources[0x30]	16700	1			T6	3		T29	14		T41	2
valid_sources[0x31]	16319	1			T43	1		T21	1		T3	234
valid_sources[0x32]	16780	1			T6	1		T46	1		T21	1
valid_sources[0x33]	17038	1			T41	2		T46	2		T1	1
valid_sources[0x34]	15742	1			T6	2		T128	5		T1	9
valid_sources[0x35]	17234	1			T6	1		T129	1		T46	1
valid_sources[0x36]	18509	1			T6	3		T43	1		T21	1
valid_sources[0x37]	17850	1			T6	2		T7	1		T5	940
valid_sources[0x38]	16411	1			T6	1		T7	1		T41	1
valid_sources[0x39]	16867	1			T6	1		T43	1		T46	1
valid_sources[0x3a]	17076	1			T6	5		T35	4		T1	6
valid_sources[0x3b]	17114	1			T4	9		T1	5		T25	2
valid_sources[0x3c]	16814	1			T3	220		T11	2		T85	10
valid_sources[0x3d]	16602	1			T6	2		T7	1		T4	3
valid_sources[0x3e]	17544	1			T6	2		T44	7		T1	16
valid_sources[0x3f]	17112	1			T26	1		T45	19		T46	1
valid_sources[0x40]	17192	1			T6	1		T4	13		T1	19
valid_sources[0x41]	15487	1			T6	1		T44	4		T3	208
valid_sources[0x42]	16820	1			T6	2		T36	4		T1	8
valid_sources[0x43]	16034	1			T41	1		T3	255		T11	8
valid_sources[0x44]	15849	1			T6	2		T1	40		T3	256
valid_sources[0x45]	16468	1			T6	3		T21	1		T3	233
valid_sources[0x46]	15666	1			T6	1		T7	1		T36	1
valid_sources[0x47]	17005	1			T1	1		T3	245		T11	12
valid_sources[0x48]	16036	1			T7	1		T41	2		T1	2
valid_sources[0x49]	14731	1			T7	2		T41	1		T46	1
valid_sources[0x4a]	15192	1			T6	2		T44	8		T129	2
valid_sources[0x4b]	17008	1			T6	2		T1	4		T21	1
valid_sources[0x4c]	17124	1			T6	1		T4	11		T1	8
valid_sources[0x4d]	19054	1			T26	9		T46	2		T1	26
valid_sources[0x4e]	17450	1			T6	2		T26	1		T46	1
valid_sources[0x4f]	17259	1			T6	1		T41	5		T36	1
valid_sources[0x50]	16336	1			T6	2		T1	12		T21	2
valid_sources[0x51]	16275	1			T6	2		T1	5		T25	2
valid_sources[0x52]	17424	1			T6	2		T1	9		T3	231
valid_sources[0x53]	17129	1			T6	1		T4	40		T3	261
valid_sources[0x54]	15764	1			T6	1		T7	1		T41	1
valid_sources[0x55]	16900	1			T6	3		T128	3		T87	1
valid_sources[0x56]	16242	1			T6	3		T1	4		T21	1
valid_sources[0x57]	16407	1			T6	1		T7	1		T3	243
valid_sources[0x58]	17165	1			T25	1		T3	265		T11	6
valid_sources[0x59]	16549	1			T6	1		T7	1		T1	53
valid_sources[0x5a]	16312	1			T26	2		T1	8		T21	1
valid_sources[0x5b]	16170	1			T6	3		T7	1		T1	9
valid_sources[0x5c]	15748	1			T1	1		T21	1		T3	226
valid_sources[0x5d]	17540	1			T6	1		T1	13		T3	264
valid_sources[0x5e]	17931	1			T7	3		T4	2		T1	4
valid_sources[0x5f]	16818	1			T88	11		T1	9		T3	252
valid_sources[0x60]	17801	1			T6	2		T7	1		T26	5
valid_sources[0x61]	16658	1			T6	2		T45	2		T21	1
valid_sources[0x62]	16296	1			T3	231		T11	4		T83	1
valid_sources[0x63]	17847	1			T6	1		T1	3		T3	214
valid_sources[0x64]	17926	1			T6	3		T4	3		T87	4
valid_sources[0x65]	17458	1			T6	1		T1	16		T22	5
valid_sources[0x66]	15780	1			T6	3		T87	8		T1	7
valid_sources[0x67]	16750	1			T35	2		T36	1		T91	39
valid_sources[0x68]	18530	1			T6	1		T32	4		T1	19
valid_sources[0x69]	18780	1			T6	3		T129	2		T1	14
valid_sources[0x6a]	16617	1			T1	2		T3	223		T11	6
valid_sources[0x6b]	16221	1			T21	1		T25	2		T3	232
valid_sources[0x6c]	16671	1			T4	36		T21	1		T3	282
valid_sources[0x6d]	15974	1			T1	5		T22	3		T25	2
valid_sources[0x6e]	18348	1			T6	2		T129	1		T4	7
valid_sources[0x6f]	17397	1			T6	2		T7	1		T44	1
valid_sources[0x70]	16369	1			T6	1		T7	1		T1	9
valid_sources[0x71]	16562	1			T6	1		T26	1		T46	2
valid_sources[0x72]	16833	1			T36	1		T46	3		T1	27
valid_sources[0x73]	16645	1			T6	1		T4	6		T1	6
valid_sources[0x74]	16073	1			T6	2		T7	1		T1	11
valid_sources[0x75]	17632	1			T6	2		T7	1		T45	2
valid_sources[0x76]	16795	1			T7	1		T1	20		T21	1
valid_sources[0x77]	16142	1			T6	2		T4	14		T21	1
valid_sources[0x78]	17111	1			T128	3		T46	1		T1	2
valid_sources[0x79]	16286	1			T6	1		T36	1		T1	10
valid_sources[0x7a]	15740	1			T128	2		T3	235		T11	12
valid_sources[0x7b]	17385	1			T6	4		T1	3		T25	1
valid_sources[0x7c]	16423	1			T6	1		T1	1		T3	260
valid_sources[0x7d]	17984	1			T128	3		T4	29		T1	10
valid_sources[0x7e]	19744	1			T6	1		T41	3		T21	1
valid_sources[0x7f]	15989	1			T6	1		T4	6		T1	4
valid_sources[0x80]	16643	1			T6	4		T41	1		T1	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

930915

1

T6

6

T7

14

T26

12

values[0x0]

all_enables

biggest_size

1401896

1

T6

103

T7

11

T26

6

values[0x1]

all_enables

biggest_size

1355019

1

T6

53

T7

9

T26

4