Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T4,T5
1	0	Covered	T8,T27,T28
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	903457817	13865	0	0
GateOpen_A	903457817	19946	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903457817	13865	0	0
T1	0	80	0	0
T2	0	84	0	0
T8	4552	26	0	0
T21	0	4	0	0
T24	0	4	0	0
T25	0	4	0	0
T26	16696	0	0	0
T27	20312	14	0	0
T28	9315	28	0	0
T29	3999	0	0	0
T30	4120	0	0	0
T31	5260	0	0	0
T32	3297	0	0	0
T43	6468	0	0	0
T44	32677	0	0	0
T45	0	4	0	0
T46	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	903457817	19946	0	0
T6	307141	4	0	0
T7	19142	0	0	0
T8	4552	30	0	0
T26	16696	4	0	0
T27	20312	18	0	0
T28	9315	32	0	0
T29	3999	4	0	0
T30	4120	0	0	0
T31	5260	0	0	0
T32	3297	0	0	0
T42	0	4	0	0
T43	0	4	0	0
T44	0	4	0	0
T45	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T4,T5
1	0	Covered	T8,T27,T28
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	99634147	3244	0	0
GateOpen_A	99634147	4762	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99634147	3244	0	0
T1	0	20	0	0
T2	0	20	0	0
T8	499	7	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	1881	0	0	0
T27	2223	3	0	0
T28	1022	7	0	0
T29	429	0	0	0
T30	458	0	0	0
T31	581	0	0	0
T32	350	0	0	0
T43	725	0	0	0
T44	3785	0	0	0
T45	0	1	0	0
T46	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99634147	4762	0	0
T6	32191	1	0	0
T7	2227	0	0	0
T8	499	8	0	0
T26	1881	1	0	0
T27	2223	4	0	0
T28	1022	8	0	0
T29	429	1	0	0
T30	458	0	0	0
T31	581	0	0	0
T32	350	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T4,T5
1	0	Covered	T8,T27,T28
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	199269093	3516	0	0
GateOpen_A	199269093	5034	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199269093	3516	0	0
T1	0	21	0	0
T2	0	22	0	0
T8	998	7	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	3762	0	0	0
T27	4446	3	0	0
T28	2043	7	0	0
T29	858	0	0	0
T30	915	0	0	0
T31	1161	0	0	0
T32	700	0	0	0
T43	1450	0	0	0
T44	7573	0	0	0
T45	0	1	0	0
T46	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199269093	5034	0	0
T6	64382	1	0	0
T7	4453	0	0	0
T8	998	8	0	0
T26	3762	1	0	0
T27	4446	4	0	0
T28	2043	8	0	0
T29	858	1	0	0
T30	915	0	0	0
T31	1161	0	0	0
T32	700	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T4,T5
1	0	Covered	T8,T27,T28
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	399449754	3554	0	0
GateOpen_A	399449754	5076	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399449754	3554	0	0
T1	0	20	0	0
T2	0	21	0	0
T8	2019	7	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	7368	0	0	0
T27	8971	3	0	0
T28	4206	7	0	0
T29	1808	0	0	0
T30	1831	0	0	0
T31	2345	0	0	0
T32	1498	0	0	0
T43	2862	0	0	0
T44	14212	0	0	0
T45	0	1	0	0
T46	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399449754	5076	0	0
T6	128856	1	0	0
T7	8308	0	0	0
T8	2019	8	0	0
T26	7368	1	0	0
T27	8971	4	0	0
T28	4206	8	0	0
T29	1808	1	0	0
T30	1831	0	0	0
T31	2345	0	0	0
T32	1498	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T45,T4,T5
1	0	Covered	T8,T27,T28
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	205104823	3551	0	0
GateOpen_A	205104823	5074	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205104823	3551	0	0
T1	0	19	0	0
T2	0	21	0	0
T8	1036	5	0	0
T21	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	3685	0	0	0
T27	4672	5	0	0
T28	2044	7	0	0
T29	904	0	0	0
T30	916	0	0	0
T31	1173	0	0	0
T32	749	0	0	0
T43	1431	0	0	0
T44	7107	0	0	0
T45	0	1	0	0
T46	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205104823	5074	0	0
T6	81712	1	0	0
T7	4154	0	0	0
T8	1036	6	0	0
T26	3685	1	0	0
T27	4672	6	0	0
T28	2044	8	0	0
T29	904	1	0	0
T30	916	0	0	0
T31	1173	0	0	0
T32	749	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0