Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	797306740	76399	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	797306740	76399	0	0
T1	4043605	1004	0	0
T2	966525	296	0	0
T3	0	844	0	0
T11	0	224	0	0
T12	0	109	0	0
T13	0	434	0	0
T14	0	697	0	0
T15	0	135	0	0
T16	0	2764	0	0
T17	0	489	0	0
T18	11205	0	0	0
T19	167200	0	0	0
T20	8885	0	0	0
T21	12360	0	0	0
T22	96160	0	0	0
T23	491305	0	0	0
T24	10615	0	0	0
T25	5020	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159461348	11196	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	11196	0	0
T1	808721	149	0	0
T2	193305	44	0	0
T3	0	134	0	0
T11	0	32	0	0
T12	0	21	0	0
T13	0	72	0	0
T14	0	104	0	0
T15	0	22	0	0
T16	0	408	0	0
T17	0	63	0	0
T18	2241	0	0	0
T19	33440	0	0	0
T20	1777	0	0	0
T21	2472	0	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	0	0	0
T25	1004	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159461348	15360	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	15360	0	0
T1	808721	204	0	0
T2	193305	61	0	0
T3	0	170	0	0
T11	0	45	0	0
T12	0	21	0	0
T13	0	87	0	0
T14	0	143	0	0
T15	0	28	0	0
T16	0	557	0	0
T17	0	96	0	0
T18	2241	0	0	0
T19	33440	0	0	0
T20	1777	0	0	0
T21	2472	0	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	0	0	0
T25	1004	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159461348	23487	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	23487	0	0
T1	808721	328	0	0
T2	193305	95	0	0
T3	0	237	0	0
T11	0	68	0	0
T12	0	25	0	0
T13	0	115	0	0
T14	0	226	0	0
T15	0	35	0	0
T16	0	907	0	0
T17	0	161	0	0
T18	2241	0	0	0
T19	33440	0	0	0
T20	1777	0	0	0
T21	2472	0	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	0	0	0
T25	1004	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159461348	10992	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	10992	0	0
T1	808721	127	0	0
T2	193305	37	0	0
T3	0	133	0	0
T11	0	32	0	0
T12	0	21	0	0
T13	0	72	0	0
T14	0	89	0	0
T15	0	22	0	0
T16	0	352	0	0
T17	0	72	0	0
T18	2241	0	0	0
T19	33440	0	0	0
T20	1777	0	0	0
T21	2472	0	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	0	0	0
T25	1004	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159461348	15364	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159461348	15364	0	0
T1	808721	196	0	0
T2	193305	59	0	0
T3	0	170	0	0
T11	0	47	0	0
T12	0	21	0	0
T13	0	88	0	0
T14	0	135	0	0
T15	0	28	0	0
T16	0	540	0	0
T17	0	97	0	0
T18	2241	0	0	0
T19	33440	0	0	0
T20	1777	0	0	0
T21	2472	0	0	0
T22	19232	0	0	0
T23	98261	0	0	0
T24	2123	0	0	0
T25	1004	0	0	0