Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T8 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
T28 |
28 |
28 |
0 |
0 |
T29 |
28 |
28 |
0 |
0 |
T30 |
28 |
28 |
0 |
0 |
T31 |
28 |
28 |
0 |
0 |
T32 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T6 |
4442842 |
4437836 |
0 |
0 |
T7 |
134388 |
132040 |
0 |
0 |
T8 |
41822 |
39314 |
0 |
0 |
T26 |
118909 |
115617 |
0 |
0 |
T27 |
138773 |
136650 |
0 |
0 |
T28 |
65238 |
61583 |
0 |
0 |
T29 |
47799 |
42209 |
0 |
0 |
T30 |
45526 |
42829 |
0 |
0 |
T31 |
63769 |
60490 |
0 |
0 |
T32 |
40454 |
35021 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
956768088 |
940382286 |
0 |
14490 |
T6 |
1060614 |
1059366 |
0 |
18 |
T7 |
12456 |
12198 |
0 |
18 |
T8 |
7020 |
6546 |
0 |
18 |
T26 |
11046 |
10686 |
0 |
18 |
T27 |
7242 |
7104 |
0 |
18 |
T28 |
7170 |
6750 |
0 |
18 |
T29 |
10734 |
9348 |
0 |
18 |
T30 |
9606 |
8958 |
0 |
18 |
T31 |
14652 |
13794 |
0 |
18 |
T32 |
9270 |
7908 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T6 |
1163318 |
1161836 |
0 |
21 |
T7 |
47072 |
46132 |
0 |
21 |
T8 |
12747 |
11809 |
0 |
21 |
T26 |
41749 |
40423 |
0 |
21 |
T27 |
52537 |
51568 |
0 |
21 |
T28 |
22147 |
20658 |
0 |
21 |
T29 |
12918 |
11246 |
0 |
21 |
T30 |
12661 |
11805 |
0 |
21 |
T31 |
16997 |
16001 |
0 |
21 |
T32 |
10824 |
9234 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
194886 |
0 |
0 |
T6 |
680924 |
4 |
0 |
0 |
T7 |
47072 |
228 |
0 |
0 |
T8 |
12747 |
63 |
0 |
0 |
T26 |
41749 |
156 |
0 |
0 |
T27 |
52537 |
104 |
0 |
0 |
T28 |
22147 |
47 |
0 |
0 |
T29 |
12918 |
34 |
0 |
0 |
T30 |
12661 |
85 |
0 |
0 |
T31 |
16997 |
106 |
0 |
0 |
T32 |
10824 |
14 |
0 |
0 |
T43 |
0 |
34 |
0 |
0 |
T44 |
18062 |
141 |
0 |
0 |
T87 |
0 |
119 |
0 |
0 |
T88 |
0 |
147 |
0 |
0 |
T89 |
0 |
32 |
0 |
0 |
T90 |
0 |
37 |
0 |
0 |
T91 |
0 |
23 |
0 |
0 |
T128 |
0 |
108 |
0 |
0 |
T129 |
0 |
30 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T6 |
2218910 |
2216595 |
0 |
0 |
T7 |
74860 |
73671 |
0 |
0 |
T8 |
22055 |
20920 |
0 |
0 |
T26 |
66114 |
64469 |
0 |
0 |
T27 |
78994 |
77939 |
0 |
0 |
T28 |
35921 |
34136 |
0 |
0 |
T29 |
24147 |
21576 |
0 |
0 |
T30 |
23259 |
22027 |
0 |
0 |
T31 |
32120 |
30656 |
0 |
0 |
T32 |
20360 |
17840 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T26,T30 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T26,T30 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T26,T30 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T26,T30 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T26,T30 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T26,T30 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T26,T30 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T26,T30 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399449316 |
394977064 |
0 |
0 |
T6 |
128856 |
128653 |
0 |
0 |
T7 |
8308 |
8145 |
0 |
0 |
T8 |
2019 |
1870 |
0 |
0 |
T26 |
7367 |
7136 |
0 |
0 |
T27 |
8971 |
8795 |
0 |
0 |
T28 |
4205 |
3947 |
0 |
0 |
T29 |
1808 |
1577 |
0 |
0 |
T30 |
1831 |
1710 |
0 |
0 |
T31 |
2345 |
2210 |
0 |
0 |
T32 |
1498 |
1281 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399449316 |
394970419 |
0 |
2415 |
T6 |
128856 |
128650 |
0 |
3 |
T7 |
8308 |
8142 |
0 |
3 |
T8 |
2019 |
1867 |
0 |
3 |
T26 |
7367 |
7133 |
0 |
3 |
T27 |
8971 |
8792 |
0 |
3 |
T28 |
4205 |
3944 |
0 |
3 |
T29 |
1808 |
1574 |
0 |
3 |
T30 |
1831 |
1707 |
0 |
3 |
T31 |
2345 |
2207 |
0 |
3 |
T32 |
1498 |
1278 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399449316 |
27979 |
0 |
0 |
T7 |
8308 |
61 |
0 |
0 |
T8 |
2019 |
0 |
0 |
0 |
T26 |
7367 |
37 |
0 |
0 |
T27 |
8971 |
0 |
0 |
0 |
T28 |
4205 |
0 |
0 |
0 |
T29 |
1808 |
0 |
0 |
0 |
T30 |
1831 |
21 |
0 |
0 |
T31 |
2345 |
0 |
0 |
0 |
T32 |
1498 |
3 |
0 |
0 |
T43 |
0 |
16 |
0 |
0 |
T44 |
14212 |
85 |
0 |
0 |
T87 |
0 |
56 |
0 |
0 |
T88 |
0 |
48 |
0 |
0 |
T128 |
0 |
41 |
0 |
0 |
T129 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T30,T32 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T30,T32 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T30,T32 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T30,T32 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T32 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T32 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T32 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T30,T32 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156730381 |
0 |
2415 |
T6 |
176769 |
176561 |
0 |
3 |
T7 |
2076 |
2033 |
0 |
3 |
T8 |
1170 |
1091 |
0 |
3 |
T26 |
1841 |
1781 |
0 |
3 |
T27 |
1207 |
1184 |
0 |
3 |
T28 |
1195 |
1125 |
0 |
3 |
T29 |
1789 |
1558 |
0 |
3 |
T30 |
1601 |
1493 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1545 |
1318 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
17448 |
0 |
0 |
T7 |
2076 |
35 |
0 |
0 |
T8 |
1170 |
0 |
0 |
0 |
T26 |
1841 |
0 |
0 |
0 |
T27 |
1207 |
0 |
0 |
0 |
T28 |
1195 |
0 |
0 |
0 |
T29 |
1789 |
0 |
0 |
0 |
T30 |
1601 |
3 |
0 |
0 |
T31 |
2442 |
0 |
0 |
0 |
T32 |
1545 |
3 |
0 |
0 |
T43 |
0 |
6 |
0 |
0 |
T44 |
1925 |
30 |
0 |
0 |
T87 |
0 |
39 |
0 |
0 |
T88 |
0 |
50 |
0 |
0 |
T90 |
0 |
37 |
0 |
0 |
T91 |
0 |
23 |
0 |
0 |
T128 |
0 |
32 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T26,T30 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T26,T30 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T26,T30 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T7,T26,T30 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T26,T30 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T26,T30 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T26,T30 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T7,T26,T30 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156730381 |
0 |
2415 |
T6 |
176769 |
176561 |
0 |
3 |
T7 |
2076 |
2033 |
0 |
3 |
T8 |
1170 |
1091 |
0 |
3 |
T26 |
1841 |
1781 |
0 |
3 |
T27 |
1207 |
1184 |
0 |
3 |
T28 |
1195 |
1125 |
0 |
3 |
T29 |
1789 |
1558 |
0 |
3 |
T30 |
1601 |
1493 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1545 |
1318 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
19928 |
0 |
0 |
T7 |
2076 |
40 |
0 |
0 |
T8 |
1170 |
0 |
0 |
0 |
T26 |
1841 |
36 |
0 |
0 |
T27 |
1207 |
0 |
0 |
0 |
T28 |
1195 |
0 |
0 |
0 |
T29 |
1789 |
0 |
0 |
0 |
T30 |
1601 |
19 |
0 |
0 |
T31 |
2442 |
0 |
0 |
0 |
T32 |
1545 |
0 |
0 |
0 |
T43 |
0 |
12 |
0 |
0 |
T44 |
1925 |
26 |
0 |
0 |
T87 |
0 |
24 |
0 |
0 |
T88 |
0 |
49 |
0 |
0 |
T89 |
0 |
32 |
0 |
0 |
T128 |
0 |
35 |
0 |
0 |
T129 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
424841123 |
0 |
0 |
T6 |
170231 |
170133 |
0 |
0 |
T7 |
8653 |
8541 |
0 |
0 |
T8 |
2097 |
2071 |
0 |
0 |
T26 |
7675 |
7535 |
0 |
0 |
T27 |
10288 |
10205 |
0 |
0 |
T28 |
3888 |
3762 |
0 |
0 |
T29 |
1883 |
1785 |
0 |
0 |
T30 |
1907 |
1867 |
0 |
0 |
T31 |
2442 |
2416 |
0 |
0 |
T32 |
1559 |
1448 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
424841123 |
0 |
0 |
T6 |
170231 |
170133 |
0 |
0 |
T7 |
8653 |
8541 |
0 |
0 |
T8 |
2097 |
2071 |
0 |
0 |
T26 |
7675 |
7535 |
0 |
0 |
T27 |
10288 |
10205 |
0 |
0 |
T28 |
3888 |
3762 |
0 |
0 |
T29 |
1883 |
1785 |
0 |
0 |
T30 |
1907 |
1867 |
0 |
0 |
T31 |
2442 |
2416 |
0 |
0 |
T32 |
1559 |
1448 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399449316 |
397178556 |
0 |
0 |
T6 |
128856 |
128763 |
0 |
0 |
T7 |
8308 |
8200 |
0 |
0 |
T8 |
2019 |
1994 |
0 |
0 |
T26 |
7367 |
7232 |
0 |
0 |
T27 |
8971 |
8891 |
0 |
0 |
T28 |
4205 |
4084 |
0 |
0 |
T29 |
1808 |
1714 |
0 |
0 |
T30 |
1831 |
1792 |
0 |
0 |
T31 |
2345 |
2320 |
0 |
0 |
T32 |
1498 |
1390 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399449316 |
397178556 |
0 |
0 |
T6 |
128856 |
128763 |
0 |
0 |
T7 |
8308 |
8200 |
0 |
0 |
T8 |
2019 |
1994 |
0 |
0 |
T26 |
7367 |
7232 |
0 |
0 |
T27 |
8971 |
8891 |
0 |
0 |
T28 |
4205 |
4084 |
0 |
0 |
T29 |
1808 |
1714 |
0 |
0 |
T30 |
1831 |
1792 |
0 |
0 |
T31 |
2345 |
2320 |
0 |
0 |
T32 |
1498 |
1390 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
199268693 |
199268693 |
0 |
0 |
T6 |
64382 |
64382 |
0 |
0 |
T7 |
4452 |
4452 |
0 |
0 |
T8 |
997 |
997 |
0 |
0 |
T26 |
3761 |
3761 |
0 |
0 |
T27 |
4446 |
4446 |
0 |
0 |
T28 |
2042 |
2042 |
0 |
0 |
T29 |
857 |
857 |
0 |
0 |
T30 |
914 |
914 |
0 |
0 |
T31 |
1160 |
1160 |
0 |
0 |
T32 |
699 |
699 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
199268693 |
199268693 |
0 |
0 |
T6 |
64382 |
64382 |
0 |
0 |
T7 |
4452 |
4452 |
0 |
0 |
T8 |
997 |
997 |
0 |
0 |
T26 |
3761 |
3761 |
0 |
0 |
T27 |
4446 |
4446 |
0 |
0 |
T28 |
2042 |
2042 |
0 |
0 |
T29 |
857 |
857 |
0 |
0 |
T30 |
914 |
914 |
0 |
0 |
T31 |
1160 |
1160 |
0 |
0 |
T32 |
699 |
699 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
99633745 |
99633745 |
0 |
0 |
T6 |
32191 |
32191 |
0 |
0 |
T7 |
2226 |
2226 |
0 |
0 |
T8 |
499 |
499 |
0 |
0 |
T26 |
1881 |
1881 |
0 |
0 |
T27 |
2223 |
2223 |
0 |
0 |
T28 |
1021 |
1021 |
0 |
0 |
T29 |
429 |
429 |
0 |
0 |
T30 |
457 |
457 |
0 |
0 |
T31 |
580 |
580 |
0 |
0 |
T32 |
350 |
350 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
99633745 |
99633745 |
0 |
0 |
T6 |
32191 |
32191 |
0 |
0 |
T7 |
2226 |
2226 |
0 |
0 |
T8 |
499 |
499 |
0 |
0 |
T26 |
1881 |
1881 |
0 |
0 |
T27 |
2223 |
2223 |
0 |
0 |
T28 |
1021 |
1021 |
0 |
0 |
T29 |
429 |
429 |
0 |
0 |
T30 |
457 |
457 |
0 |
0 |
T31 |
580 |
580 |
0 |
0 |
T32 |
350 |
350 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
205104417 |
203959805 |
0 |
0 |
T6 |
81712 |
81666 |
0 |
0 |
T7 |
4153 |
4100 |
0 |
0 |
T8 |
1035 |
1023 |
0 |
0 |
T26 |
3684 |
3616 |
0 |
0 |
T27 |
4672 |
4632 |
0 |
0 |
T28 |
2043 |
1983 |
0 |
0 |
T29 |
904 |
857 |
0 |
0 |
T30 |
916 |
897 |
0 |
0 |
T31 |
1173 |
1160 |
0 |
0 |
T32 |
748 |
695 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
205104417 |
203959805 |
0 |
0 |
T6 |
81712 |
81666 |
0 |
0 |
T7 |
4153 |
4100 |
0 |
0 |
T8 |
1035 |
1023 |
0 |
0 |
T26 |
3684 |
3616 |
0 |
0 |
T27 |
4672 |
4632 |
0 |
0 |
T28 |
2043 |
1983 |
0 |
0 |
T29 |
904 |
857 |
0 |
0 |
T30 |
916 |
897 |
0 |
0 |
T31 |
1173 |
1160 |
0 |
0 |
T32 |
748 |
695 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156730381 |
0 |
2415 |
T6 |
176769 |
176561 |
0 |
3 |
T7 |
2076 |
2033 |
0 |
3 |
T8 |
1170 |
1091 |
0 |
3 |
T26 |
1841 |
1781 |
0 |
3 |
T27 |
1207 |
1184 |
0 |
3 |
T28 |
1195 |
1125 |
0 |
3 |
T29 |
1789 |
1558 |
0 |
3 |
T30 |
1601 |
1493 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1545 |
1318 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156730381 |
0 |
2415 |
T6 |
176769 |
176561 |
0 |
3 |
T7 |
2076 |
2033 |
0 |
3 |
T8 |
1170 |
1091 |
0 |
3 |
T26 |
1841 |
1781 |
0 |
3 |
T27 |
1207 |
1184 |
0 |
3 |
T28 |
1195 |
1125 |
0 |
3 |
T29 |
1789 |
1558 |
0 |
3 |
T30 |
1601 |
1493 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1545 |
1318 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156730381 |
0 |
2415 |
T6 |
176769 |
176561 |
0 |
3 |
T7 |
2076 |
2033 |
0 |
3 |
T8 |
1170 |
1091 |
0 |
3 |
T26 |
1841 |
1781 |
0 |
3 |
T27 |
1207 |
1184 |
0 |
3 |
T28 |
1195 |
1125 |
0 |
3 |
T29 |
1789 |
1558 |
0 |
3 |
T30 |
1601 |
1493 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1545 |
1318 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156730381 |
0 |
2415 |
T6 |
176769 |
176561 |
0 |
3 |
T7 |
2076 |
2033 |
0 |
3 |
T8 |
1170 |
1091 |
0 |
3 |
T26 |
1841 |
1781 |
0 |
3 |
T27 |
1207 |
1184 |
0 |
3 |
T28 |
1195 |
1125 |
0 |
3 |
T29 |
1789 |
1558 |
0 |
3 |
T30 |
1601 |
1493 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1545 |
1318 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156730381 |
0 |
2415 |
T6 |
176769 |
176561 |
0 |
3 |
T7 |
2076 |
2033 |
0 |
3 |
T8 |
1170 |
1091 |
0 |
3 |
T26 |
1841 |
1781 |
0 |
3 |
T27 |
1207 |
1184 |
0 |
3 |
T28 |
1195 |
1125 |
0 |
3 |
T29 |
1789 |
1558 |
0 |
3 |
T30 |
1601 |
1493 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1545 |
1318 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156730381 |
0 |
2415 |
T6 |
176769 |
176561 |
0 |
3 |
T7 |
2076 |
2033 |
0 |
3 |
T8 |
1170 |
1091 |
0 |
3 |
T26 |
1841 |
1781 |
0 |
3 |
T27 |
1207 |
1184 |
0 |
3 |
T28 |
1195 |
1125 |
0 |
3 |
T29 |
1789 |
1558 |
0 |
3 |
T30 |
1601 |
1493 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1545 |
1318 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159461348 |
156737154 |
0 |
0 |
T6 |
176769 |
176564 |
0 |
0 |
T7 |
2076 |
2036 |
0 |
0 |
T8 |
1170 |
1094 |
0 |
0 |
T26 |
1841 |
1784 |
0 |
0 |
T27 |
1207 |
1187 |
0 |
0 |
T28 |
1195 |
1128 |
0 |
0 |
T29 |
1789 |
1561 |
0 |
0 |
T30 |
1601 |
1496 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1545 |
1321 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422491740 |
0 |
2415 |
T6 |
170231 |
170016 |
0 |
3 |
T7 |
8653 |
8481 |
0 |
3 |
T8 |
2097 |
1940 |
0 |
3 |
T26 |
7675 |
7432 |
0 |
3 |
T27 |
10288 |
10102 |
0 |
3 |
T28 |
3888 |
3616 |
0 |
3 |
T29 |
1883 |
1639 |
0 |
3 |
T30 |
1907 |
1778 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1559 |
1330 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
32554 |
0 |
0 |
T6 |
170231 |
1 |
0 |
0 |
T7 |
8653 |
23 |
0 |
0 |
T8 |
2097 |
20 |
0 |
0 |
T26 |
7675 |
21 |
0 |
0 |
T27 |
10288 |
29 |
0 |
0 |
T28 |
3888 |
13 |
0 |
0 |
T29 |
1883 |
9 |
0 |
0 |
T30 |
1907 |
12 |
0 |
0 |
T31 |
2442 |
27 |
0 |
0 |
T32 |
1559 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422491740 |
0 |
2415 |
T6 |
170231 |
170016 |
0 |
3 |
T7 |
8653 |
8481 |
0 |
3 |
T8 |
2097 |
1940 |
0 |
3 |
T26 |
7675 |
7432 |
0 |
3 |
T27 |
10288 |
10102 |
0 |
3 |
T28 |
3888 |
3616 |
0 |
3 |
T29 |
1883 |
1639 |
0 |
3 |
T30 |
1907 |
1778 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1559 |
1330 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
32576 |
0 |
0 |
T6 |
170231 |
1 |
0 |
0 |
T7 |
8653 |
23 |
0 |
0 |
T8 |
2097 |
13 |
0 |
0 |
T26 |
7675 |
26 |
0 |
0 |
T27 |
10288 |
29 |
0 |
0 |
T28 |
3888 |
12 |
0 |
0 |
T29 |
1883 |
8 |
0 |
0 |
T30 |
1907 |
11 |
0 |
0 |
T31 |
2442 |
28 |
0 |
0 |
T32 |
1559 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422491740 |
0 |
2415 |
T6 |
170231 |
170016 |
0 |
3 |
T7 |
8653 |
8481 |
0 |
3 |
T8 |
2097 |
1940 |
0 |
3 |
T26 |
7675 |
7432 |
0 |
3 |
T27 |
10288 |
10102 |
0 |
3 |
T28 |
3888 |
3616 |
0 |
3 |
T29 |
1883 |
1639 |
0 |
3 |
T30 |
1907 |
1778 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1559 |
1330 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
32081 |
0 |
0 |
T6 |
170231 |
1 |
0 |
0 |
T7 |
8653 |
21 |
0 |
0 |
T8 |
2097 |
17 |
0 |
0 |
T26 |
7675 |
17 |
0 |
0 |
T27 |
10288 |
17 |
0 |
0 |
T28 |
3888 |
13 |
0 |
0 |
T29 |
1883 |
7 |
0 |
0 |
T30 |
1907 |
11 |
0 |
0 |
T31 |
2442 |
28 |
0 |
0 |
T32 |
1559 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422491740 |
0 |
2415 |
T6 |
170231 |
170016 |
0 |
3 |
T7 |
8653 |
8481 |
0 |
3 |
T8 |
2097 |
1940 |
0 |
3 |
T26 |
7675 |
7432 |
0 |
3 |
T27 |
10288 |
10102 |
0 |
3 |
T28 |
3888 |
3616 |
0 |
3 |
T29 |
1883 |
1639 |
0 |
3 |
T30 |
1907 |
1778 |
0 |
3 |
T31 |
2442 |
2299 |
0 |
3 |
T32 |
1559 |
1330 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
32320 |
0 |
0 |
T6 |
170231 |
1 |
0 |
0 |
T7 |
8653 |
25 |
0 |
0 |
T8 |
2097 |
13 |
0 |
0 |
T26 |
7675 |
19 |
0 |
0 |
T27 |
10288 |
29 |
0 |
0 |
T28 |
3888 |
9 |
0 |
0 |
T29 |
1883 |
10 |
0 |
0 |
T30 |
1907 |
8 |
0 |
0 |
T31 |
2442 |
23 |
0 |
0 |
T32 |
1559 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
T29 |
1 |
1 |
0 |
0 |
T30 |
1 |
1 |
0 |
0 |
T31 |
1 |
1 |
0 |
0 |
T32 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
427231722 |
422498429 |
0 |
0 |
T6 |
170231 |
170019 |
0 |
0 |
T7 |
8653 |
8484 |
0 |
0 |
T8 |
2097 |
1943 |
0 |
0 |
T26 |
7675 |
7435 |
0 |
0 |
T27 |
10288 |
10105 |
0 |
0 |
T28 |
3888 |
3619 |
0 |
0 |
T29 |
1883 |
1642 |
0 |
0 |
T30 |
1907 |
1781 |
0 |
0 |
T31 |
2442 |
2302 |
0 |
0 |
T32 |
1559 |
1333 |
0 |
0 |